1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_HW_H_ 5 #define _IGC_HW_H_ 6 7 #include <linux/types.h> 8 #include <linux/if_ether.h> 9 #include <linux/netdevice.h> 10 11 #include "igc_regs.h" 12 #include "igc_defines.h" 13 #include "igc_mac.h" 14 #include "igc_phy.h" 15 #include "igc_nvm.h" 16 #include "igc_i225.h" 17 #include "igc_base.h" 18 19 #define IGC_DEV_ID_I225_LM 0x15F2 20 #define IGC_DEV_ID_I225_V 0x15F3 21 #define IGC_DEV_ID_I225_I 0x15F8 22 #define IGC_DEV_ID_I220_V 0x15F7 23 #define IGC_DEV_ID_I225_K 0x3100 24 #define IGC_DEV_ID_I225_K2 0x3101 25 #define IGC_DEV_ID_I225_LMVP 0x5502 26 #define IGC_DEV_ID_I225_IT 0x0D9F 27 #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD 28 29 /* Function pointers for the MAC. */ 30 struct igc_mac_operations { 31 s32 (*check_for_link)(struct igc_hw *hw); 32 s32 (*reset_hw)(struct igc_hw *hw); 33 s32 (*init_hw)(struct igc_hw *hw); 34 s32 (*setup_physical_interface)(struct igc_hw *hw); 35 void (*rar_set)(struct igc_hw *hw, u8 *address, u32 index); 36 s32 (*read_mac_addr)(struct igc_hw *hw); 37 s32 (*get_speed_and_duplex)(struct igc_hw *hw, u16 *speed, 38 u16 *duplex); 39 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask); 40 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask); 41 }; 42 43 enum igc_mac_type { 44 igc_undefined = 0, 45 igc_i225, 46 igc_num_macs /* List is 1-based, so subtract 1 for true count. */ 47 }; 48 49 enum igc_phy_type { 50 igc_phy_unknown = 0, 51 igc_phy_none, 52 igc_phy_i225, 53 }; 54 55 enum igc_media_type { 56 igc_media_type_unknown = 0, 57 igc_media_type_copper = 1, 58 igc_num_media_types 59 }; 60 61 enum igc_nvm_type { 62 igc_nvm_unknown = 0, 63 igc_nvm_eeprom_spi, 64 igc_nvm_flash_hw, 65 igc_nvm_invm, 66 }; 67 68 struct igc_info { 69 s32 (*get_invariants)(struct igc_hw *hw); 70 struct igc_mac_operations *mac_ops; 71 const struct igc_phy_operations *phy_ops; 72 struct igc_nvm_operations *nvm_ops; 73 }; 74 75 extern const struct igc_info igc_base_info; 76 77 struct igc_mac_info { 78 struct igc_mac_operations ops; 79 80 u8 addr[ETH_ALEN]; 81 u8 perm_addr[ETH_ALEN]; 82 83 enum igc_mac_type type; 84 85 u32 mc_filter_type; 86 87 u16 mta_reg_count; 88 u16 uta_reg_count; 89 90 u32 mta_shadow[MAX_MTA_REG]; 91 u16 rar_entry_count; 92 93 u8 forced_speed_duplex; 94 95 bool asf_firmware_present; 96 bool arc_subsystem_valid; 97 98 bool autoneg; 99 bool autoneg_failed; 100 bool get_link_status; 101 }; 102 103 struct igc_nvm_operations { 104 s32 (*acquire)(struct igc_hw *hw); 105 s32 (*read)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 106 void (*release)(struct igc_hw *hw); 107 s32 (*write)(struct igc_hw *hw, u16 offset, u16 i, u16 *data); 108 s32 (*update)(struct igc_hw *hw); 109 s32 (*validate)(struct igc_hw *hw); 110 s32 (*valid_led_default)(struct igc_hw *hw, u16 *data); 111 }; 112 113 struct igc_phy_operations { 114 s32 (*acquire)(struct igc_hw *hw); 115 s32 (*check_reset_block)(struct igc_hw *hw); 116 s32 (*force_speed_duplex)(struct igc_hw *hw); 117 s32 (*get_phy_info)(struct igc_hw *hw); 118 s32 (*read_reg)(struct igc_hw *hw, u32 address, u16 *data); 119 void (*release)(struct igc_hw *hw); 120 s32 (*reset)(struct igc_hw *hw); 121 s32 (*write_reg)(struct igc_hw *hw, u32 address, u16 data); 122 }; 123 124 struct igc_nvm_info { 125 struct igc_nvm_operations ops; 126 enum igc_nvm_type type; 127 128 u32 flash_bank_size; 129 u32 flash_base_addr; 130 131 u16 word_size; 132 u16 delay_usec; 133 u16 address_bits; 134 u16 opcode_bits; 135 u16 page_size; 136 }; 137 138 struct igc_phy_info { 139 struct igc_phy_operations ops; 140 141 enum igc_phy_type type; 142 143 u32 addr; 144 u32 id; 145 u32 reset_delay_us; /* in usec */ 146 u32 revision; 147 148 enum igc_media_type media_type; 149 150 u16 autoneg_advertised; 151 u16 autoneg_mask; 152 153 u8 mdix; 154 155 bool is_mdix; 156 bool reset_disable; 157 bool speed_downgraded; 158 bool autoneg_wait_to_complete; 159 }; 160 161 struct igc_bus_info { 162 u16 func; 163 u16 pci_cmd_word; 164 }; 165 166 enum igc_fc_mode { 167 igc_fc_none = 0, 168 igc_fc_rx_pause, 169 igc_fc_tx_pause, 170 igc_fc_full, 171 igc_fc_default = 0xFF 172 }; 173 174 struct igc_fc_info { 175 u32 high_water; /* Flow control high-water mark */ 176 u32 low_water; /* Flow control low-water mark */ 177 u16 pause_time; /* Flow control pause timer */ 178 bool send_xon; /* Flow control send XON */ 179 bool strict_ieee; /* Strict IEEE mode */ 180 enum igc_fc_mode current_mode; /* Type of flow control */ 181 enum igc_fc_mode requested_mode; 182 }; 183 184 struct igc_dev_spec_base { 185 bool clear_semaphore_once; 186 bool eee_enable; 187 }; 188 189 struct igc_hw { 190 void *back; 191 192 u8 __iomem *hw_addr; 193 unsigned long io_base; 194 195 struct igc_mac_info mac; 196 struct igc_fc_info fc; 197 struct igc_nvm_info nvm; 198 struct igc_phy_info phy; 199 200 struct igc_bus_info bus; 201 202 union { 203 struct igc_dev_spec_base _base; 204 } dev_spec; 205 206 u16 device_id; 207 u16 subsystem_vendor_id; 208 u16 subsystem_device_id; 209 u16 vendor_id; 210 211 u8 revision_id; 212 }; 213 214 /* Statistics counters collected by the MAC */ 215 struct igc_hw_stats { 216 u64 crcerrs; 217 u64 algnerrc; 218 u64 symerrs; 219 u64 rxerrc; 220 u64 mpc; 221 u64 scc; 222 u64 ecol; 223 u64 mcc; 224 u64 latecol; 225 u64 colc; 226 u64 dc; 227 u64 tncrs; 228 u64 sec; 229 u64 cexterr; 230 u64 rlec; 231 u64 xonrxc; 232 u64 xontxc; 233 u64 xoffrxc; 234 u64 xofftxc; 235 u64 fcruc; 236 u64 prc64; 237 u64 prc127; 238 u64 prc255; 239 u64 prc511; 240 u64 prc1023; 241 u64 prc1522; 242 u64 gprc; 243 u64 bprc; 244 u64 mprc; 245 u64 gptc; 246 u64 gorc; 247 u64 gotc; 248 u64 rnbc; 249 u64 ruc; 250 u64 rfc; 251 u64 roc; 252 u64 rjc; 253 u64 mgprc; 254 u64 mgpdc; 255 u64 mgptc; 256 u64 tor; 257 u64 tot; 258 u64 tpr; 259 u64 tpt; 260 u64 ptc64; 261 u64 ptc127; 262 u64 ptc255; 263 u64 ptc511; 264 u64 ptc1023; 265 u64 ptc1522; 266 u64 mptc; 267 u64 bptc; 268 u64 tsctc; 269 u64 tsctfc; 270 u64 iac; 271 u64 htdpmc; 272 u64 rpthc; 273 u64 hgptc; 274 u64 hgorc; 275 u64 hgotc; 276 u64 lenerrs; 277 u64 scvpc; 278 u64 hrmpc; 279 u64 doosync; 280 u64 o2bgptc; 281 u64 o2bspc; 282 u64 b2ospc; 283 u64 b2ogprc; 284 }; 285 286 struct net_device *igc_get_hw_dev(struct igc_hw *hw); 287 #define hw_dbg(format, arg...) \ 288 netdev_dbg(igc_get_hw_dev(hw), format, ##arg) 289 290 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 291 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value); 292 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 293 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value); 294 295 #endif /* _IGC_HW_H_ */ 296