1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/perf_event.h> 3 #include <linux/export.h> 4 #include <linux/types.h> 5 #include <linux/init.h> 6 #include <linux/slab.h> 7 #include <linux/delay.h> 8 #include <linux/jiffies.h> 9 #include <asm/apicdef.h> 10 #include <asm/nmi.h> 11 12 #include "../perf_event.h" 13 14 static DEFINE_PER_CPU(unsigned long, perf_nmi_tstamp); 15 static unsigned long perf_nmi_window; 16 17 /* AMD Event 0xFFF: Merge. Used with Large Increment per Cycle events */ 18 #define AMD_MERGE_EVENT ((0xFULL << 32) | 0xFFULL) 19 #define AMD_MERGE_EVENT_ENABLE (AMD_MERGE_EVENT | ARCH_PERFMON_EVENTSEL_ENABLE) 20 21 static __initconst const u64 amd_hw_cache_event_ids 22 [PERF_COUNT_HW_CACHE_MAX] 23 [PERF_COUNT_HW_CACHE_OP_MAX] 24 [PERF_COUNT_HW_CACHE_RESULT_MAX] = 25 { 26 [ C(L1D) ] = { 27 [ C(OP_READ) ] = { 28 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ 29 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */ 30 }, 31 [ C(OP_WRITE) ] = { 32 [ C(RESULT_ACCESS) ] = 0, 33 [ C(RESULT_MISS) ] = 0, 34 }, 35 [ C(OP_PREFETCH) ] = { 36 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */ 37 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */ 38 }, 39 }, 40 [ C(L1I ) ] = { 41 [ C(OP_READ) ] = { 42 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */ 43 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */ 44 }, 45 [ C(OP_WRITE) ] = { 46 [ C(RESULT_ACCESS) ] = -1, 47 [ C(RESULT_MISS) ] = -1, 48 }, 49 [ C(OP_PREFETCH) ] = { 50 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */ 51 [ C(RESULT_MISS) ] = 0, 52 }, 53 }, 54 [ C(LL ) ] = { 55 [ C(OP_READ) ] = { 56 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */ 57 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */ 58 }, 59 [ C(OP_WRITE) ] = { 60 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */ 61 [ C(RESULT_MISS) ] = 0, 62 }, 63 [ C(OP_PREFETCH) ] = { 64 [ C(RESULT_ACCESS) ] = 0, 65 [ C(RESULT_MISS) ] = 0, 66 }, 67 }, 68 [ C(DTLB) ] = { 69 [ C(OP_READ) ] = { 70 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */ 71 [ C(RESULT_MISS) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */ 72 }, 73 [ C(OP_WRITE) ] = { 74 [ C(RESULT_ACCESS) ] = 0, 75 [ C(RESULT_MISS) ] = 0, 76 }, 77 [ C(OP_PREFETCH) ] = { 78 [ C(RESULT_ACCESS) ] = 0, 79 [ C(RESULT_MISS) ] = 0, 80 }, 81 }, 82 [ C(ITLB) ] = { 83 [ C(OP_READ) ] = { 84 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */ 85 [ C(RESULT_MISS) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */ 86 }, 87 [ C(OP_WRITE) ] = { 88 [ C(RESULT_ACCESS) ] = -1, 89 [ C(RESULT_MISS) ] = -1, 90 }, 91 [ C(OP_PREFETCH) ] = { 92 [ C(RESULT_ACCESS) ] = -1, 93 [ C(RESULT_MISS) ] = -1, 94 }, 95 }, 96 [ C(BPU ) ] = { 97 [ C(OP_READ) ] = { 98 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */ 99 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */ 100 }, 101 [ C(OP_WRITE) ] = { 102 [ C(RESULT_ACCESS) ] = -1, 103 [ C(RESULT_MISS) ] = -1, 104 }, 105 [ C(OP_PREFETCH) ] = { 106 [ C(RESULT_ACCESS) ] = -1, 107 [ C(RESULT_MISS) ] = -1, 108 }, 109 }, 110 [ C(NODE) ] = { 111 [ C(OP_READ) ] = { 112 [ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */ 113 [ C(RESULT_MISS) ] = 0x98e9, /* CPU Request to Memory, r */ 114 }, 115 [ C(OP_WRITE) ] = { 116 [ C(RESULT_ACCESS) ] = -1, 117 [ C(RESULT_MISS) ] = -1, 118 }, 119 [ C(OP_PREFETCH) ] = { 120 [ C(RESULT_ACCESS) ] = -1, 121 [ C(RESULT_MISS) ] = -1, 122 }, 123 }, 124 }; 125 126 static __initconst const u64 amd_hw_cache_event_ids_f17h 127 [PERF_COUNT_HW_CACHE_MAX] 128 [PERF_COUNT_HW_CACHE_OP_MAX] 129 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 130 [C(L1D)] = { 131 [C(OP_READ)] = { 132 [C(RESULT_ACCESS)] = 0x0040, /* Data Cache Accesses */ 133 [C(RESULT_MISS)] = 0xc860, /* L2$ access from DC Miss */ 134 }, 135 [C(OP_WRITE)] = { 136 [C(RESULT_ACCESS)] = 0, 137 [C(RESULT_MISS)] = 0, 138 }, 139 [C(OP_PREFETCH)] = { 140 [C(RESULT_ACCESS)] = 0xff5a, /* h/w prefetch DC Fills */ 141 [C(RESULT_MISS)] = 0, 142 }, 143 }, 144 [C(L1I)] = { 145 [C(OP_READ)] = { 146 [C(RESULT_ACCESS)] = 0x0080, /* Instruction cache fetches */ 147 [C(RESULT_MISS)] = 0x0081, /* Instruction cache misses */ 148 }, 149 [C(OP_WRITE)] = { 150 [C(RESULT_ACCESS)] = -1, 151 [C(RESULT_MISS)] = -1, 152 }, 153 [C(OP_PREFETCH)] = { 154 [C(RESULT_ACCESS)] = 0, 155 [C(RESULT_MISS)] = 0, 156 }, 157 }, 158 [C(LL)] = { 159 [C(OP_READ)] = { 160 [C(RESULT_ACCESS)] = 0, 161 [C(RESULT_MISS)] = 0, 162 }, 163 [C(OP_WRITE)] = { 164 [C(RESULT_ACCESS)] = 0, 165 [C(RESULT_MISS)] = 0, 166 }, 167 [C(OP_PREFETCH)] = { 168 [C(RESULT_ACCESS)] = 0, 169 [C(RESULT_MISS)] = 0, 170 }, 171 }, 172 [C(DTLB)] = { 173 [C(OP_READ)] = { 174 [C(RESULT_ACCESS)] = 0xff45, /* All L2 DTLB accesses */ 175 [C(RESULT_MISS)] = 0xf045, /* L2 DTLB misses (PT walks) */ 176 }, 177 [C(OP_WRITE)] = { 178 [C(RESULT_ACCESS)] = 0, 179 [C(RESULT_MISS)] = 0, 180 }, 181 [C(OP_PREFETCH)] = { 182 [C(RESULT_ACCESS)] = 0, 183 [C(RESULT_MISS)] = 0, 184 }, 185 }, 186 [C(ITLB)] = { 187 [C(OP_READ)] = { 188 [C(RESULT_ACCESS)] = 0x0084, /* L1 ITLB misses, L2 ITLB hits */ 189 [C(RESULT_MISS)] = 0xff85, /* L1 ITLB misses, L2 misses */ 190 }, 191 [C(OP_WRITE)] = { 192 [C(RESULT_ACCESS)] = -1, 193 [C(RESULT_MISS)] = -1, 194 }, 195 [C(OP_PREFETCH)] = { 196 [C(RESULT_ACCESS)] = -1, 197 [C(RESULT_MISS)] = -1, 198 }, 199 }, 200 [C(BPU)] = { 201 [C(OP_READ)] = { 202 [C(RESULT_ACCESS)] = 0x00c2, /* Retired Branch Instr. */ 203 [C(RESULT_MISS)] = 0x00c3, /* Retired Mispredicted BI */ 204 }, 205 [C(OP_WRITE)] = { 206 [C(RESULT_ACCESS)] = -1, 207 [C(RESULT_MISS)] = -1, 208 }, 209 [C(OP_PREFETCH)] = { 210 [C(RESULT_ACCESS)] = -1, 211 [C(RESULT_MISS)] = -1, 212 }, 213 }, 214 [C(NODE)] = { 215 [C(OP_READ)] = { 216 [C(RESULT_ACCESS)] = 0, 217 [C(RESULT_MISS)] = 0, 218 }, 219 [C(OP_WRITE)] = { 220 [C(RESULT_ACCESS)] = -1, 221 [C(RESULT_MISS)] = -1, 222 }, 223 [C(OP_PREFETCH)] = { 224 [C(RESULT_ACCESS)] = -1, 225 [C(RESULT_MISS)] = -1, 226 }, 227 }, 228 }; 229 230 /* 231 * AMD Performance Monitor K7 and later, up to and including Family 16h: 232 */ 233 static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] = 234 { 235 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, 236 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 237 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x077d, 238 [PERF_COUNT_HW_CACHE_MISSES] = 0x077e, 239 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, 240 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, 241 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */ 242 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */ 243 }; 244 245 /* 246 * AMD Performance Monitor Family 17h and later: 247 */ 248 static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = 249 { 250 [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, 251 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, 252 [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60, 253 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, 254 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, 255 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x0287, 256 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187, 257 }; 258 259 static u64 amd_pmu_event_map(int hw_event) 260 { 261 if (boot_cpu_data.x86 >= 0x17) 262 return amd_f17h_perfmon_event_map[hw_event]; 263 264 return amd_perfmon_event_map[hw_event]; 265 } 266 267 /* 268 * Previously calculated offsets 269 */ 270 static unsigned int event_offsets[X86_PMC_IDX_MAX] __read_mostly; 271 static unsigned int count_offsets[X86_PMC_IDX_MAX] __read_mostly; 272 273 /* 274 * Legacy CPUs: 275 * 4 counters starting at 0xc0010000 each offset by 1 276 * 277 * CPUs with core performance counter extensions: 278 * 6 counters starting at 0xc0010200 each offset by 2 279 */ 280 static inline int amd_pmu_addr_offset(int index, bool eventsel) 281 { 282 int offset; 283 284 if (!index) 285 return index; 286 287 if (eventsel) 288 offset = event_offsets[index]; 289 else 290 offset = count_offsets[index]; 291 292 if (offset) 293 return offset; 294 295 if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) 296 offset = index; 297 else 298 offset = index << 1; 299 300 if (eventsel) 301 event_offsets[index] = offset; 302 else 303 count_offsets[index] = offset; 304 305 return offset; 306 } 307 308 /* 309 * AMD64 events are detected based on their event codes. 310 */ 311 static inline unsigned int amd_get_event_code(struct hw_perf_event *hwc) 312 { 313 return ((hwc->config >> 24) & 0x0f00) | (hwc->config & 0x00ff); 314 } 315 316 static inline bool amd_is_pair_event_code(struct hw_perf_event *hwc) 317 { 318 if (!(x86_pmu.flags & PMU_FL_PAIR)) 319 return false; 320 321 switch (amd_get_event_code(hwc)) { 322 case 0x003: return true; /* Retired SSE/AVX FLOPs */ 323 default: return false; 324 } 325 } 326 327 static int amd_core_hw_config(struct perf_event *event) 328 { 329 if (event->attr.exclude_host && event->attr.exclude_guest) 330 /* 331 * When HO == GO == 1 the hardware treats that as GO == HO == 0 332 * and will count in both modes. We don't want to count in that 333 * case so we emulate no-counting by setting US = OS = 0. 334 */ 335 event->hw.config &= ~(ARCH_PERFMON_EVENTSEL_USR | 336 ARCH_PERFMON_EVENTSEL_OS); 337 else if (event->attr.exclude_host) 338 event->hw.config |= AMD64_EVENTSEL_GUESTONLY; 339 else if (event->attr.exclude_guest) 340 event->hw.config |= AMD64_EVENTSEL_HOSTONLY; 341 342 if ((x86_pmu.flags & PMU_FL_PAIR) && amd_is_pair_event_code(&event->hw)) 343 event->hw.flags |= PERF_X86_EVENT_PAIR; 344 345 return 0; 346 } 347 348 static inline int amd_is_nb_event(struct hw_perf_event *hwc) 349 { 350 return (hwc->config & 0xe0) == 0xe0; 351 } 352 353 static inline int amd_has_nb(struct cpu_hw_events *cpuc) 354 { 355 struct amd_nb *nb = cpuc->amd_nb; 356 357 return nb && nb->nb_id != -1; 358 } 359 360 static int amd_pmu_hw_config(struct perf_event *event) 361 { 362 int ret; 363 364 /* pass precise event sampling to ibs: */ 365 if (event->attr.precise_ip && get_ibs_caps()) 366 return -ENOENT; 367 368 if (has_branch_stack(event)) 369 return -EOPNOTSUPP; 370 371 ret = x86_pmu_hw_config(event); 372 if (ret) 373 return ret; 374 375 if (event->attr.type == PERF_TYPE_RAW) 376 event->hw.config |= event->attr.config & AMD64_RAW_EVENT_MASK; 377 378 return amd_core_hw_config(event); 379 } 380 381 static void __amd_put_nb_event_constraints(struct cpu_hw_events *cpuc, 382 struct perf_event *event) 383 { 384 struct amd_nb *nb = cpuc->amd_nb; 385 int i; 386 387 /* 388 * need to scan whole list because event may not have 389 * been assigned during scheduling 390 * 391 * no race condition possible because event can only 392 * be removed on one CPU at a time AND PMU is disabled 393 * when we come here 394 */ 395 for (i = 0; i < x86_pmu.num_counters; i++) { 396 if (cmpxchg(nb->owners + i, event, NULL) == event) 397 break; 398 } 399 } 400 401 /* 402 * AMD64 NorthBridge events need special treatment because 403 * counter access needs to be synchronized across all cores 404 * of a package. Refer to BKDG section 3.12 405 * 406 * NB events are events measuring L3 cache, Hypertransport 407 * traffic. They are identified by an event code >= 0xe00. 408 * They measure events on the NorthBride which is shared 409 * by all cores on a package. NB events are counted on a 410 * shared set of counters. When a NB event is programmed 411 * in a counter, the data actually comes from a shared 412 * counter. Thus, access to those counters needs to be 413 * synchronized. 414 * 415 * We implement the synchronization such that no two cores 416 * can be measuring NB events using the same counters. Thus, 417 * we maintain a per-NB allocation table. The available slot 418 * is propagated using the event_constraint structure. 419 * 420 * We provide only one choice for each NB event based on 421 * the fact that only NB events have restrictions. Consequently, 422 * if a counter is available, there is a guarantee the NB event 423 * will be assigned to it. If no slot is available, an empty 424 * constraint is returned and scheduling will eventually fail 425 * for this event. 426 * 427 * Note that all cores attached the same NB compete for the same 428 * counters to host NB events, this is why we use atomic ops. Some 429 * multi-chip CPUs may have more than one NB. 430 * 431 * Given that resources are allocated (cmpxchg), they must be 432 * eventually freed for others to use. This is accomplished by 433 * calling __amd_put_nb_event_constraints() 434 * 435 * Non NB events are not impacted by this restriction. 436 */ 437 static struct event_constraint * 438 __amd_get_nb_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event, 439 struct event_constraint *c) 440 { 441 struct hw_perf_event *hwc = &event->hw; 442 struct amd_nb *nb = cpuc->amd_nb; 443 struct perf_event *old; 444 int idx, new = -1; 445 446 if (!c) 447 c = &unconstrained; 448 449 if (cpuc->is_fake) 450 return c; 451 452 /* 453 * detect if already present, if so reuse 454 * 455 * cannot merge with actual allocation 456 * because of possible holes 457 * 458 * event can already be present yet not assigned (in hwc->idx) 459 * because of successive calls to x86_schedule_events() from 460 * hw_perf_group_sched_in() without hw_perf_enable() 461 */ 462 for_each_set_bit(idx, c->idxmsk, x86_pmu.num_counters) { 463 if (new == -1 || hwc->idx == idx) 464 /* assign free slot, prefer hwc->idx */ 465 old = cmpxchg(nb->owners + idx, NULL, event); 466 else if (nb->owners[idx] == event) 467 /* event already present */ 468 old = event; 469 else 470 continue; 471 472 if (old && old != event) 473 continue; 474 475 /* reassign to this slot */ 476 if (new != -1) 477 cmpxchg(nb->owners + new, event, NULL); 478 new = idx; 479 480 /* already present, reuse */ 481 if (old == event) 482 break; 483 } 484 485 if (new == -1) 486 return &emptyconstraint; 487 488 return &nb->event_constraints[new]; 489 } 490 491 static struct amd_nb *amd_alloc_nb(int cpu) 492 { 493 struct amd_nb *nb; 494 int i; 495 496 nb = kzalloc_node(sizeof(struct amd_nb), GFP_KERNEL, cpu_to_node(cpu)); 497 if (!nb) 498 return NULL; 499 500 nb->nb_id = -1; 501 502 /* 503 * initialize all possible NB constraints 504 */ 505 for (i = 0; i < x86_pmu.num_counters; i++) { 506 __set_bit(i, nb->event_constraints[i].idxmsk); 507 nb->event_constraints[i].weight = 1; 508 } 509 return nb; 510 } 511 512 static int amd_pmu_cpu_prepare(int cpu) 513 { 514 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 515 516 WARN_ON_ONCE(cpuc->amd_nb); 517 518 if (!x86_pmu.amd_nb_constraints) 519 return 0; 520 521 cpuc->amd_nb = amd_alloc_nb(cpu); 522 if (!cpuc->amd_nb) 523 return -ENOMEM; 524 525 return 0; 526 } 527 528 static void amd_pmu_cpu_starting(int cpu) 529 { 530 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 531 void **onln = &cpuc->kfree_on_online[X86_PERF_KFREE_SHARED]; 532 struct amd_nb *nb; 533 int i, nb_id; 534 535 cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY; 536 537 if (!x86_pmu.amd_nb_constraints) 538 return; 539 540 nb_id = amd_get_nb_id(cpu); 541 WARN_ON_ONCE(nb_id == BAD_APICID); 542 543 for_each_online_cpu(i) { 544 nb = per_cpu(cpu_hw_events, i).amd_nb; 545 if (WARN_ON_ONCE(!nb)) 546 continue; 547 548 if (nb->nb_id == nb_id) { 549 *onln = cpuc->amd_nb; 550 cpuc->amd_nb = nb; 551 break; 552 } 553 } 554 555 cpuc->amd_nb->nb_id = nb_id; 556 cpuc->amd_nb->refcnt++; 557 } 558 559 static void amd_pmu_cpu_dead(int cpu) 560 { 561 struct cpu_hw_events *cpuhw; 562 563 if (!x86_pmu.amd_nb_constraints) 564 return; 565 566 cpuhw = &per_cpu(cpu_hw_events, cpu); 567 568 if (cpuhw->amd_nb) { 569 struct amd_nb *nb = cpuhw->amd_nb; 570 571 if (nb->nb_id == -1 || --nb->refcnt == 0) 572 kfree(nb); 573 574 cpuhw->amd_nb = NULL; 575 } 576 } 577 578 /* 579 * When a PMC counter overflows, an NMI is used to process the event and 580 * reset the counter. NMI latency can result in the counter being updated 581 * before the NMI can run, which can result in what appear to be spurious 582 * NMIs. This function is intended to wait for the NMI to run and reset 583 * the counter to avoid possible unhandled NMI messages. 584 */ 585 #define OVERFLOW_WAIT_COUNT 50 586 587 static void amd_pmu_wait_on_overflow(int idx) 588 { 589 unsigned int i; 590 u64 counter; 591 592 /* 593 * Wait for the counter to be reset if it has overflowed. This loop 594 * should exit very, very quickly, but just in case, don't wait 595 * forever... 596 */ 597 for (i = 0; i < OVERFLOW_WAIT_COUNT; i++) { 598 rdmsrl(x86_pmu_event_addr(idx), counter); 599 if (counter & (1ULL << (x86_pmu.cntval_bits - 1))) 600 break; 601 602 /* Might be in IRQ context, so can't sleep */ 603 udelay(1); 604 } 605 } 606 607 static void amd_pmu_disable_all(void) 608 { 609 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 610 int idx; 611 612 x86_pmu_disable_all(); 613 614 /* 615 * This shouldn't be called from NMI context, but add a safeguard here 616 * to return, since if we're in NMI context we can't wait for an NMI 617 * to reset an overflowed counter value. 618 */ 619 if (in_nmi()) 620 return; 621 622 /* 623 * Check each counter for overflow and wait for it to be reset by the 624 * NMI if it has overflowed. This relies on the fact that all active 625 * counters are always enabled when this function is caled and 626 * ARCH_PERFMON_EVENTSEL_INT is always set. 627 */ 628 for (idx = 0; idx < x86_pmu.num_counters; idx++) { 629 if (!test_bit(idx, cpuc->active_mask)) 630 continue; 631 632 amd_pmu_wait_on_overflow(idx); 633 } 634 } 635 636 static void amd_pmu_disable_event(struct perf_event *event) 637 { 638 x86_pmu_disable_event(event); 639 640 /* 641 * This can be called from NMI context (via x86_pmu_stop). The counter 642 * may have overflowed, but either way, we'll never see it get reset 643 * by the NMI if we're already in the NMI. And the NMI latency support 644 * below will take care of any pending NMI that might have been 645 * generated by the overflow. 646 */ 647 if (in_nmi()) 648 return; 649 650 amd_pmu_wait_on_overflow(event->hw.idx); 651 } 652 653 /* 654 * Because of NMI latency, if multiple PMC counters are active or other sources 655 * of NMIs are received, the perf NMI handler can handle one or more overflowed 656 * PMC counters outside of the NMI associated with the PMC overflow. If the NMI 657 * doesn't arrive at the LAPIC in time to become a pending NMI, then the kernel 658 * back-to-back NMI support won't be active. This PMC handler needs to take into 659 * account that this can occur, otherwise this could result in unknown NMI 660 * messages being issued. Examples of this is PMC overflow while in the NMI 661 * handler when multiple PMCs are active or PMC overflow while handling some 662 * other source of an NMI. 663 * 664 * Attempt to mitigate this by creating an NMI window in which un-handled NMIs 665 * received during this window will be claimed. This prevents extending the 666 * window past when it is possible that latent NMIs should be received. The 667 * per-CPU perf_nmi_tstamp will be set to the window end time whenever perf has 668 * handled a counter. When an un-handled NMI is received, it will be claimed 669 * only if arriving within that window. 670 */ 671 static int amd_pmu_handle_irq(struct pt_regs *regs) 672 { 673 int handled; 674 675 /* Process any counter overflows */ 676 handled = x86_pmu_handle_irq(regs); 677 678 /* 679 * If a counter was handled, record a timestamp such that un-handled 680 * NMIs will be claimed if arriving within that window. 681 */ 682 if (handled) { 683 this_cpu_write(perf_nmi_tstamp, jiffies + perf_nmi_window); 684 685 return handled; 686 } 687 688 if (time_after(jiffies, this_cpu_read(perf_nmi_tstamp))) 689 return NMI_DONE; 690 691 return NMI_HANDLED; 692 } 693 694 static struct event_constraint * 695 amd_get_event_constraints(struct cpu_hw_events *cpuc, int idx, 696 struct perf_event *event) 697 { 698 /* 699 * if not NB event or no NB, then no constraints 700 */ 701 if (!(amd_has_nb(cpuc) && amd_is_nb_event(&event->hw))) 702 return &unconstrained; 703 704 return __amd_get_nb_event_constraints(cpuc, event, NULL); 705 } 706 707 static void amd_put_event_constraints(struct cpu_hw_events *cpuc, 708 struct perf_event *event) 709 { 710 if (amd_has_nb(cpuc) && amd_is_nb_event(&event->hw)) 711 __amd_put_nb_event_constraints(cpuc, event); 712 } 713 714 PMU_FORMAT_ATTR(event, "config:0-7,32-35"); 715 PMU_FORMAT_ATTR(umask, "config:8-15" ); 716 PMU_FORMAT_ATTR(edge, "config:18" ); 717 PMU_FORMAT_ATTR(inv, "config:23" ); 718 PMU_FORMAT_ATTR(cmask, "config:24-31" ); 719 720 static struct attribute *amd_format_attr[] = { 721 &format_attr_event.attr, 722 &format_attr_umask.attr, 723 &format_attr_edge.attr, 724 &format_attr_inv.attr, 725 &format_attr_cmask.attr, 726 NULL, 727 }; 728 729 /* AMD Family 15h */ 730 731 #define AMD_EVENT_TYPE_MASK 0x000000F0ULL 732 733 #define AMD_EVENT_FP 0x00000000ULL ... 0x00000010ULL 734 #define AMD_EVENT_LS 0x00000020ULL ... 0x00000030ULL 735 #define AMD_EVENT_DC 0x00000040ULL ... 0x00000050ULL 736 #define AMD_EVENT_CU 0x00000060ULL ... 0x00000070ULL 737 #define AMD_EVENT_IC_DE 0x00000080ULL ... 0x00000090ULL 738 #define AMD_EVENT_EX_LS 0x000000C0ULL 739 #define AMD_EVENT_DE 0x000000D0ULL 740 #define AMD_EVENT_NB 0x000000E0ULL ... 0x000000F0ULL 741 742 /* 743 * AMD family 15h event code/PMC mappings: 744 * 745 * type = event_code & 0x0F0: 746 * 747 * 0x000 FP PERF_CTL[5:3] 748 * 0x010 FP PERF_CTL[5:3] 749 * 0x020 LS PERF_CTL[5:0] 750 * 0x030 LS PERF_CTL[5:0] 751 * 0x040 DC PERF_CTL[5:0] 752 * 0x050 DC PERF_CTL[5:0] 753 * 0x060 CU PERF_CTL[2:0] 754 * 0x070 CU PERF_CTL[2:0] 755 * 0x080 IC/DE PERF_CTL[2:0] 756 * 0x090 IC/DE PERF_CTL[2:0] 757 * 0x0A0 --- 758 * 0x0B0 --- 759 * 0x0C0 EX/LS PERF_CTL[5:0] 760 * 0x0D0 DE PERF_CTL[2:0] 761 * 0x0E0 NB NB_PERF_CTL[3:0] 762 * 0x0F0 NB NB_PERF_CTL[3:0] 763 * 764 * Exceptions: 765 * 766 * 0x000 FP PERF_CTL[3], PERF_CTL[5:3] (*) 767 * 0x003 FP PERF_CTL[3] 768 * 0x004 FP PERF_CTL[3], PERF_CTL[5:3] (*) 769 * 0x00B FP PERF_CTL[3] 770 * 0x00D FP PERF_CTL[3] 771 * 0x023 DE PERF_CTL[2:0] 772 * 0x02D LS PERF_CTL[3] 773 * 0x02E LS PERF_CTL[3,0] 774 * 0x031 LS PERF_CTL[2:0] (**) 775 * 0x043 CU PERF_CTL[2:0] 776 * 0x045 CU PERF_CTL[2:0] 777 * 0x046 CU PERF_CTL[2:0] 778 * 0x054 CU PERF_CTL[2:0] 779 * 0x055 CU PERF_CTL[2:0] 780 * 0x08F IC PERF_CTL[0] 781 * 0x187 DE PERF_CTL[0] 782 * 0x188 DE PERF_CTL[0] 783 * 0x0DB EX PERF_CTL[5:0] 784 * 0x0DC LS PERF_CTL[5:0] 785 * 0x0DD LS PERF_CTL[5:0] 786 * 0x0DE LS PERF_CTL[5:0] 787 * 0x0DF LS PERF_CTL[5:0] 788 * 0x1C0 EX PERF_CTL[5:3] 789 * 0x1D6 EX PERF_CTL[5:0] 790 * 0x1D8 EX PERF_CTL[5:0] 791 * 792 * (*) depending on the umask all FPU counters may be used 793 * (**) only one unitmask enabled at a time 794 */ 795 796 static struct event_constraint amd_f15_PMC0 = EVENT_CONSTRAINT(0, 0x01, 0); 797 static struct event_constraint amd_f15_PMC20 = EVENT_CONSTRAINT(0, 0x07, 0); 798 static struct event_constraint amd_f15_PMC3 = EVENT_CONSTRAINT(0, 0x08, 0); 799 static struct event_constraint amd_f15_PMC30 = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0); 800 static struct event_constraint amd_f15_PMC50 = EVENT_CONSTRAINT(0, 0x3F, 0); 801 static struct event_constraint amd_f15_PMC53 = EVENT_CONSTRAINT(0, 0x38, 0); 802 803 static struct event_constraint * 804 amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, int idx, 805 struct perf_event *event) 806 { 807 struct hw_perf_event *hwc = &event->hw; 808 unsigned int event_code = amd_get_event_code(hwc); 809 810 switch (event_code & AMD_EVENT_TYPE_MASK) { 811 case AMD_EVENT_FP: 812 switch (event_code) { 813 case 0x000: 814 if (!(hwc->config & 0x0000F000ULL)) 815 break; 816 if (!(hwc->config & 0x00000F00ULL)) 817 break; 818 return &amd_f15_PMC3; 819 case 0x004: 820 if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1) 821 break; 822 return &amd_f15_PMC3; 823 case 0x003: 824 case 0x00B: 825 case 0x00D: 826 return &amd_f15_PMC3; 827 } 828 return &amd_f15_PMC53; 829 case AMD_EVENT_LS: 830 case AMD_EVENT_DC: 831 case AMD_EVENT_EX_LS: 832 switch (event_code) { 833 case 0x023: 834 case 0x043: 835 case 0x045: 836 case 0x046: 837 case 0x054: 838 case 0x055: 839 return &amd_f15_PMC20; 840 case 0x02D: 841 return &amd_f15_PMC3; 842 case 0x02E: 843 return &amd_f15_PMC30; 844 case 0x031: 845 if (hweight_long(hwc->config & ARCH_PERFMON_EVENTSEL_UMASK) <= 1) 846 return &amd_f15_PMC20; 847 return &emptyconstraint; 848 case 0x1C0: 849 return &amd_f15_PMC53; 850 default: 851 return &amd_f15_PMC50; 852 } 853 case AMD_EVENT_CU: 854 case AMD_EVENT_IC_DE: 855 case AMD_EVENT_DE: 856 switch (event_code) { 857 case 0x08F: 858 case 0x187: 859 case 0x188: 860 return &amd_f15_PMC0; 861 case 0x0DB ... 0x0DF: 862 case 0x1D6: 863 case 0x1D8: 864 return &amd_f15_PMC50; 865 default: 866 return &amd_f15_PMC20; 867 } 868 case AMD_EVENT_NB: 869 /* moved to uncore.c */ 870 return &emptyconstraint; 871 default: 872 return &emptyconstraint; 873 } 874 } 875 876 static struct event_constraint pair_constraint; 877 878 static struct event_constraint * 879 amd_get_event_constraints_f17h(struct cpu_hw_events *cpuc, int idx, 880 struct perf_event *event) 881 { 882 struct hw_perf_event *hwc = &event->hw; 883 884 if (amd_is_pair_event_code(hwc)) 885 return &pair_constraint; 886 887 return &unconstrained; 888 } 889 890 static void amd_put_event_constraints_f17h(struct cpu_hw_events *cpuc, 891 struct perf_event *event) 892 { 893 struct hw_perf_event *hwc = &event->hw; 894 895 if (is_counter_pair(hwc)) 896 --cpuc->n_pair; 897 } 898 899 static ssize_t amd_event_sysfs_show(char *page, u64 config) 900 { 901 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT) | 902 (config & AMD64_EVENTSEL_EVENT) >> 24; 903 904 return x86_event_sysfs_show(page, config, event); 905 } 906 907 static __initconst const struct x86_pmu amd_pmu = { 908 .name = "AMD", 909 .handle_irq = amd_pmu_handle_irq, 910 .disable_all = amd_pmu_disable_all, 911 .enable_all = x86_pmu_enable_all, 912 .enable = x86_pmu_enable_event, 913 .disable = amd_pmu_disable_event, 914 .hw_config = amd_pmu_hw_config, 915 .schedule_events = x86_schedule_events, 916 .eventsel = MSR_K7_EVNTSEL0, 917 .perfctr = MSR_K7_PERFCTR0, 918 .addr_offset = amd_pmu_addr_offset, 919 .event_map = amd_pmu_event_map, 920 .max_events = ARRAY_SIZE(amd_perfmon_event_map), 921 .num_counters = AMD64_NUM_COUNTERS, 922 .cntval_bits = 48, 923 .cntval_mask = (1ULL << 48) - 1, 924 .apic = 1, 925 /* use highest bit to detect overflow */ 926 .max_period = (1ULL << 47) - 1, 927 .get_event_constraints = amd_get_event_constraints, 928 .put_event_constraints = amd_put_event_constraints, 929 930 .format_attrs = amd_format_attr, 931 .events_sysfs_show = amd_event_sysfs_show, 932 933 .cpu_prepare = amd_pmu_cpu_prepare, 934 .cpu_starting = amd_pmu_cpu_starting, 935 .cpu_dead = amd_pmu_cpu_dead, 936 937 .amd_nb_constraints = 1, 938 }; 939 940 static int __init amd_core_pmu_init(void) 941 { 942 u64 even_ctr_mask = 0ULL; 943 int i; 944 945 if (!boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) 946 return 0; 947 948 /* Avoid calculating the value each time in the NMI handler */ 949 perf_nmi_window = msecs_to_jiffies(100); 950 951 /* 952 * If core performance counter extensions exists, we must use 953 * MSR_F15H_PERF_CTL/MSR_F15H_PERF_CTR msrs. See also 954 * amd_pmu_addr_offset(). 955 */ 956 x86_pmu.eventsel = MSR_F15H_PERF_CTL; 957 x86_pmu.perfctr = MSR_F15H_PERF_CTR; 958 x86_pmu.num_counters = AMD64_NUM_COUNTERS_CORE; 959 /* 960 * AMD Core perfctr has separate MSRs for the NB events, see 961 * the amd/uncore.c driver. 962 */ 963 x86_pmu.amd_nb_constraints = 0; 964 965 if (boot_cpu_data.x86 == 0x15) { 966 pr_cont("Fam15h "); 967 x86_pmu.get_event_constraints = amd_get_event_constraints_f15h; 968 } 969 if (boot_cpu_data.x86 >= 0x17) { 970 pr_cont("Fam17h+ "); 971 /* 972 * Family 17h and compatibles have constraints for Large 973 * Increment per Cycle events: they may only be assigned an 974 * even numbered counter that has a consecutive adjacent odd 975 * numbered counter following it. 976 */ 977 for (i = 0; i < x86_pmu.num_counters - 1; i += 2) 978 even_ctr_mask |= 1 << i; 979 980 pair_constraint = (struct event_constraint) 981 __EVENT_CONSTRAINT(0, even_ctr_mask, 0, 982 x86_pmu.num_counters / 2, 0, 983 PERF_X86_EVENT_PAIR); 984 985 x86_pmu.get_event_constraints = amd_get_event_constraints_f17h; 986 x86_pmu.put_event_constraints = amd_put_event_constraints_f17h; 987 x86_pmu.perf_ctr_pair_en = AMD_MERGE_EVENT_ENABLE; 988 x86_pmu.flags |= PMU_FL_PAIR; 989 } 990 991 pr_cont("core perfctr, "); 992 return 0; 993 } 994 995 __init int amd_pmu_init(void) 996 { 997 int ret; 998 999 /* Performance-monitoring supported from K7 and later: */ 1000 if (boot_cpu_data.x86 < 6) 1001 return -ENODEV; 1002 1003 x86_pmu = amd_pmu; 1004 1005 ret = amd_core_pmu_init(); 1006 if (ret) 1007 return ret; 1008 1009 if (num_possible_cpus() == 1) { 1010 /* 1011 * No point in allocating data structures to serialize 1012 * against other CPUs, when there is only the one CPU. 1013 */ 1014 x86_pmu.amd_nb_constraints = 0; 1015 } 1016 1017 if (boot_cpu_data.x86 >= 0x17) 1018 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids_f17h, sizeof(hw_cache_event_ids)); 1019 else 1020 memcpy(hw_cache_event_ids, amd_hw_cache_event_ids, sizeof(hw_cache_event_ids)); 1021 1022 return 0; 1023 } 1024 1025 void amd_pmu_enable_virt(void) 1026 { 1027 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1028 1029 cpuc->perf_ctr_virt_mask = 0; 1030 1031 /* Reload all events */ 1032 amd_pmu_disable_all(); 1033 x86_pmu_enable_all(0); 1034 } 1035 EXPORT_SYMBOL_GPL(amd_pmu_enable_virt); 1036 1037 void amd_pmu_disable_virt(void) 1038 { 1039 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); 1040 1041 /* 1042 * We only mask out the Host-only bit so that host-only counting works 1043 * when SVM is disabled. If someone sets up a guest-only counter when 1044 * SVM is disabled the Guest-only bits still gets set and the counter 1045 * will not count anything. 1046 */ 1047 cpuc->perf_ctr_virt_mask = AMD64_EVENTSEL_HOSTONLY; 1048 1049 /* Reload all events */ 1050 amd_pmu_disable_all(); 1051 x86_pmu_enable_all(0); 1052 } 1053 EXPORT_SYMBOL_GPL(amd_pmu_disable_virt); 1054