1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 */ 7 #include <linux/etherdevice.h> 8 #include <linux/ethtool.h> 9 #include <linux/if_bridge.h> 10 #include <linux/if_ether.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/phy.h> 17 #include <linux/ptp_clock_kernel.h> 18 #include <linux/skbuff.h> 19 #include <linux/iopoll.h> 20 #include <net/arp.h> 21 #include <net/netevent.h> 22 #include <net/rtnetlink.h> 23 #include <net/switchdev.h> 24 25 #include "ocelot.h" 26 #include "ocelot_ace.h" 27 28 #define TABLE_UPDATE_SLEEP_US 10 29 #define TABLE_UPDATE_TIMEOUT_US 100000 30 31 /* MAC table entry types. 32 * ENTRYTYPE_NORMAL is subject to aging. 33 * ENTRYTYPE_LOCKED is not subject to aging. 34 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. 35 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. 36 */ 37 enum macaccess_entry_type { 38 ENTRYTYPE_NORMAL = 0, 39 ENTRYTYPE_LOCKED, 40 ENTRYTYPE_MACv4, 41 ENTRYTYPE_MACv6, 42 }; 43 44 struct ocelot_mact_entry { 45 u8 mac[ETH_ALEN]; 46 u16 vid; 47 enum macaccess_entry_type type; 48 }; 49 50 static inline u32 ocelot_mact_read_macaccess(struct ocelot *ocelot) 51 { 52 return ocelot_read(ocelot, ANA_TABLES_MACACCESS); 53 } 54 55 static inline int ocelot_mact_wait_for_completion(struct ocelot *ocelot) 56 { 57 u32 val; 58 59 return readx_poll_timeout(ocelot_mact_read_macaccess, 60 ocelot, val, 61 (val & ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M) == 62 MACACCESS_CMD_IDLE, 63 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 64 } 65 66 static void ocelot_mact_select(struct ocelot *ocelot, 67 const unsigned char mac[ETH_ALEN], 68 unsigned int vid) 69 { 70 u32 macl = 0, mach = 0; 71 72 /* Set the MAC address to handle and the vlan associated in a format 73 * understood by the hardware. 74 */ 75 mach |= vid << 16; 76 mach |= mac[0] << 8; 77 mach |= mac[1] << 0; 78 macl |= mac[2] << 24; 79 macl |= mac[3] << 16; 80 macl |= mac[4] << 8; 81 macl |= mac[5] << 0; 82 83 ocelot_write(ocelot, macl, ANA_TABLES_MACLDATA); 84 ocelot_write(ocelot, mach, ANA_TABLES_MACHDATA); 85 86 } 87 88 static int ocelot_mact_learn(struct ocelot *ocelot, int port, 89 const unsigned char mac[ETH_ALEN], 90 unsigned int vid, 91 enum macaccess_entry_type type) 92 { 93 ocelot_mact_select(ocelot, mac, vid); 94 95 /* Issue a write command */ 96 ocelot_write(ocelot, ANA_TABLES_MACACCESS_VALID | 97 ANA_TABLES_MACACCESS_DEST_IDX(port) | 98 ANA_TABLES_MACACCESS_ENTRYTYPE(type) | 99 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_LEARN), 100 ANA_TABLES_MACACCESS); 101 102 return ocelot_mact_wait_for_completion(ocelot); 103 } 104 105 static int ocelot_mact_forget(struct ocelot *ocelot, 106 const unsigned char mac[ETH_ALEN], 107 unsigned int vid) 108 { 109 ocelot_mact_select(ocelot, mac, vid); 110 111 /* Issue a forget command */ 112 ocelot_write(ocelot, 113 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_FORGET), 114 ANA_TABLES_MACACCESS); 115 116 return ocelot_mact_wait_for_completion(ocelot); 117 } 118 119 static void ocelot_mact_init(struct ocelot *ocelot) 120 { 121 /* Configure the learning mode entries attributes: 122 * - Do not copy the frame to the CPU extraction queues. 123 * - Use the vlan and mac_cpoy for dmac lookup. 124 */ 125 ocelot_rmw(ocelot, 0, 126 ANA_AGENCTRL_LEARN_CPU_COPY | ANA_AGENCTRL_IGNORE_DMAC_FLAGS 127 | ANA_AGENCTRL_LEARN_FWD_KILL 128 | ANA_AGENCTRL_LEARN_IGNORE_VLAN, 129 ANA_AGENCTRL); 130 131 /* Clear the MAC table */ 132 ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); 133 } 134 135 static void ocelot_vcap_enable(struct ocelot *ocelot, int port) 136 { 137 ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA | 138 ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa), 139 ANA_PORT_VCAP_S2_CFG, port); 140 } 141 142 static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) 143 { 144 return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); 145 } 146 147 static inline int ocelot_vlant_wait_for_completion(struct ocelot *ocelot) 148 { 149 u32 val; 150 151 return readx_poll_timeout(ocelot_vlant_read_vlanaccess, 152 ocelot, 153 val, 154 (val & ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M) == 155 ANA_TABLES_VLANACCESS_CMD_IDLE, 156 TABLE_UPDATE_SLEEP_US, TABLE_UPDATE_TIMEOUT_US); 157 } 158 159 static int ocelot_vlant_set_mask(struct ocelot *ocelot, u16 vid, u32 mask) 160 { 161 /* Select the VID to configure */ 162 ocelot_write(ocelot, ANA_TABLES_VLANTIDX_V_INDEX(vid), 163 ANA_TABLES_VLANTIDX); 164 /* Set the vlan port members mask and issue a write command */ 165 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(mask) | 166 ANA_TABLES_VLANACCESS_CMD_WRITE, 167 ANA_TABLES_VLANACCESS); 168 169 return ocelot_vlant_wait_for_completion(ocelot); 170 } 171 172 static void ocelot_vlan_mode(struct ocelot *ocelot, int port, 173 netdev_features_t features) 174 { 175 u32 val; 176 177 /* Filtering */ 178 val = ocelot_read(ocelot, ANA_VLANMASK); 179 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 180 val |= BIT(port); 181 else 182 val &= ~BIT(port); 183 ocelot_write(ocelot, val, ANA_VLANMASK); 184 } 185 186 void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, 187 bool vlan_aware) 188 { 189 struct ocelot_port *ocelot_port = ocelot->ports[port]; 190 u32 val; 191 192 if (vlan_aware) 193 val = ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 194 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1); 195 else 196 val = 0; 197 ocelot_rmw_gix(ocelot, val, 198 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 199 ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M, 200 ANA_PORT_VLAN_CFG, port); 201 202 if (vlan_aware && !ocelot_port->vid) 203 /* If port is vlan-aware and tagged, drop untagged and priority 204 * tagged frames. 205 */ 206 val = ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 207 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 208 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA; 209 else 210 val = 0; 211 ocelot_rmw_gix(ocelot, val, 212 ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA | 213 ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA | 214 ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA, 215 ANA_PORT_DROP_CFG, port); 216 217 if (vlan_aware) { 218 if (ocelot_port->vid) 219 /* Tag all frames except when VID == DEFAULT_VLAN */ 220 val |= REW_TAG_CFG_TAG_CFG(1); 221 else 222 /* Tag all frames */ 223 val |= REW_TAG_CFG_TAG_CFG(3); 224 } else { 225 /* Port tagging disabled. */ 226 val = REW_TAG_CFG_TAG_CFG(0); 227 } 228 ocelot_rmw_gix(ocelot, val, 229 REW_TAG_CFG_TAG_CFG_M, 230 REW_TAG_CFG, port); 231 } 232 EXPORT_SYMBOL(ocelot_port_vlan_filtering); 233 234 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port, 235 u16 vid) 236 { 237 struct ocelot_port *ocelot_port = ocelot->ports[port]; 238 239 if (ocelot_port->vid != vid) { 240 /* Always permit deleting the native VLAN (vid = 0) */ 241 if (ocelot_port->vid && vid) { 242 dev_err(ocelot->dev, 243 "Port already has a native VLAN: %d\n", 244 ocelot_port->vid); 245 return -EBUSY; 246 } 247 ocelot_port->vid = vid; 248 } 249 250 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_VID(vid), 251 REW_PORT_VLAN_CFG_PORT_VID_M, 252 REW_PORT_VLAN_CFG, port); 253 254 return 0; 255 } 256 257 /* Default vlan to clasify for untagged frames (may be zero) */ 258 static void ocelot_port_set_pvid(struct ocelot *ocelot, int port, u16 pvid) 259 { 260 struct ocelot_port *ocelot_port = ocelot->ports[port]; 261 262 ocelot_rmw_gix(ocelot, 263 ANA_PORT_VLAN_CFG_VLAN_VID(pvid), 264 ANA_PORT_VLAN_CFG_VLAN_VID_M, 265 ANA_PORT_VLAN_CFG, port); 266 267 ocelot_port->pvid = pvid; 268 } 269 270 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid, 271 bool untagged) 272 { 273 int ret; 274 275 /* Make the port a member of the VLAN */ 276 ocelot->vlan_mask[vid] |= BIT(port); 277 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 278 if (ret) 279 return ret; 280 281 /* Default ingress vlan classification */ 282 if (pvid) 283 ocelot_port_set_pvid(ocelot, port, vid); 284 285 /* Untagged egress vlan clasification */ 286 if (untagged) { 287 ret = ocelot_port_set_native_vlan(ocelot, port, vid); 288 if (ret) 289 return ret; 290 } 291 292 return 0; 293 } 294 EXPORT_SYMBOL(ocelot_vlan_add); 295 296 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid, 297 bool untagged) 298 { 299 struct ocelot_port_private *priv = netdev_priv(dev); 300 struct ocelot_port *ocelot_port = &priv->port; 301 struct ocelot *ocelot = ocelot_port->ocelot; 302 int port = priv->chip_port; 303 int ret; 304 305 ret = ocelot_vlan_add(ocelot, port, vid, pvid, untagged); 306 if (ret) 307 return ret; 308 309 /* Add the port MAC address to with the right VLAN information */ 310 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, vid, 311 ENTRYTYPE_LOCKED); 312 313 return 0; 314 } 315 316 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid) 317 { 318 struct ocelot_port *ocelot_port = ocelot->ports[port]; 319 int ret; 320 321 /* Stop the port from being a member of the vlan */ 322 ocelot->vlan_mask[vid] &= ~BIT(port); 323 ret = ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 324 if (ret) 325 return ret; 326 327 /* Ingress */ 328 if (ocelot_port->pvid == vid) 329 ocelot_port_set_pvid(ocelot, port, 0); 330 331 /* Egress */ 332 if (ocelot_port->vid == vid) 333 ocelot_port_set_native_vlan(ocelot, port, 0); 334 335 return 0; 336 } 337 EXPORT_SYMBOL(ocelot_vlan_del); 338 339 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid) 340 { 341 struct ocelot_port_private *priv = netdev_priv(dev); 342 struct ocelot *ocelot = priv->port.ocelot; 343 int port = priv->chip_port; 344 int ret; 345 346 /* 8021q removes VID 0 on module unload for all interfaces 347 * with VLAN filtering feature. We need to keep it to receive 348 * untagged traffic. 349 */ 350 if (vid == 0) 351 return 0; 352 353 ret = ocelot_vlan_del(ocelot, port, vid); 354 if (ret) 355 return ret; 356 357 /* Del the port MAC address to with the right VLAN information */ 358 ocelot_mact_forget(ocelot, dev->dev_addr, vid); 359 360 return 0; 361 } 362 363 static void ocelot_vlan_init(struct ocelot *ocelot) 364 { 365 u16 port, vid; 366 367 /* Clear VLAN table, by default all ports are members of all VLANs */ 368 ocelot_write(ocelot, ANA_TABLES_VLANACCESS_CMD_INIT, 369 ANA_TABLES_VLANACCESS); 370 ocelot_vlant_wait_for_completion(ocelot); 371 372 /* Configure the port VLAN memberships */ 373 for (vid = 1; vid < VLAN_N_VID; vid++) { 374 ocelot->vlan_mask[vid] = 0; 375 ocelot_vlant_set_mask(ocelot, vid, ocelot->vlan_mask[vid]); 376 } 377 378 /* Because VLAN filtering is enabled, we need VID 0 to get untagged 379 * traffic. It is added automatically if 8021q module is loaded, but 380 * we can't rely on it since module may be not loaded. 381 */ 382 ocelot->vlan_mask[0] = GENMASK(ocelot->num_phys_ports - 1, 0); 383 ocelot_vlant_set_mask(ocelot, 0, ocelot->vlan_mask[0]); 384 385 /* Set vlan ingress filter mask to all ports but the CPU port by 386 * default. 387 */ 388 ocelot_write(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 389 ANA_VLANMASK); 390 391 for (port = 0; port < ocelot->num_phys_ports; port++) { 392 ocelot_write_gix(ocelot, 0, REW_PORT_VLAN_CFG, port); 393 ocelot_write_gix(ocelot, 0, REW_TAG_CFG, port); 394 } 395 } 396 397 /* Watermark encode 398 * Bit 8: Unit; 0:1, 1:16 399 * Bit 7-0: Value to be multiplied with unit 400 */ 401 static u16 ocelot_wm_enc(u16 value) 402 { 403 if (value >= BIT(8)) 404 return BIT(8) | (value / 16); 405 406 return value; 407 } 408 409 void ocelot_adjust_link(struct ocelot *ocelot, int port, 410 struct phy_device *phydev) 411 { 412 struct ocelot_port *ocelot_port = ocelot->ports[port]; 413 int speed, mode = 0; 414 415 switch (phydev->speed) { 416 case SPEED_10: 417 speed = OCELOT_SPEED_10; 418 break; 419 case SPEED_100: 420 speed = OCELOT_SPEED_100; 421 break; 422 case SPEED_1000: 423 speed = OCELOT_SPEED_1000; 424 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 425 break; 426 case SPEED_2500: 427 speed = OCELOT_SPEED_2500; 428 mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA; 429 break; 430 default: 431 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n", 432 port, phydev->speed); 433 return; 434 } 435 436 phy_print_status(phydev); 437 438 if (!phydev->link) 439 return; 440 441 /* Only full duplex supported for now */ 442 ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA | 443 mode, DEV_MAC_MODE_CFG); 444 445 /* Disable HDX fast control */ 446 ocelot_port_writel(ocelot_port, DEV_PORT_MISC_HDX_FAST_DIS, 447 DEV_PORT_MISC); 448 449 /* SGMII only for now */ 450 ocelot_port_writel(ocelot_port, PCS1G_MODE_CFG_SGMII_MODE_ENA, 451 PCS1G_MODE_CFG); 452 ocelot_port_writel(ocelot_port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG); 453 454 /* Enable PCS */ 455 ocelot_port_writel(ocelot_port, PCS1G_CFG_PCS_ENA, PCS1G_CFG); 456 457 /* No aneg on SGMII */ 458 ocelot_port_writel(ocelot_port, 0, PCS1G_ANEG_CFG); 459 460 /* No loopback */ 461 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); 462 463 /* Enable MAC module */ 464 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | 465 DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG); 466 467 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of 468 * reset */ 469 ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed), 470 DEV_CLOCK_CFG); 471 472 /* No PFC */ 473 ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed), 474 ANA_PFC_PFC_CFG, port); 475 476 /* Core: Enable port for frame transfer */ 477 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 478 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 479 QSYS_SWITCH_PORT_MODE_PORT_ENA, 480 QSYS_SWITCH_PORT_MODE, port); 481 482 /* Flow control */ 483 ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) | 484 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA | 485 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA | 486 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) | 487 SYS_MAC_FC_CFG_FC_LINK_SPEED(speed), 488 SYS_MAC_FC_CFG, port); 489 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port); 490 } 491 EXPORT_SYMBOL(ocelot_adjust_link); 492 493 static void ocelot_port_adjust_link(struct net_device *dev) 494 { 495 struct ocelot_port_private *priv = netdev_priv(dev); 496 struct ocelot *ocelot = priv->port.ocelot; 497 int port = priv->chip_port; 498 499 ocelot_adjust_link(ocelot, port, dev->phydev); 500 } 501 502 void ocelot_port_enable(struct ocelot *ocelot, int port, 503 struct phy_device *phy) 504 { 505 /* Enable receiving frames on the port, and activate auto-learning of 506 * MAC addresses. 507 */ 508 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO | 509 ANA_PORT_PORT_CFG_RECV_ENA | 510 ANA_PORT_PORT_CFG_PORTID_VAL(port), 511 ANA_PORT_PORT_CFG, port); 512 } 513 EXPORT_SYMBOL(ocelot_port_enable); 514 515 static int ocelot_port_open(struct net_device *dev) 516 { 517 struct ocelot_port_private *priv = netdev_priv(dev); 518 struct ocelot_port *ocelot_port = &priv->port; 519 struct ocelot *ocelot = ocelot_port->ocelot; 520 int port = priv->chip_port; 521 int err; 522 523 if (priv->serdes) { 524 err = phy_set_mode_ext(priv->serdes, PHY_MODE_ETHERNET, 525 ocelot_port->phy_mode); 526 if (err) { 527 netdev_err(dev, "Could not set mode of SerDes\n"); 528 return err; 529 } 530 } 531 532 err = phy_connect_direct(dev, priv->phy, &ocelot_port_adjust_link, 533 ocelot_port->phy_mode); 534 if (err) { 535 netdev_err(dev, "Could not attach to PHY\n"); 536 return err; 537 } 538 539 dev->phydev = priv->phy; 540 541 phy_attached_info(priv->phy); 542 phy_start(priv->phy); 543 544 ocelot_port_enable(ocelot, port, priv->phy); 545 546 return 0; 547 } 548 549 void ocelot_port_disable(struct ocelot *ocelot, int port) 550 { 551 struct ocelot_port *ocelot_port = ocelot->ports[port]; 552 553 ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG); 554 ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA, 555 QSYS_SWITCH_PORT_MODE, port); 556 } 557 EXPORT_SYMBOL(ocelot_port_disable); 558 559 static int ocelot_port_stop(struct net_device *dev) 560 { 561 struct ocelot_port_private *priv = netdev_priv(dev); 562 struct ocelot *ocelot = priv->port.ocelot; 563 int port = priv->chip_port; 564 565 phy_disconnect(priv->phy); 566 567 dev->phydev = NULL; 568 569 ocelot_port_disable(ocelot, port); 570 571 return 0; 572 } 573 574 /* Generate the IFH for frame injection 575 * 576 * The IFH is a 128bit-value 577 * bit 127: bypass the analyzer processing 578 * bit 56-67: destination mask 579 * bit 28-29: pop_cnt: 3 disables all rewriting of the frame 580 * bit 20-27: cpu extraction queue mask 581 * bit 16: tag type 0: C-tag, 1: S-tag 582 * bit 0-11: VID 583 */ 584 static int ocelot_gen_ifh(u32 *ifh, struct frame_info *info) 585 { 586 ifh[0] = IFH_INJ_BYPASS | ((0x1ff & info->rew_op) << 21); 587 ifh[1] = (0xf00 & info->port) >> 8; 588 ifh[2] = (0xff & info->port) << 24; 589 ifh[3] = (info->tag_type << 16) | info->vid; 590 591 return 0; 592 } 593 594 int ocelot_port_add_txtstamp_skb(struct ocelot_port *ocelot_port, 595 struct sk_buff *skb) 596 { 597 struct skb_shared_info *shinfo = skb_shinfo(skb); 598 struct ocelot *ocelot = ocelot_port->ocelot; 599 600 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP && 601 ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) { 602 shinfo->tx_flags |= SKBTX_IN_PROGRESS; 603 /* Store timestamp ID in cb[0] of sk_buff */ 604 skb->cb[0] = ocelot_port->ts_id % 4; 605 skb_queue_tail(&ocelot_port->tx_skbs, skb); 606 return 0; 607 } 608 return -ENODATA; 609 } 610 EXPORT_SYMBOL(ocelot_port_add_txtstamp_skb); 611 612 static int ocelot_port_xmit(struct sk_buff *skb, struct net_device *dev) 613 { 614 struct ocelot_port_private *priv = netdev_priv(dev); 615 struct skb_shared_info *shinfo = skb_shinfo(skb); 616 struct ocelot_port *ocelot_port = &priv->port; 617 struct ocelot *ocelot = ocelot_port->ocelot; 618 u32 val, ifh[OCELOT_TAG_LEN / 4]; 619 struct frame_info info = {}; 620 u8 grp = 0; /* Send everything on CPU group 0 */ 621 unsigned int i, count, last; 622 int port = priv->chip_port; 623 624 val = ocelot_read(ocelot, QS_INJ_STATUS); 625 if (!(val & QS_INJ_STATUS_FIFO_RDY(BIT(grp))) || 626 (val & QS_INJ_STATUS_WMARK_REACHED(BIT(grp)))) 627 return NETDEV_TX_BUSY; 628 629 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 630 QS_INJ_CTRL_SOF, QS_INJ_CTRL, grp); 631 632 info.port = BIT(port); 633 info.tag_type = IFH_TAG_TYPE_C; 634 info.vid = skb_vlan_tag_get(skb); 635 636 /* Check if timestamping is needed */ 637 if (ocelot->ptp && shinfo->tx_flags & SKBTX_HW_TSTAMP) { 638 info.rew_op = ocelot_port->ptp_cmd; 639 if (ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) 640 info.rew_op |= (ocelot_port->ts_id % 4) << 3; 641 } 642 643 ocelot_gen_ifh(ifh, &info); 644 645 for (i = 0; i < OCELOT_TAG_LEN / 4; i++) 646 ocelot_write_rix(ocelot, (__force u32)cpu_to_be32(ifh[i]), 647 QS_INJ_WR, grp); 648 649 count = (skb->len + 3) / 4; 650 last = skb->len % 4; 651 for (i = 0; i < count; i++) { 652 ocelot_write_rix(ocelot, ((u32 *)skb->data)[i], QS_INJ_WR, grp); 653 } 654 655 /* Add padding */ 656 while (i < (OCELOT_BUFFER_CELL_SZ / 4)) { 657 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 658 i++; 659 } 660 661 /* Indicate EOF and valid bytes in last word */ 662 ocelot_write_rix(ocelot, QS_INJ_CTRL_GAP_SIZE(1) | 663 QS_INJ_CTRL_VLD_BYTES(skb->len < OCELOT_BUFFER_CELL_SZ ? 0 : last) | 664 QS_INJ_CTRL_EOF, 665 QS_INJ_CTRL, grp); 666 667 /* Add dummy CRC */ 668 ocelot_write_rix(ocelot, 0, QS_INJ_WR, grp); 669 skb_tx_timestamp(skb); 670 671 dev->stats.tx_packets++; 672 dev->stats.tx_bytes += skb->len; 673 674 if (!ocelot_port_add_txtstamp_skb(ocelot_port, skb)) { 675 ocelot_port->ts_id++; 676 return NETDEV_TX_OK; 677 } 678 679 dev_kfree_skb_any(skb); 680 return NETDEV_TX_OK; 681 } 682 683 static void ocelot_get_hwtimestamp(struct ocelot *ocelot, 684 struct timespec64 *ts) 685 { 686 unsigned long flags; 687 u32 val; 688 689 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 690 691 /* Read current PTP time to get seconds */ 692 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 693 694 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 695 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 696 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 697 ts->tv_sec = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 698 699 /* Read packet HW timestamp from FIFO */ 700 val = ocelot_read(ocelot, SYS_PTP_TXSTAMP); 701 ts->tv_nsec = SYS_PTP_TXSTAMP_PTP_TXSTAMP(val); 702 703 /* Sec has incremented since the ts was registered */ 704 if ((ts->tv_sec & 0x1) != !!(val & SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC)) 705 ts->tv_sec--; 706 707 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 708 } 709 710 void ocelot_get_txtstamp(struct ocelot *ocelot) 711 { 712 int budget = OCELOT_PTP_QUEUE_SZ; 713 714 while (budget--) { 715 struct sk_buff *skb, *skb_tmp, *skb_match = NULL; 716 struct skb_shared_hwtstamps shhwtstamps; 717 struct ocelot_port *port; 718 struct timespec64 ts; 719 unsigned long flags; 720 u32 val, id, txport; 721 722 val = ocelot_read(ocelot, SYS_PTP_STATUS); 723 724 /* Check if a timestamp can be retrieved */ 725 if (!(val & SYS_PTP_STATUS_PTP_MESS_VLD)) 726 break; 727 728 WARN_ON(val & SYS_PTP_STATUS_PTP_OVFL); 729 730 /* Retrieve the ts ID and Tx port */ 731 id = SYS_PTP_STATUS_PTP_MESS_ID_X(val); 732 txport = SYS_PTP_STATUS_PTP_MESS_TXPORT_X(val); 733 734 /* Retrieve its associated skb */ 735 port = ocelot->ports[txport]; 736 737 spin_lock_irqsave(&port->tx_skbs.lock, flags); 738 739 skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { 740 if (skb->cb[0] != id) 741 continue; 742 __skb_unlink(skb, &port->tx_skbs); 743 skb_match = skb; 744 break; 745 } 746 747 spin_unlock_irqrestore(&port->tx_skbs.lock, flags); 748 749 /* Next ts */ 750 ocelot_write(ocelot, SYS_PTP_NXT_PTP_NXT, SYS_PTP_NXT); 751 752 if (unlikely(!skb_match)) 753 continue; 754 755 /* Get the h/w timestamp */ 756 ocelot_get_hwtimestamp(ocelot, &ts); 757 758 /* Set the timestamp into the skb */ 759 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 760 shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); 761 skb_tstamp_tx(skb_match, &shhwtstamps); 762 763 dev_kfree_skb_any(skb_match); 764 } 765 } 766 EXPORT_SYMBOL(ocelot_get_txtstamp); 767 768 static int ocelot_mc_unsync(struct net_device *dev, const unsigned char *addr) 769 { 770 struct ocelot_port_private *priv = netdev_priv(dev); 771 struct ocelot_port *ocelot_port = &priv->port; 772 struct ocelot *ocelot = ocelot_port->ocelot; 773 774 return ocelot_mact_forget(ocelot, addr, ocelot_port->pvid); 775 } 776 777 static int ocelot_mc_sync(struct net_device *dev, const unsigned char *addr) 778 { 779 struct ocelot_port_private *priv = netdev_priv(dev); 780 struct ocelot_port *ocelot_port = &priv->port; 781 struct ocelot *ocelot = ocelot_port->ocelot; 782 783 return ocelot_mact_learn(ocelot, PGID_CPU, addr, ocelot_port->pvid, 784 ENTRYTYPE_LOCKED); 785 } 786 787 static void ocelot_set_rx_mode(struct net_device *dev) 788 { 789 struct ocelot_port_private *priv = netdev_priv(dev); 790 struct ocelot *ocelot = priv->port.ocelot; 791 u32 val; 792 int i; 793 794 /* This doesn't handle promiscuous mode because the bridge core is 795 * setting IFF_PROMISC on all slave interfaces and all frames would be 796 * forwarded to the CPU port. 797 */ 798 val = GENMASK(ocelot->num_phys_ports - 1, 0); 799 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) 800 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 801 802 __dev_mc_sync(dev, ocelot_mc_sync, ocelot_mc_unsync); 803 } 804 805 static int ocelot_port_get_phys_port_name(struct net_device *dev, 806 char *buf, size_t len) 807 { 808 struct ocelot_port_private *priv = netdev_priv(dev); 809 int port = priv->chip_port; 810 int ret; 811 812 ret = snprintf(buf, len, "p%d", port); 813 if (ret >= len) 814 return -EINVAL; 815 816 return 0; 817 } 818 819 static int ocelot_port_set_mac_address(struct net_device *dev, void *p) 820 { 821 struct ocelot_port_private *priv = netdev_priv(dev); 822 struct ocelot_port *ocelot_port = &priv->port; 823 struct ocelot *ocelot = ocelot_port->ocelot; 824 const struct sockaddr *addr = p; 825 826 /* Learn the new net device MAC address in the mac table. */ 827 ocelot_mact_learn(ocelot, PGID_CPU, addr->sa_data, ocelot_port->pvid, 828 ENTRYTYPE_LOCKED); 829 /* Then forget the previous one. */ 830 ocelot_mact_forget(ocelot, dev->dev_addr, ocelot_port->pvid); 831 832 ether_addr_copy(dev->dev_addr, addr->sa_data); 833 return 0; 834 } 835 836 static void ocelot_get_stats64(struct net_device *dev, 837 struct rtnl_link_stats64 *stats) 838 { 839 struct ocelot_port_private *priv = netdev_priv(dev); 840 struct ocelot *ocelot = priv->port.ocelot; 841 int port = priv->chip_port; 842 843 /* Configure the port to read the stats from */ 844 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port), 845 SYS_STAT_CFG); 846 847 /* Get Rx stats */ 848 stats->rx_bytes = ocelot_read(ocelot, SYS_COUNT_RX_OCTETS); 849 stats->rx_packets = ocelot_read(ocelot, SYS_COUNT_RX_SHORTS) + 850 ocelot_read(ocelot, SYS_COUNT_RX_FRAGMENTS) + 851 ocelot_read(ocelot, SYS_COUNT_RX_JABBERS) + 852 ocelot_read(ocelot, SYS_COUNT_RX_LONGS) + 853 ocelot_read(ocelot, SYS_COUNT_RX_64) + 854 ocelot_read(ocelot, SYS_COUNT_RX_65_127) + 855 ocelot_read(ocelot, SYS_COUNT_RX_128_255) + 856 ocelot_read(ocelot, SYS_COUNT_RX_256_1023) + 857 ocelot_read(ocelot, SYS_COUNT_RX_1024_1526) + 858 ocelot_read(ocelot, SYS_COUNT_RX_1527_MAX); 859 stats->multicast = ocelot_read(ocelot, SYS_COUNT_RX_MULTICAST); 860 stats->rx_dropped = dev->stats.rx_dropped; 861 862 /* Get Tx stats */ 863 stats->tx_bytes = ocelot_read(ocelot, SYS_COUNT_TX_OCTETS); 864 stats->tx_packets = ocelot_read(ocelot, SYS_COUNT_TX_64) + 865 ocelot_read(ocelot, SYS_COUNT_TX_65_127) + 866 ocelot_read(ocelot, SYS_COUNT_TX_128_511) + 867 ocelot_read(ocelot, SYS_COUNT_TX_512_1023) + 868 ocelot_read(ocelot, SYS_COUNT_TX_1024_1526) + 869 ocelot_read(ocelot, SYS_COUNT_TX_1527_MAX); 870 stats->tx_dropped = ocelot_read(ocelot, SYS_COUNT_TX_DROPS) + 871 ocelot_read(ocelot, SYS_COUNT_TX_AGING); 872 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION); 873 } 874 875 int ocelot_fdb_add(struct ocelot *ocelot, int port, 876 const unsigned char *addr, u16 vid, bool vlan_aware) 877 { 878 struct ocelot_port *ocelot_port = ocelot->ports[port]; 879 880 if (!vid) { 881 if (!vlan_aware) 882 /* If the bridge is not VLAN aware and no VID was 883 * provided, set it to pvid to ensure the MAC entry 884 * matches incoming untagged packets 885 */ 886 vid = ocelot_port->pvid; 887 else 888 /* If the bridge is VLAN aware a VID must be provided as 889 * otherwise the learnt entry wouldn't match any frame. 890 */ 891 return -EINVAL; 892 } 893 894 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED); 895 } 896 EXPORT_SYMBOL(ocelot_fdb_add); 897 898 static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], 899 struct net_device *dev, 900 const unsigned char *addr, 901 u16 vid, u16 flags, 902 struct netlink_ext_ack *extack) 903 { 904 struct ocelot_port_private *priv = netdev_priv(dev); 905 struct ocelot *ocelot = priv->port.ocelot; 906 int port = priv->chip_port; 907 908 return ocelot_fdb_add(ocelot, port, addr, vid, priv->vlan_aware); 909 } 910 911 int ocelot_fdb_del(struct ocelot *ocelot, int port, 912 const unsigned char *addr, u16 vid) 913 { 914 return ocelot_mact_forget(ocelot, addr, vid); 915 } 916 EXPORT_SYMBOL(ocelot_fdb_del); 917 918 static int ocelot_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[], 919 struct net_device *dev, 920 const unsigned char *addr, u16 vid) 921 { 922 struct ocelot_port_private *priv = netdev_priv(dev); 923 struct ocelot *ocelot = priv->port.ocelot; 924 int port = priv->chip_port; 925 926 return ocelot_fdb_del(ocelot, port, addr, vid); 927 } 928 929 struct ocelot_dump_ctx { 930 struct net_device *dev; 931 struct sk_buff *skb; 932 struct netlink_callback *cb; 933 int idx; 934 }; 935 936 static int ocelot_port_fdb_do_dump(const unsigned char *addr, u16 vid, 937 bool is_static, void *data) 938 { 939 struct ocelot_dump_ctx *dump = data; 940 u32 portid = NETLINK_CB(dump->cb->skb).portid; 941 u32 seq = dump->cb->nlh->nlmsg_seq; 942 struct nlmsghdr *nlh; 943 struct ndmsg *ndm; 944 945 if (dump->idx < dump->cb->args[2]) 946 goto skip; 947 948 nlh = nlmsg_put(dump->skb, portid, seq, RTM_NEWNEIGH, 949 sizeof(*ndm), NLM_F_MULTI); 950 if (!nlh) 951 return -EMSGSIZE; 952 953 ndm = nlmsg_data(nlh); 954 ndm->ndm_family = AF_BRIDGE; 955 ndm->ndm_pad1 = 0; 956 ndm->ndm_pad2 = 0; 957 ndm->ndm_flags = NTF_SELF; 958 ndm->ndm_type = 0; 959 ndm->ndm_ifindex = dump->dev->ifindex; 960 ndm->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE; 961 962 if (nla_put(dump->skb, NDA_LLADDR, ETH_ALEN, addr)) 963 goto nla_put_failure; 964 965 if (vid && nla_put_u16(dump->skb, NDA_VLAN, vid)) 966 goto nla_put_failure; 967 968 nlmsg_end(dump->skb, nlh); 969 970 skip: 971 dump->idx++; 972 return 0; 973 974 nla_put_failure: 975 nlmsg_cancel(dump->skb, nlh); 976 return -EMSGSIZE; 977 } 978 979 static int ocelot_mact_read(struct ocelot *ocelot, int port, int row, int col, 980 struct ocelot_mact_entry *entry) 981 { 982 u32 val, dst, macl, mach; 983 char mac[ETH_ALEN]; 984 985 /* Set row and column to read from */ 986 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_M_INDEX, row); 987 ocelot_field_write(ocelot, ANA_TABLES_MACTINDX_BUCKET, col); 988 989 /* Issue a read command */ 990 ocelot_write(ocelot, 991 ANA_TABLES_MACACCESS_MAC_TABLE_CMD(MACACCESS_CMD_READ), 992 ANA_TABLES_MACACCESS); 993 994 if (ocelot_mact_wait_for_completion(ocelot)) 995 return -ETIMEDOUT; 996 997 /* Read the entry flags */ 998 val = ocelot_read(ocelot, ANA_TABLES_MACACCESS); 999 if (!(val & ANA_TABLES_MACACCESS_VALID)) 1000 return -EINVAL; 1001 1002 /* If the entry read has another port configured as its destination, 1003 * do not report it. 1004 */ 1005 dst = (val & ANA_TABLES_MACACCESS_DEST_IDX_M) >> 3; 1006 if (dst != port) 1007 return -EINVAL; 1008 1009 /* Get the entry's MAC address and VLAN id */ 1010 macl = ocelot_read(ocelot, ANA_TABLES_MACLDATA); 1011 mach = ocelot_read(ocelot, ANA_TABLES_MACHDATA); 1012 1013 mac[0] = (mach >> 8) & 0xff; 1014 mac[1] = (mach >> 0) & 0xff; 1015 mac[2] = (macl >> 24) & 0xff; 1016 mac[3] = (macl >> 16) & 0xff; 1017 mac[4] = (macl >> 8) & 0xff; 1018 mac[5] = (macl >> 0) & 0xff; 1019 1020 entry->vid = (mach >> 16) & 0xfff; 1021 ether_addr_copy(entry->mac, mac); 1022 1023 return 0; 1024 } 1025 1026 int ocelot_fdb_dump(struct ocelot *ocelot, int port, 1027 dsa_fdb_dump_cb_t *cb, void *data) 1028 { 1029 int i, j; 1030 1031 /* Loop through all the mac tables entries. There are 1024 rows of 4 1032 * entries. 1033 */ 1034 for (i = 0; i < 1024; i++) { 1035 for (j = 0; j < 4; j++) { 1036 struct ocelot_mact_entry entry; 1037 bool is_static; 1038 int ret; 1039 1040 ret = ocelot_mact_read(ocelot, port, i, j, &entry); 1041 /* If the entry is invalid (wrong port, invalid...), 1042 * skip it. 1043 */ 1044 if (ret == -EINVAL) 1045 continue; 1046 else if (ret) 1047 return ret; 1048 1049 is_static = (entry.type == ENTRYTYPE_LOCKED); 1050 1051 ret = cb(entry.mac, entry.vid, is_static, data); 1052 if (ret) 1053 return ret; 1054 } 1055 } 1056 1057 return 0; 1058 } 1059 EXPORT_SYMBOL(ocelot_fdb_dump); 1060 1061 static int ocelot_port_fdb_dump(struct sk_buff *skb, 1062 struct netlink_callback *cb, 1063 struct net_device *dev, 1064 struct net_device *filter_dev, int *idx) 1065 { 1066 struct ocelot_port_private *priv = netdev_priv(dev); 1067 struct ocelot *ocelot = priv->port.ocelot; 1068 struct ocelot_dump_ctx dump = { 1069 .dev = dev, 1070 .skb = skb, 1071 .cb = cb, 1072 .idx = *idx, 1073 }; 1074 int port = priv->chip_port; 1075 int ret; 1076 1077 ret = ocelot_fdb_dump(ocelot, port, ocelot_port_fdb_do_dump, &dump); 1078 1079 *idx = dump.idx; 1080 1081 return ret; 1082 } 1083 1084 static int ocelot_vlan_rx_add_vid(struct net_device *dev, __be16 proto, 1085 u16 vid) 1086 { 1087 return ocelot_vlan_vid_add(dev, vid, false, false); 1088 } 1089 1090 static int ocelot_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, 1091 u16 vid) 1092 { 1093 return ocelot_vlan_vid_del(dev, vid); 1094 } 1095 1096 static int ocelot_set_features(struct net_device *dev, 1097 netdev_features_t features) 1098 { 1099 netdev_features_t changed = dev->features ^ features; 1100 struct ocelot_port_private *priv = netdev_priv(dev); 1101 struct ocelot *ocelot = priv->port.ocelot; 1102 int port = priv->chip_port; 1103 1104 if ((dev->features & NETIF_F_HW_TC) > (features & NETIF_F_HW_TC) && 1105 priv->tc.offload_cnt) { 1106 netdev_err(dev, 1107 "Cannot disable HW TC offload while offloads active\n"); 1108 return -EBUSY; 1109 } 1110 1111 if (changed & NETIF_F_HW_VLAN_CTAG_FILTER) 1112 ocelot_vlan_mode(ocelot, port, features); 1113 1114 return 0; 1115 } 1116 1117 static int ocelot_get_port_parent_id(struct net_device *dev, 1118 struct netdev_phys_item_id *ppid) 1119 { 1120 struct ocelot_port_private *priv = netdev_priv(dev); 1121 struct ocelot *ocelot = priv->port.ocelot; 1122 1123 ppid->id_len = sizeof(ocelot->base_mac); 1124 memcpy(&ppid->id, &ocelot->base_mac, ppid->id_len); 1125 1126 return 0; 1127 } 1128 1129 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr) 1130 { 1131 return copy_to_user(ifr->ifr_data, &ocelot->hwtstamp_config, 1132 sizeof(ocelot->hwtstamp_config)) ? -EFAULT : 0; 1133 } 1134 EXPORT_SYMBOL(ocelot_hwstamp_get); 1135 1136 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr) 1137 { 1138 struct ocelot_port *ocelot_port = ocelot->ports[port]; 1139 struct hwtstamp_config cfg; 1140 1141 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1142 return -EFAULT; 1143 1144 /* reserved for future extensions */ 1145 if (cfg.flags) 1146 return -EINVAL; 1147 1148 /* Tx type sanity check */ 1149 switch (cfg.tx_type) { 1150 case HWTSTAMP_TX_ON: 1151 ocelot_port->ptp_cmd = IFH_REW_OP_TWO_STEP_PTP; 1152 break; 1153 case HWTSTAMP_TX_ONESTEP_SYNC: 1154 /* IFH_REW_OP_ONE_STEP_PTP updates the correctional field, we 1155 * need to update the origin time. 1156 */ 1157 ocelot_port->ptp_cmd = IFH_REW_OP_ORIGIN_PTP; 1158 break; 1159 case HWTSTAMP_TX_OFF: 1160 ocelot_port->ptp_cmd = 0; 1161 break; 1162 default: 1163 return -ERANGE; 1164 } 1165 1166 mutex_lock(&ocelot->ptp_lock); 1167 1168 switch (cfg.rx_filter) { 1169 case HWTSTAMP_FILTER_NONE: 1170 break; 1171 case HWTSTAMP_FILTER_ALL: 1172 case HWTSTAMP_FILTER_SOME: 1173 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1174 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1175 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1176 case HWTSTAMP_FILTER_NTP_ALL: 1177 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1178 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1179 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1180 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1181 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1182 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1183 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1184 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1185 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1186 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1187 break; 1188 default: 1189 mutex_unlock(&ocelot->ptp_lock); 1190 return -ERANGE; 1191 } 1192 1193 /* Commit back the result & save it */ 1194 memcpy(&ocelot->hwtstamp_config, &cfg, sizeof(cfg)); 1195 mutex_unlock(&ocelot->ptp_lock); 1196 1197 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1198 } 1199 EXPORT_SYMBOL(ocelot_hwstamp_set); 1200 1201 static int ocelot_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 1202 { 1203 struct ocelot_port_private *priv = netdev_priv(dev); 1204 struct ocelot *ocelot = priv->port.ocelot; 1205 int port = priv->chip_port; 1206 1207 /* The function is only used for PTP operations for now */ 1208 if (!ocelot->ptp) 1209 return -EOPNOTSUPP; 1210 1211 switch (cmd) { 1212 case SIOCSHWTSTAMP: 1213 return ocelot_hwstamp_set(ocelot, port, ifr); 1214 case SIOCGHWTSTAMP: 1215 return ocelot_hwstamp_get(ocelot, port, ifr); 1216 default: 1217 return -EOPNOTSUPP; 1218 } 1219 } 1220 1221 static const struct net_device_ops ocelot_port_netdev_ops = { 1222 .ndo_open = ocelot_port_open, 1223 .ndo_stop = ocelot_port_stop, 1224 .ndo_start_xmit = ocelot_port_xmit, 1225 .ndo_set_rx_mode = ocelot_set_rx_mode, 1226 .ndo_get_phys_port_name = ocelot_port_get_phys_port_name, 1227 .ndo_set_mac_address = ocelot_port_set_mac_address, 1228 .ndo_get_stats64 = ocelot_get_stats64, 1229 .ndo_fdb_add = ocelot_port_fdb_add, 1230 .ndo_fdb_del = ocelot_port_fdb_del, 1231 .ndo_fdb_dump = ocelot_port_fdb_dump, 1232 .ndo_vlan_rx_add_vid = ocelot_vlan_rx_add_vid, 1233 .ndo_vlan_rx_kill_vid = ocelot_vlan_rx_kill_vid, 1234 .ndo_set_features = ocelot_set_features, 1235 .ndo_get_port_parent_id = ocelot_get_port_parent_id, 1236 .ndo_setup_tc = ocelot_setup_tc, 1237 .ndo_do_ioctl = ocelot_ioctl, 1238 }; 1239 1240 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data) 1241 { 1242 int i; 1243 1244 if (sset != ETH_SS_STATS) 1245 return; 1246 1247 for (i = 0; i < ocelot->num_stats; i++) 1248 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name, 1249 ETH_GSTRING_LEN); 1250 } 1251 EXPORT_SYMBOL(ocelot_get_strings); 1252 1253 static void ocelot_port_get_strings(struct net_device *netdev, u32 sset, 1254 u8 *data) 1255 { 1256 struct ocelot_port_private *priv = netdev_priv(netdev); 1257 struct ocelot *ocelot = priv->port.ocelot; 1258 int port = priv->chip_port; 1259 1260 ocelot_get_strings(ocelot, port, sset, data); 1261 } 1262 1263 static void ocelot_update_stats(struct ocelot *ocelot) 1264 { 1265 int i, j; 1266 1267 mutex_lock(&ocelot->stats_lock); 1268 1269 for (i = 0; i < ocelot->num_phys_ports; i++) { 1270 /* Configure the port to read the stats from */ 1271 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(i), SYS_STAT_CFG); 1272 1273 for (j = 0; j < ocelot->num_stats; j++) { 1274 u32 val; 1275 unsigned int idx = i * ocelot->num_stats + j; 1276 1277 val = ocelot_read_rix(ocelot, SYS_COUNT_RX_OCTETS, 1278 ocelot->stats_layout[j].offset); 1279 1280 if (val < (ocelot->stats[idx] & U32_MAX)) 1281 ocelot->stats[idx] += (u64)1 << 32; 1282 1283 ocelot->stats[idx] = (ocelot->stats[idx] & 1284 ~(u64)U32_MAX) + val; 1285 } 1286 } 1287 1288 mutex_unlock(&ocelot->stats_lock); 1289 } 1290 1291 static void ocelot_check_stats_work(struct work_struct *work) 1292 { 1293 struct delayed_work *del_work = to_delayed_work(work); 1294 struct ocelot *ocelot = container_of(del_work, struct ocelot, 1295 stats_work); 1296 1297 ocelot_update_stats(ocelot); 1298 1299 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 1300 OCELOT_STATS_CHECK_DELAY); 1301 } 1302 1303 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data) 1304 { 1305 int i; 1306 1307 /* check and update now */ 1308 ocelot_update_stats(ocelot); 1309 1310 /* Copy all counters */ 1311 for (i = 0; i < ocelot->num_stats; i++) 1312 *data++ = ocelot->stats[port * ocelot->num_stats + i]; 1313 } 1314 EXPORT_SYMBOL(ocelot_get_ethtool_stats); 1315 1316 static void ocelot_port_get_ethtool_stats(struct net_device *dev, 1317 struct ethtool_stats *stats, 1318 u64 *data) 1319 { 1320 struct ocelot_port_private *priv = netdev_priv(dev); 1321 struct ocelot *ocelot = priv->port.ocelot; 1322 int port = priv->chip_port; 1323 1324 ocelot_get_ethtool_stats(ocelot, port, data); 1325 } 1326 1327 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset) 1328 { 1329 if (sset != ETH_SS_STATS) 1330 return -EOPNOTSUPP; 1331 1332 return ocelot->num_stats; 1333 } 1334 EXPORT_SYMBOL(ocelot_get_sset_count); 1335 1336 static int ocelot_port_get_sset_count(struct net_device *dev, int sset) 1337 { 1338 struct ocelot_port_private *priv = netdev_priv(dev); 1339 struct ocelot *ocelot = priv->port.ocelot; 1340 int port = priv->chip_port; 1341 1342 return ocelot_get_sset_count(ocelot, port, sset); 1343 } 1344 1345 int ocelot_get_ts_info(struct ocelot *ocelot, int port, 1346 struct ethtool_ts_info *info) 1347 { 1348 info->phc_index = ocelot->ptp_clock ? 1349 ptp_clock_index(ocelot->ptp_clock) : -1; 1350 info->so_timestamping |= SOF_TIMESTAMPING_TX_SOFTWARE | 1351 SOF_TIMESTAMPING_RX_SOFTWARE | 1352 SOF_TIMESTAMPING_SOFTWARE | 1353 SOF_TIMESTAMPING_TX_HARDWARE | 1354 SOF_TIMESTAMPING_RX_HARDWARE | 1355 SOF_TIMESTAMPING_RAW_HARDWARE; 1356 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON) | 1357 BIT(HWTSTAMP_TX_ONESTEP_SYNC); 1358 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | BIT(HWTSTAMP_FILTER_ALL); 1359 1360 return 0; 1361 } 1362 EXPORT_SYMBOL(ocelot_get_ts_info); 1363 1364 static int ocelot_port_get_ts_info(struct net_device *dev, 1365 struct ethtool_ts_info *info) 1366 { 1367 struct ocelot_port_private *priv = netdev_priv(dev); 1368 struct ocelot *ocelot = priv->port.ocelot; 1369 int port = priv->chip_port; 1370 1371 if (!ocelot->ptp) 1372 return ethtool_op_get_ts_info(dev, info); 1373 1374 return ocelot_get_ts_info(ocelot, port, info); 1375 } 1376 1377 static const struct ethtool_ops ocelot_ethtool_ops = { 1378 .get_strings = ocelot_port_get_strings, 1379 .get_ethtool_stats = ocelot_port_get_ethtool_stats, 1380 .get_sset_count = ocelot_port_get_sset_count, 1381 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1382 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1383 .get_ts_info = ocelot_port_get_ts_info, 1384 }; 1385 1386 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state) 1387 { 1388 u32 port_cfg; 1389 int p, i; 1390 1391 if (!(BIT(port) & ocelot->bridge_mask)) 1392 return; 1393 1394 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1395 1396 switch (state) { 1397 case BR_STATE_FORWARDING: 1398 ocelot->bridge_fwd_mask |= BIT(port); 1399 /* Fallthrough */ 1400 case BR_STATE_LEARNING: 1401 port_cfg |= ANA_PORT_PORT_CFG_LEARN_ENA; 1402 break; 1403 1404 default: 1405 port_cfg &= ~ANA_PORT_PORT_CFG_LEARN_ENA; 1406 ocelot->bridge_fwd_mask &= ~BIT(port); 1407 break; 1408 } 1409 1410 ocelot_write_gix(ocelot, port_cfg, ANA_PORT_PORT_CFG, port); 1411 1412 /* Apply FWD mask. The loop is needed to add/remove the current port as 1413 * a source for the other ports. 1414 */ 1415 for (p = 0; p < ocelot->num_phys_ports; p++) { 1416 if (ocelot->bridge_fwd_mask & BIT(p)) { 1417 unsigned long mask = ocelot->bridge_fwd_mask & ~BIT(p); 1418 1419 for (i = 0; i < ocelot->num_phys_ports; i++) { 1420 unsigned long bond_mask = ocelot->lags[i]; 1421 1422 if (!bond_mask) 1423 continue; 1424 1425 if (bond_mask & BIT(p)) { 1426 mask &= ~bond_mask; 1427 break; 1428 } 1429 } 1430 1431 ocelot_write_rix(ocelot, mask, 1432 ANA_PGID_PGID, PGID_SRC + p); 1433 } else { 1434 ocelot_write_rix(ocelot, 0, 1435 ANA_PGID_PGID, PGID_SRC + p); 1436 } 1437 } 1438 } 1439 EXPORT_SYMBOL(ocelot_bridge_stp_state_set); 1440 1441 static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port, 1442 struct switchdev_trans *trans, 1443 u8 state) 1444 { 1445 if (switchdev_trans_ph_prepare(trans)) 1446 return; 1447 1448 ocelot_bridge_stp_state_set(ocelot, port, state); 1449 } 1450 1451 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs) 1452 { 1453 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(msecs / 2), 1454 ANA_AUTOAGE); 1455 } 1456 EXPORT_SYMBOL(ocelot_set_ageing_time); 1457 1458 static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port, 1459 unsigned long ageing_clock_t) 1460 { 1461 unsigned long ageing_jiffies = clock_t_to_jiffies(ageing_clock_t); 1462 u32 ageing_time = jiffies_to_msecs(ageing_jiffies) / 1000; 1463 1464 ocelot_set_ageing_time(ocelot, ageing_time); 1465 } 1466 1467 static void ocelot_port_attr_mc_set(struct ocelot *ocelot, int port, bool mc) 1468 { 1469 u32 cpu_fwd_mcast = ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA | 1470 ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA | 1471 ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA; 1472 u32 val = 0; 1473 1474 if (mc) 1475 val = cpu_fwd_mcast; 1476 1477 ocelot_rmw_gix(ocelot, val, cpu_fwd_mcast, 1478 ANA_PORT_CPU_FWD_CFG, port); 1479 } 1480 1481 static int ocelot_port_attr_set(struct net_device *dev, 1482 const struct switchdev_attr *attr, 1483 struct switchdev_trans *trans) 1484 { 1485 struct ocelot_port_private *priv = netdev_priv(dev); 1486 struct ocelot *ocelot = priv->port.ocelot; 1487 int port = priv->chip_port; 1488 int err = 0; 1489 1490 switch (attr->id) { 1491 case SWITCHDEV_ATTR_ID_PORT_STP_STATE: 1492 ocelot_port_attr_stp_state_set(ocelot, port, trans, 1493 attr->u.stp_state); 1494 break; 1495 case SWITCHDEV_ATTR_ID_BRIDGE_AGEING_TIME: 1496 ocelot_port_attr_ageing_set(ocelot, port, attr->u.ageing_time); 1497 break; 1498 case SWITCHDEV_ATTR_ID_BRIDGE_VLAN_FILTERING: 1499 priv->vlan_aware = attr->u.vlan_filtering; 1500 ocelot_port_vlan_filtering(ocelot, port, priv->vlan_aware); 1501 break; 1502 case SWITCHDEV_ATTR_ID_BRIDGE_MC_DISABLED: 1503 ocelot_port_attr_mc_set(ocelot, port, !attr->u.mc_disabled); 1504 break; 1505 default: 1506 err = -EOPNOTSUPP; 1507 break; 1508 } 1509 1510 return err; 1511 } 1512 1513 static int ocelot_port_obj_add_vlan(struct net_device *dev, 1514 const struct switchdev_obj_port_vlan *vlan, 1515 struct switchdev_trans *trans) 1516 { 1517 int ret; 1518 u16 vid; 1519 1520 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1521 ret = ocelot_vlan_vid_add(dev, vid, 1522 vlan->flags & BRIDGE_VLAN_INFO_PVID, 1523 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1524 if (ret) 1525 return ret; 1526 } 1527 1528 return 0; 1529 } 1530 1531 static int ocelot_port_vlan_del_vlan(struct net_device *dev, 1532 const struct switchdev_obj_port_vlan *vlan) 1533 { 1534 int ret; 1535 u16 vid; 1536 1537 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) { 1538 ret = ocelot_vlan_vid_del(dev, vid); 1539 1540 if (ret) 1541 return ret; 1542 } 1543 1544 return 0; 1545 } 1546 1547 static struct ocelot_multicast *ocelot_multicast_get(struct ocelot *ocelot, 1548 const unsigned char *addr, 1549 u16 vid) 1550 { 1551 struct ocelot_multicast *mc; 1552 1553 list_for_each_entry(mc, &ocelot->multicast, list) { 1554 if (ether_addr_equal(mc->addr, addr) && mc->vid == vid) 1555 return mc; 1556 } 1557 1558 return NULL; 1559 } 1560 1561 static int ocelot_port_obj_add_mdb(struct net_device *dev, 1562 const struct switchdev_obj_port_mdb *mdb, 1563 struct switchdev_trans *trans) 1564 { 1565 struct ocelot_port_private *priv = netdev_priv(dev); 1566 struct ocelot_port *ocelot_port = &priv->port; 1567 struct ocelot *ocelot = ocelot_port->ocelot; 1568 unsigned char addr[ETH_ALEN]; 1569 struct ocelot_multicast *mc; 1570 int port = priv->chip_port; 1571 u16 vid = mdb->vid; 1572 bool new = false; 1573 1574 if (!vid) 1575 vid = ocelot_port->pvid; 1576 1577 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1578 if (!mc) { 1579 mc = devm_kzalloc(ocelot->dev, sizeof(*mc), GFP_KERNEL); 1580 if (!mc) 1581 return -ENOMEM; 1582 1583 memcpy(mc->addr, mdb->addr, ETH_ALEN); 1584 mc->vid = vid; 1585 1586 list_add_tail(&mc->list, &ocelot->multicast); 1587 new = true; 1588 } 1589 1590 memcpy(addr, mc->addr, ETH_ALEN); 1591 addr[0] = 0; 1592 1593 if (!new) { 1594 addr[2] = mc->ports << 0; 1595 addr[1] = mc->ports << 8; 1596 ocelot_mact_forget(ocelot, addr, vid); 1597 } 1598 1599 mc->ports |= BIT(port); 1600 addr[2] = mc->ports << 0; 1601 addr[1] = mc->ports << 8; 1602 1603 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1604 } 1605 1606 static int ocelot_port_obj_del_mdb(struct net_device *dev, 1607 const struct switchdev_obj_port_mdb *mdb) 1608 { 1609 struct ocelot_port_private *priv = netdev_priv(dev); 1610 struct ocelot_port *ocelot_port = &priv->port; 1611 struct ocelot *ocelot = ocelot_port->ocelot; 1612 unsigned char addr[ETH_ALEN]; 1613 struct ocelot_multicast *mc; 1614 int port = priv->chip_port; 1615 u16 vid = mdb->vid; 1616 1617 if (!vid) 1618 vid = ocelot_port->pvid; 1619 1620 mc = ocelot_multicast_get(ocelot, mdb->addr, vid); 1621 if (!mc) 1622 return -ENOENT; 1623 1624 memcpy(addr, mc->addr, ETH_ALEN); 1625 addr[2] = mc->ports << 0; 1626 addr[1] = mc->ports << 8; 1627 addr[0] = 0; 1628 ocelot_mact_forget(ocelot, addr, vid); 1629 1630 mc->ports &= ~BIT(port); 1631 if (!mc->ports) { 1632 list_del(&mc->list); 1633 devm_kfree(ocelot->dev, mc); 1634 return 0; 1635 } 1636 1637 addr[2] = mc->ports << 0; 1638 addr[1] = mc->ports << 8; 1639 1640 return ocelot_mact_learn(ocelot, 0, addr, vid, ENTRYTYPE_MACv4); 1641 } 1642 1643 static int ocelot_port_obj_add(struct net_device *dev, 1644 const struct switchdev_obj *obj, 1645 struct switchdev_trans *trans, 1646 struct netlink_ext_ack *extack) 1647 { 1648 int ret = 0; 1649 1650 switch (obj->id) { 1651 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1652 ret = ocelot_port_obj_add_vlan(dev, 1653 SWITCHDEV_OBJ_PORT_VLAN(obj), 1654 trans); 1655 break; 1656 case SWITCHDEV_OBJ_ID_PORT_MDB: 1657 ret = ocelot_port_obj_add_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj), 1658 trans); 1659 break; 1660 default: 1661 return -EOPNOTSUPP; 1662 } 1663 1664 return ret; 1665 } 1666 1667 static int ocelot_port_obj_del(struct net_device *dev, 1668 const struct switchdev_obj *obj) 1669 { 1670 int ret = 0; 1671 1672 switch (obj->id) { 1673 case SWITCHDEV_OBJ_ID_PORT_VLAN: 1674 ret = ocelot_port_vlan_del_vlan(dev, 1675 SWITCHDEV_OBJ_PORT_VLAN(obj)); 1676 break; 1677 case SWITCHDEV_OBJ_ID_PORT_MDB: 1678 ret = ocelot_port_obj_del_mdb(dev, SWITCHDEV_OBJ_PORT_MDB(obj)); 1679 break; 1680 default: 1681 return -EOPNOTSUPP; 1682 } 1683 1684 return ret; 1685 } 1686 1687 int ocelot_port_bridge_join(struct ocelot *ocelot, int port, 1688 struct net_device *bridge) 1689 { 1690 if (!ocelot->bridge_mask) { 1691 ocelot->hw_bridge_dev = bridge; 1692 } else { 1693 if (ocelot->hw_bridge_dev != bridge) 1694 /* This is adding the port to a second bridge, this is 1695 * unsupported */ 1696 return -ENODEV; 1697 } 1698 1699 ocelot->bridge_mask |= BIT(port); 1700 1701 return 0; 1702 } 1703 EXPORT_SYMBOL(ocelot_port_bridge_join); 1704 1705 int ocelot_port_bridge_leave(struct ocelot *ocelot, int port, 1706 struct net_device *bridge) 1707 { 1708 ocelot->bridge_mask &= ~BIT(port); 1709 1710 if (!ocelot->bridge_mask) 1711 ocelot->hw_bridge_dev = NULL; 1712 1713 ocelot_port_vlan_filtering(ocelot, port, 0); 1714 ocelot_port_set_pvid(ocelot, port, 0); 1715 return ocelot_port_set_native_vlan(ocelot, port, 0); 1716 } 1717 EXPORT_SYMBOL(ocelot_port_bridge_leave); 1718 1719 static void ocelot_set_aggr_pgids(struct ocelot *ocelot) 1720 { 1721 int i, port, lag; 1722 1723 /* Reset destination and aggregation PGIDS */ 1724 for (port = 0; port < ocelot->num_phys_ports; port++) 1725 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 1726 1727 for (i = PGID_AGGR; i < PGID_SRC; i++) 1728 ocelot_write_rix(ocelot, GENMASK(ocelot->num_phys_ports - 1, 0), 1729 ANA_PGID_PGID, i); 1730 1731 /* Now, set PGIDs for each LAG */ 1732 for (lag = 0; lag < ocelot->num_phys_ports; lag++) { 1733 unsigned long bond_mask; 1734 int aggr_count = 0; 1735 u8 aggr_idx[16]; 1736 1737 bond_mask = ocelot->lags[lag]; 1738 if (!bond_mask) 1739 continue; 1740 1741 for_each_set_bit(port, &bond_mask, ocelot->num_phys_ports) { 1742 // Destination mask 1743 ocelot_write_rix(ocelot, bond_mask, 1744 ANA_PGID_PGID, port); 1745 aggr_idx[aggr_count] = port; 1746 aggr_count++; 1747 } 1748 1749 for (i = PGID_AGGR; i < PGID_SRC; i++) { 1750 u32 ac; 1751 1752 ac = ocelot_read_rix(ocelot, ANA_PGID_PGID, i); 1753 ac &= ~bond_mask; 1754 ac |= BIT(aggr_idx[i % aggr_count]); 1755 ocelot_write_rix(ocelot, ac, ANA_PGID_PGID, i); 1756 } 1757 } 1758 } 1759 1760 static void ocelot_setup_lag(struct ocelot *ocelot, int lag) 1761 { 1762 unsigned long bond_mask = ocelot->lags[lag]; 1763 unsigned int p; 1764 1765 for_each_set_bit(p, &bond_mask, ocelot->num_phys_ports) { 1766 u32 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, p); 1767 1768 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1769 1770 /* Use lag port as logical port for port i */ 1771 ocelot_write_gix(ocelot, port_cfg | 1772 ANA_PORT_PORT_CFG_PORTID_VAL(lag), 1773 ANA_PORT_PORT_CFG, p); 1774 } 1775 } 1776 1777 static int ocelot_port_lag_join(struct ocelot *ocelot, int port, 1778 struct net_device *bond) 1779 { 1780 struct net_device *ndev; 1781 u32 bond_mask = 0; 1782 int lag, lp; 1783 1784 rcu_read_lock(); 1785 for_each_netdev_in_bond_rcu(bond, ndev) { 1786 struct ocelot_port_private *priv = netdev_priv(ndev); 1787 1788 bond_mask |= BIT(priv->chip_port); 1789 } 1790 rcu_read_unlock(); 1791 1792 lp = __ffs(bond_mask); 1793 1794 /* If the new port is the lowest one, use it as the logical port from 1795 * now on 1796 */ 1797 if (port == lp) { 1798 lag = port; 1799 ocelot->lags[port] = bond_mask; 1800 bond_mask &= ~BIT(port); 1801 if (bond_mask) { 1802 lp = __ffs(bond_mask); 1803 ocelot->lags[lp] = 0; 1804 } 1805 } else { 1806 lag = lp; 1807 ocelot->lags[lp] |= BIT(port); 1808 } 1809 1810 ocelot_setup_lag(ocelot, lag); 1811 ocelot_set_aggr_pgids(ocelot); 1812 1813 return 0; 1814 } 1815 1816 static void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 1817 struct net_device *bond) 1818 { 1819 u32 port_cfg; 1820 int i; 1821 1822 /* Remove port from any lag */ 1823 for (i = 0; i < ocelot->num_phys_ports; i++) 1824 ocelot->lags[i] &= ~BIT(port); 1825 1826 /* if it was the logical port of the lag, move the lag config to the 1827 * next port 1828 */ 1829 if (ocelot->lags[port]) { 1830 int n = __ffs(ocelot->lags[port]); 1831 1832 ocelot->lags[n] = ocelot->lags[port]; 1833 ocelot->lags[port] = 0; 1834 1835 ocelot_setup_lag(ocelot, n); 1836 } 1837 1838 port_cfg = ocelot_read_gix(ocelot, ANA_PORT_PORT_CFG, port); 1839 port_cfg &= ~ANA_PORT_PORT_CFG_PORTID_VAL_M; 1840 ocelot_write_gix(ocelot, port_cfg | ANA_PORT_PORT_CFG_PORTID_VAL(port), 1841 ANA_PORT_PORT_CFG, port); 1842 1843 ocelot_set_aggr_pgids(ocelot); 1844 } 1845 1846 /* Checks if the net_device instance given to us originate from our driver. */ 1847 static bool ocelot_netdevice_dev_check(const struct net_device *dev) 1848 { 1849 return dev->netdev_ops == &ocelot_port_netdev_ops; 1850 } 1851 1852 static int ocelot_netdevice_port_event(struct net_device *dev, 1853 unsigned long event, 1854 struct netdev_notifier_changeupper_info *info) 1855 { 1856 struct ocelot_port_private *priv = netdev_priv(dev); 1857 struct ocelot_port *ocelot_port = &priv->port; 1858 struct ocelot *ocelot = ocelot_port->ocelot; 1859 int port = priv->chip_port; 1860 int err = 0; 1861 1862 switch (event) { 1863 case NETDEV_CHANGEUPPER: 1864 if (netif_is_bridge_master(info->upper_dev)) { 1865 if (info->linking) { 1866 err = ocelot_port_bridge_join(ocelot, port, 1867 info->upper_dev); 1868 } else { 1869 err = ocelot_port_bridge_leave(ocelot, port, 1870 info->upper_dev); 1871 priv->vlan_aware = false; 1872 } 1873 } 1874 if (netif_is_lag_master(info->upper_dev)) { 1875 if (info->linking) 1876 err = ocelot_port_lag_join(ocelot, port, 1877 info->upper_dev); 1878 else 1879 ocelot_port_lag_leave(ocelot, port, 1880 info->upper_dev); 1881 } 1882 break; 1883 default: 1884 break; 1885 } 1886 1887 return err; 1888 } 1889 1890 static int ocelot_netdevice_event(struct notifier_block *unused, 1891 unsigned long event, void *ptr) 1892 { 1893 struct netdev_notifier_changeupper_info *info = ptr; 1894 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 1895 int ret = 0; 1896 1897 if (!ocelot_netdevice_dev_check(dev)) 1898 return 0; 1899 1900 if (event == NETDEV_PRECHANGEUPPER && 1901 netif_is_lag_master(info->upper_dev)) { 1902 struct netdev_lag_upper_info *lag_upper_info = info->upper_info; 1903 struct netlink_ext_ack *extack; 1904 1905 if (lag_upper_info && 1906 lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 1907 extack = netdev_notifier_info_to_extack(&info->info); 1908 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type"); 1909 1910 ret = -EINVAL; 1911 goto notify; 1912 } 1913 } 1914 1915 if (netif_is_lag_master(dev)) { 1916 struct net_device *slave; 1917 struct list_head *iter; 1918 1919 netdev_for_each_lower_dev(dev, slave, iter) { 1920 ret = ocelot_netdevice_port_event(slave, event, info); 1921 if (ret) 1922 goto notify; 1923 } 1924 } else { 1925 ret = ocelot_netdevice_port_event(dev, event, info); 1926 } 1927 1928 notify: 1929 return notifier_from_errno(ret); 1930 } 1931 1932 struct notifier_block ocelot_netdevice_nb __read_mostly = { 1933 .notifier_call = ocelot_netdevice_event, 1934 }; 1935 EXPORT_SYMBOL(ocelot_netdevice_nb); 1936 1937 static int ocelot_switchdev_event(struct notifier_block *unused, 1938 unsigned long event, void *ptr) 1939 { 1940 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1941 int err; 1942 1943 switch (event) { 1944 case SWITCHDEV_PORT_ATTR_SET: 1945 err = switchdev_handle_port_attr_set(dev, ptr, 1946 ocelot_netdevice_dev_check, 1947 ocelot_port_attr_set); 1948 return notifier_from_errno(err); 1949 } 1950 1951 return NOTIFY_DONE; 1952 } 1953 1954 struct notifier_block ocelot_switchdev_nb __read_mostly = { 1955 .notifier_call = ocelot_switchdev_event, 1956 }; 1957 EXPORT_SYMBOL(ocelot_switchdev_nb); 1958 1959 static int ocelot_switchdev_blocking_event(struct notifier_block *unused, 1960 unsigned long event, void *ptr) 1961 { 1962 struct net_device *dev = switchdev_notifier_info_to_dev(ptr); 1963 int err; 1964 1965 switch (event) { 1966 /* Blocking events. */ 1967 case SWITCHDEV_PORT_OBJ_ADD: 1968 err = switchdev_handle_port_obj_add(dev, ptr, 1969 ocelot_netdevice_dev_check, 1970 ocelot_port_obj_add); 1971 return notifier_from_errno(err); 1972 case SWITCHDEV_PORT_OBJ_DEL: 1973 err = switchdev_handle_port_obj_del(dev, ptr, 1974 ocelot_netdevice_dev_check, 1975 ocelot_port_obj_del); 1976 return notifier_from_errno(err); 1977 case SWITCHDEV_PORT_ATTR_SET: 1978 err = switchdev_handle_port_attr_set(dev, ptr, 1979 ocelot_netdevice_dev_check, 1980 ocelot_port_attr_set); 1981 return notifier_from_errno(err); 1982 } 1983 1984 return NOTIFY_DONE; 1985 } 1986 1987 struct notifier_block ocelot_switchdev_blocking_nb __read_mostly = { 1988 .notifier_call = ocelot_switchdev_blocking_event, 1989 }; 1990 EXPORT_SYMBOL(ocelot_switchdev_blocking_nb); 1991 1992 int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts) 1993 { 1994 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 1995 unsigned long flags; 1996 time64_t s; 1997 u32 val; 1998 s64 ns; 1999 2000 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 2001 2002 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 2003 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 2004 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_SAVE); 2005 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 2006 2007 s = ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN) & 0xffff; 2008 s <<= 32; 2009 s += ocelot_read_rix(ocelot, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 2010 ns = ocelot_read_rix(ocelot, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 2011 2012 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2013 2014 /* Deal with negative values */ 2015 if (ns >= 0x3ffffff0 && ns <= 0x3fffffff) { 2016 s--; 2017 ns &= 0xf; 2018 ns += 999999984; 2019 } 2020 2021 set_normalized_timespec64(ts, s, ns); 2022 return 0; 2023 } 2024 EXPORT_SYMBOL(ocelot_ptp_gettime64); 2025 2026 static int ocelot_ptp_settime64(struct ptp_clock_info *ptp, 2027 const struct timespec64 *ts) 2028 { 2029 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 2030 unsigned long flags; 2031 u32 val; 2032 2033 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 2034 2035 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 2036 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 2037 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); 2038 2039 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 2040 2041 ocelot_write_rix(ocelot, lower_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_LSB, 2042 TOD_ACC_PIN); 2043 ocelot_write_rix(ocelot, upper_32_bits(ts->tv_sec), PTP_PIN_TOD_SEC_MSB, 2044 TOD_ACC_PIN); 2045 ocelot_write_rix(ocelot, ts->tv_nsec, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 2046 2047 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 2048 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 2049 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_LOAD); 2050 2051 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 2052 2053 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2054 return 0; 2055 } 2056 2057 static int ocelot_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 2058 { 2059 if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) { 2060 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 2061 unsigned long flags; 2062 u32 val; 2063 2064 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 2065 2066 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 2067 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 2068 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_IDLE); 2069 2070 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 2071 2072 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_LSB, TOD_ACC_PIN); 2073 ocelot_write_rix(ocelot, 0, PTP_PIN_TOD_SEC_MSB, TOD_ACC_PIN); 2074 ocelot_write_rix(ocelot, delta, PTP_PIN_TOD_NSEC, TOD_ACC_PIN); 2075 2076 val = ocelot_read_rix(ocelot, PTP_PIN_CFG, TOD_ACC_PIN); 2077 val &= ~(PTP_PIN_CFG_SYNC | PTP_PIN_CFG_ACTION_MASK | PTP_PIN_CFG_DOM); 2078 val |= PTP_PIN_CFG_ACTION(PTP_PIN_ACTION_DELTA); 2079 2080 ocelot_write_rix(ocelot, val, PTP_PIN_CFG, TOD_ACC_PIN); 2081 2082 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2083 } else { 2084 /* Fall back using ocelot_ptp_settime64 which is not exact. */ 2085 struct timespec64 ts; 2086 u64 now; 2087 2088 ocelot_ptp_gettime64(ptp, &ts); 2089 2090 now = ktime_to_ns(timespec64_to_ktime(ts)); 2091 ts = ns_to_timespec64(now + delta); 2092 2093 ocelot_ptp_settime64(ptp, &ts); 2094 } 2095 return 0; 2096 } 2097 2098 static int ocelot_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) 2099 { 2100 struct ocelot *ocelot = container_of(ptp, struct ocelot, ptp_info); 2101 u32 unit = 0, direction = 0; 2102 unsigned long flags; 2103 u64 adj = 0; 2104 2105 spin_lock_irqsave(&ocelot->ptp_clock_lock, flags); 2106 2107 if (!scaled_ppm) 2108 goto disable_adj; 2109 2110 if (scaled_ppm < 0) { 2111 direction = PTP_CFG_CLK_ADJ_CFG_DIR; 2112 scaled_ppm = -scaled_ppm; 2113 } 2114 2115 adj = PSEC_PER_SEC << 16; 2116 do_div(adj, scaled_ppm); 2117 do_div(adj, 1000); 2118 2119 /* If the adjustment value is too large, use ns instead */ 2120 if (adj >= (1L << 30)) { 2121 unit = PTP_CFG_CLK_ADJ_FREQ_NS; 2122 do_div(adj, 1000); 2123 } 2124 2125 /* Still too big */ 2126 if (adj >= (1L << 30)) 2127 goto disable_adj; 2128 2129 ocelot_write(ocelot, unit | adj, PTP_CLK_CFG_ADJ_FREQ); 2130 ocelot_write(ocelot, PTP_CFG_CLK_ADJ_CFG_ENA | direction, 2131 PTP_CLK_CFG_ADJ_CFG); 2132 2133 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2134 return 0; 2135 2136 disable_adj: 2137 ocelot_write(ocelot, 0, PTP_CLK_CFG_ADJ_CFG); 2138 2139 spin_unlock_irqrestore(&ocelot->ptp_clock_lock, flags); 2140 return 0; 2141 } 2142 2143 static struct ptp_clock_info ocelot_ptp_clock_info = { 2144 .owner = THIS_MODULE, 2145 .name = "ocelot ptp", 2146 .max_adj = 0x7fffffff, 2147 .n_alarm = 0, 2148 .n_ext_ts = 0, 2149 .n_per_out = 0, 2150 .n_pins = 0, 2151 .pps = 0, 2152 .gettime64 = ocelot_ptp_gettime64, 2153 .settime64 = ocelot_ptp_settime64, 2154 .adjtime = ocelot_ptp_adjtime, 2155 .adjfine = ocelot_ptp_adjfine, 2156 }; 2157 2158 static int ocelot_init_timestamp(struct ocelot *ocelot) 2159 { 2160 struct ptp_clock *ptp_clock; 2161 2162 ocelot->ptp_info = ocelot_ptp_clock_info; 2163 ptp_clock = ptp_clock_register(&ocelot->ptp_info, ocelot->dev); 2164 if (IS_ERR(ptp_clock)) 2165 return PTR_ERR(ptp_clock); 2166 /* Check if PHC support is missing at the configuration level */ 2167 if (!ptp_clock) 2168 return 0; 2169 2170 ocelot->ptp_clock = ptp_clock; 2171 2172 ocelot_write(ocelot, SYS_PTP_CFG_PTP_STAMP_WID(30), SYS_PTP_CFG); 2173 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_LOW); 2174 ocelot_write(ocelot, 0xffffffff, ANA_TABLES_PTP_ID_HIGH); 2175 2176 ocelot_write(ocelot, PTP_CFG_MISC_PTP_EN, PTP_CFG_MISC); 2177 2178 /* There is no device reconfiguration, PTP Rx stamping is always 2179 * enabled. 2180 */ 2181 ocelot->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 2182 2183 return 0; 2184 } 2185 2186 /* Configure the maximum SDU (L2 payload) on RX to the value specified in @sdu. 2187 * The length of VLAN tags is accounted for automatically via DEV_MAC_TAGS_CFG. 2188 * In the special case that it's the NPI port that we're configuring, the 2189 * length of the tag and optional prefix needs to be accounted for privately, 2190 * in order to be able to sustain communication at the requested @sdu. 2191 */ 2192 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu) 2193 { 2194 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2195 int maxlen = sdu + ETH_HLEN + ETH_FCS_LEN; 2196 int atop_wm; 2197 2198 if (port == ocelot->npi) { 2199 maxlen += OCELOT_TAG_LEN; 2200 2201 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2202 maxlen += OCELOT_SHORT_PREFIX_LEN; 2203 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 2204 maxlen += OCELOT_LONG_PREFIX_LEN; 2205 } 2206 2207 ocelot_port_writel(ocelot_port, maxlen, DEV_MAC_MAXLEN_CFG); 2208 2209 /* Set Pause WM hysteresis 2210 * 152 = 6 * maxlen / OCELOT_BUFFER_CELL_SZ 2211 * 101 = 4 * maxlen / OCELOT_BUFFER_CELL_SZ 2212 */ 2213 ocelot_write_rix(ocelot, SYS_PAUSE_CFG_PAUSE_ENA | 2214 SYS_PAUSE_CFG_PAUSE_STOP(101) | 2215 SYS_PAUSE_CFG_PAUSE_START(152), SYS_PAUSE_CFG, port); 2216 2217 /* Tail dropping watermark */ 2218 atop_wm = (ocelot->shared_queue_sz - 9 * maxlen) / 2219 OCELOT_BUFFER_CELL_SZ; 2220 ocelot_write_rix(ocelot, ocelot_wm_enc(9 * maxlen), 2221 SYS_ATOP, port); 2222 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG); 2223 } 2224 EXPORT_SYMBOL(ocelot_port_set_maxlen); 2225 2226 int ocelot_get_max_mtu(struct ocelot *ocelot, int port) 2227 { 2228 int max_mtu = 65535 - ETH_HLEN - ETH_FCS_LEN; 2229 2230 if (port == ocelot->npi) { 2231 max_mtu -= OCELOT_TAG_LEN; 2232 2233 if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_SHORT) 2234 max_mtu -= OCELOT_SHORT_PREFIX_LEN; 2235 else if (ocelot->inj_prefix == OCELOT_TAG_PREFIX_LONG) 2236 max_mtu -= OCELOT_LONG_PREFIX_LEN; 2237 } 2238 2239 return max_mtu; 2240 } 2241 EXPORT_SYMBOL(ocelot_get_max_mtu); 2242 2243 void ocelot_init_port(struct ocelot *ocelot, int port) 2244 { 2245 struct ocelot_port *ocelot_port = ocelot->ports[port]; 2246 2247 skb_queue_head_init(&ocelot_port->tx_skbs); 2248 2249 /* Basic L2 initialization */ 2250 2251 /* Set MAC IFG Gaps 2252 * FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 0 2253 * !FDX: TX_IFG = 5, RX_IFG1 = RX_IFG2 = 5 2254 */ 2255 ocelot_port_writel(ocelot_port, DEV_MAC_IFG_CFG_TX_IFG(5), 2256 DEV_MAC_IFG_CFG); 2257 2258 /* Load seed (0) and set MAC HDX late collision */ 2259 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67) | 2260 DEV_MAC_HDX_CFG_SEED_LOAD, 2261 DEV_MAC_HDX_CFG); 2262 mdelay(1); 2263 ocelot_port_writel(ocelot_port, DEV_MAC_HDX_CFG_LATE_COL_POS(67), 2264 DEV_MAC_HDX_CFG); 2265 2266 /* Set Max Length and maximum tags allowed */ 2267 ocelot_port_set_maxlen(ocelot, port, ETH_DATA_LEN); 2268 ocelot_port_writel(ocelot_port, DEV_MAC_TAGS_CFG_TAG_ID(ETH_P_8021AD) | 2269 DEV_MAC_TAGS_CFG_VLAN_AWR_ENA | 2270 DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA | 2271 DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, 2272 DEV_MAC_TAGS_CFG); 2273 2274 /* Set SMAC of Pause frame (00:00:00:00:00:00) */ 2275 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_HIGH_CFG); 2276 ocelot_port_writel(ocelot_port, 0, DEV_MAC_FC_MAC_LOW_CFG); 2277 2278 /* Drop frames with multicast source address */ 2279 ocelot_rmw_gix(ocelot, ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2280 ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA, 2281 ANA_PORT_DROP_CFG, port); 2282 2283 /* Set default VLAN and tag type to 8021Q. */ 2284 ocelot_rmw_gix(ocelot, REW_PORT_VLAN_CFG_PORT_TPID(ETH_P_8021Q), 2285 REW_PORT_VLAN_CFG_PORT_TPID_M, 2286 REW_PORT_VLAN_CFG, port); 2287 2288 /* Enable vcap lookups */ 2289 ocelot_vcap_enable(ocelot, port); 2290 } 2291 EXPORT_SYMBOL(ocelot_init_port); 2292 2293 int ocelot_probe_port(struct ocelot *ocelot, u8 port, 2294 void __iomem *regs, 2295 struct phy_device *phy) 2296 { 2297 struct ocelot_port_private *priv; 2298 struct ocelot_port *ocelot_port; 2299 struct net_device *dev; 2300 int err; 2301 2302 dev = alloc_etherdev(sizeof(struct ocelot_port_private)); 2303 if (!dev) 2304 return -ENOMEM; 2305 SET_NETDEV_DEV(dev, ocelot->dev); 2306 priv = netdev_priv(dev); 2307 priv->dev = dev; 2308 priv->phy = phy; 2309 priv->chip_port = port; 2310 ocelot_port = &priv->port; 2311 ocelot_port->ocelot = ocelot; 2312 ocelot_port->regs = regs; 2313 ocelot->ports[port] = ocelot_port; 2314 2315 dev->netdev_ops = &ocelot_port_netdev_ops; 2316 dev->ethtool_ops = &ocelot_ethtool_ops; 2317 2318 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_RXFCS | 2319 NETIF_F_HW_TC; 2320 dev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC; 2321 2322 memcpy(dev->dev_addr, ocelot->base_mac, ETH_ALEN); 2323 dev->dev_addr[ETH_ALEN - 1] += port; 2324 ocelot_mact_learn(ocelot, PGID_CPU, dev->dev_addr, ocelot_port->pvid, 2325 ENTRYTYPE_LOCKED); 2326 2327 ocelot_init_port(ocelot, port); 2328 2329 err = register_netdev(dev); 2330 if (err) { 2331 dev_err(ocelot->dev, "register_netdev failed\n"); 2332 free_netdev(dev); 2333 } 2334 2335 return err; 2336 } 2337 EXPORT_SYMBOL(ocelot_probe_port); 2338 2339 /* Configure and enable the CPU port module, which is a set of queues. 2340 * If @npi contains a valid port index, the CPU port module is connected 2341 * to the Node Processor Interface (NPI). This is the mode through which 2342 * frames can be injected from and extracted to an external CPU, 2343 * over Ethernet. 2344 */ 2345 void ocelot_configure_cpu(struct ocelot *ocelot, int npi, 2346 enum ocelot_tag_prefix injection, 2347 enum ocelot_tag_prefix extraction) 2348 { 2349 int cpu = ocelot->num_phys_ports; 2350 2351 ocelot->npi = npi; 2352 ocelot->inj_prefix = injection; 2353 ocelot->xtr_prefix = extraction; 2354 2355 /* The unicast destination PGID for the CPU port module is unused */ 2356 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, cpu); 2357 /* Instead set up a multicast destination PGID for traffic copied to 2358 * the CPU. Whitelisted MAC addresses like the port netdevice MAC 2359 * addresses will be copied to the CPU via this PGID. 2360 */ 2361 ocelot_write_rix(ocelot, BIT(cpu), ANA_PGID_PGID, PGID_CPU); 2362 ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_RECV_ENA | 2363 ANA_PORT_PORT_CFG_PORTID_VAL(cpu), 2364 ANA_PORT_PORT_CFG, cpu); 2365 2366 if (npi >= 0 && npi < ocelot->num_phys_ports) { 2367 ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M | 2368 QSYS_EXT_CPU_CFG_EXT_CPU_PORT(npi), 2369 QSYS_EXT_CPU_CFG); 2370 2371 /* Enable NPI port */ 2372 ocelot_write_rix(ocelot, 2373 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 2374 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 2375 QSYS_SWITCH_PORT_MODE_PORT_ENA, 2376 QSYS_SWITCH_PORT_MODE, npi); 2377 /* NPI port Injection/Extraction configuration */ 2378 ocelot_write_rix(ocelot, 2379 SYS_PORT_MODE_INCL_XTR_HDR(extraction) | 2380 SYS_PORT_MODE_INCL_INJ_HDR(injection), 2381 SYS_PORT_MODE, npi); 2382 } 2383 2384 /* Enable CPU port module */ 2385 ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE | 2386 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) | 2387 QSYS_SWITCH_PORT_MODE_PORT_ENA, 2388 QSYS_SWITCH_PORT_MODE, cpu); 2389 /* CPU port Injection/Extraction configuration */ 2390 ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) | 2391 SYS_PORT_MODE_INCL_INJ_HDR(injection), 2392 SYS_PORT_MODE, cpu); 2393 2394 /* Configure the CPU port to be VLAN aware */ 2395 ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) | 2396 ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA | 2397 ANA_PORT_VLAN_CFG_VLAN_POP_CNT(1), 2398 ANA_PORT_VLAN_CFG, cpu); 2399 } 2400 EXPORT_SYMBOL(ocelot_configure_cpu); 2401 2402 int ocelot_init(struct ocelot *ocelot) 2403 { 2404 char queue_name[32]; 2405 int i, ret; 2406 u32 port; 2407 2408 if (ocelot->ops->reset) { 2409 ret = ocelot->ops->reset(ocelot); 2410 if (ret) { 2411 dev_err(ocelot->dev, "Switch reset failed\n"); 2412 return ret; 2413 } 2414 } 2415 2416 ocelot->lags = devm_kcalloc(ocelot->dev, ocelot->num_phys_ports, 2417 sizeof(u32), GFP_KERNEL); 2418 if (!ocelot->lags) 2419 return -ENOMEM; 2420 2421 ocelot->stats = devm_kcalloc(ocelot->dev, 2422 ocelot->num_phys_ports * ocelot->num_stats, 2423 sizeof(u64), GFP_KERNEL); 2424 if (!ocelot->stats) 2425 return -ENOMEM; 2426 2427 mutex_init(&ocelot->stats_lock); 2428 mutex_init(&ocelot->ptp_lock); 2429 spin_lock_init(&ocelot->ptp_clock_lock); 2430 snprintf(queue_name, sizeof(queue_name), "%s-stats", 2431 dev_name(ocelot->dev)); 2432 ocelot->stats_queue = create_singlethread_workqueue(queue_name); 2433 if (!ocelot->stats_queue) 2434 return -ENOMEM; 2435 2436 INIT_LIST_HEAD(&ocelot->multicast); 2437 ocelot_mact_init(ocelot); 2438 ocelot_vlan_init(ocelot); 2439 ocelot_ace_init(ocelot); 2440 2441 for (port = 0; port < ocelot->num_phys_ports; port++) { 2442 /* Clear all counters (5 groups) */ 2443 ocelot_write(ocelot, SYS_STAT_CFG_STAT_VIEW(port) | 2444 SYS_STAT_CFG_STAT_CLEAR_SHOT(0x7f), 2445 SYS_STAT_CFG); 2446 } 2447 2448 /* Only use S-Tag */ 2449 ocelot_write(ocelot, ETH_P_8021AD, SYS_VLAN_ETYPE_CFG); 2450 2451 /* Aggregation mode */ 2452 ocelot_write(ocelot, ANA_AGGR_CFG_AC_SMAC_ENA | 2453 ANA_AGGR_CFG_AC_DMAC_ENA | 2454 ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA | 2455 ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA, ANA_AGGR_CFG); 2456 2457 /* Set MAC age time to default value. The entry is aged after 2458 * 2*AGE_PERIOD 2459 */ 2460 ocelot_write(ocelot, 2461 ANA_AUTOAGE_AGE_PERIOD(BR_DEFAULT_AGEING_TIME / 2 / HZ), 2462 ANA_AUTOAGE); 2463 2464 /* Disable learning for frames discarded by VLAN ingress filtering */ 2465 regmap_field_write(ocelot->regfields[ANA_ADVLEARN_VLAN_CHK], 1); 2466 2467 /* Setup frame ageing - fixed value "2 sec" - in 6.5 us units */ 2468 ocelot_write(ocelot, SYS_FRM_AGING_AGE_TX_ENA | 2469 SYS_FRM_AGING_MAX_AGE(307692), SYS_FRM_AGING); 2470 2471 /* Setup flooding PGIDs */ 2472 ocelot_write_rix(ocelot, ANA_FLOODING_FLD_MULTICAST(PGID_MC) | 2473 ANA_FLOODING_FLD_BROADCAST(PGID_MC) | 2474 ANA_FLOODING_FLD_UNICAST(PGID_UC), 2475 ANA_FLOODING, 0); 2476 ocelot_write(ocelot, ANA_FLOODING_IPMC_FLD_MC6_DATA(PGID_MCIPV6) | 2477 ANA_FLOODING_IPMC_FLD_MC6_CTRL(PGID_MC) | 2478 ANA_FLOODING_IPMC_FLD_MC4_DATA(PGID_MCIPV4) | 2479 ANA_FLOODING_IPMC_FLD_MC4_CTRL(PGID_MC), 2480 ANA_FLOODING_IPMC); 2481 2482 for (port = 0; port < ocelot->num_phys_ports; port++) { 2483 /* Transmit the frame to the local port. */ 2484 ocelot_write_rix(ocelot, BIT(port), ANA_PGID_PGID, port); 2485 /* Do not forward BPDU frames to the front ports. */ 2486 ocelot_write_gix(ocelot, 2487 ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(0xffff), 2488 ANA_PORT_CPU_FWD_BPDU_CFG, 2489 port); 2490 /* Ensure bridging is disabled */ 2491 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_SRC + port); 2492 } 2493 2494 /* Allow broadcast MAC frames. */ 2495 for (i = ocelot->num_phys_ports + 1; i < PGID_CPU; i++) { 2496 u32 val = ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports - 1, 0)); 2497 2498 ocelot_write_rix(ocelot, val, ANA_PGID_PGID, i); 2499 } 2500 ocelot_write_rix(ocelot, 2501 ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)), 2502 ANA_PGID_PGID, PGID_MC); 2503 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV4); 2504 ocelot_write_rix(ocelot, 0, ANA_PGID_PGID, PGID_MCIPV6); 2505 2506 /* Allow manual injection via DEVCPU_QS registers, and byte swap these 2507 * registers endianness. 2508 */ 2509 ocelot_write_rix(ocelot, QS_INJ_GRP_CFG_BYTE_SWAP | 2510 QS_INJ_GRP_CFG_MODE(1), QS_INJ_GRP_CFG, 0); 2511 ocelot_write_rix(ocelot, QS_XTR_GRP_CFG_BYTE_SWAP | 2512 QS_XTR_GRP_CFG_MODE(1), QS_XTR_GRP_CFG, 0); 2513 ocelot_write(ocelot, ANA_CPUQ_CFG_CPUQ_MIRROR(2) | 2514 ANA_CPUQ_CFG_CPUQ_LRN(2) | 2515 ANA_CPUQ_CFG_CPUQ_MAC_COPY(2) | 2516 ANA_CPUQ_CFG_CPUQ_SRC_COPY(2) | 2517 ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(2) | 2518 ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(6) | 2519 ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(6) | 2520 ANA_CPUQ_CFG_CPUQ_IGMP(6) | 2521 ANA_CPUQ_CFG_CPUQ_MLD(6), ANA_CPUQ_CFG); 2522 for (i = 0; i < 16; i++) 2523 ocelot_write_rix(ocelot, ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(6) | 2524 ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(6), 2525 ANA_CPUQ_8021_CFG, i); 2526 2527 INIT_DELAYED_WORK(&ocelot->stats_work, ocelot_check_stats_work); 2528 queue_delayed_work(ocelot->stats_queue, &ocelot->stats_work, 2529 OCELOT_STATS_CHECK_DELAY); 2530 2531 if (ocelot->ptp) { 2532 ret = ocelot_init_timestamp(ocelot); 2533 if (ret) { 2534 dev_err(ocelot->dev, 2535 "Timestamp initialization failed\n"); 2536 return ret; 2537 } 2538 } 2539 2540 return 0; 2541 } 2542 EXPORT_SYMBOL(ocelot_init); 2543 2544 void ocelot_deinit(struct ocelot *ocelot) 2545 { 2546 struct ocelot_port *port; 2547 int i; 2548 2549 cancel_delayed_work(&ocelot->stats_work); 2550 destroy_workqueue(ocelot->stats_queue); 2551 mutex_destroy(&ocelot->stats_lock); 2552 if (ocelot->ptp_clock) 2553 ptp_clock_unregister(ocelot->ptp_clock); 2554 2555 for (i = 0; i < ocelot->num_phys_ports; i++) { 2556 port = ocelot->ports[i]; 2557 skb_queue_purge(&port->tx_skbs); 2558 } 2559 } 2560 EXPORT_SYMBOL(ocelot_deinit); 2561 2562 MODULE_LICENSE("Dual MIT/GPL"); 2563