1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2019 Marvell International Ltd.
4 *
5 * Device tree for the CN9131-DB board.
6 */
7
8#include "cn9130-db.dts"
9
10/ {
11	model = "Marvell Armada CN9131-DB";
12	compatible = "marvell,cn9131", "marvell,cn9130",
13		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
14
15	aliases {
16		gpio3 = &cp1_gpio1;
17		gpio4 = &cp1_gpio2;
18		ethernet3 = &cp1_eth0;
19		ethernet4 = &cp1_eth1;
20	};
21
22	cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
23		compatible = "regulator-fixed";
24		pinctrl-names = "default";
25		pinctrl-0 = <&cp1_xhci0_vbus_pins>;
26		regulator-name = "cp1-xhci0-vbus";
27		regulator-min-microvolt = <5000000>;
28		regulator-max-microvolt = <5000000>;
29		enable-active-high;
30		gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
31	};
32
33	cp1_usb3_0_phy0: cp1_usb3_phy0 {
34		compatible = "usb-nop-xceiv";
35		vcc-supply = <&cp1_reg_usb3_vbus0>;
36	};
37
38	cp1_sfp_eth1: sfp-eth1 {
39		compatible = "sff,sfp";
40		i2c-bus = <&cp1_i2c0>;
41		los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
42		mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
43		tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
44		tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
45		pinctrl-names = "default";
46		pinctrl-0 = <&cp1_sfp_pins>;
47		/*
48		 * SFP cages are unconnected on early PCBs because of an the I2C
49		 * lanes not being connected. Prevent the port for being
50		 * unusable by disabling the SFP node.
51		 */
52		status = "disabled";
53	};
54};
55
56/*
57 * Instantiate the first slave CP115
58 */
59
60#define CP11X_NAME		cp1
61#define CP11X_BASE		f4000000
62#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
63#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
64#define CP11X_PCIE0_BASE	f4600000
65#define CP11X_PCIE1_BASE	f4620000
66#define CP11X_PCIE2_BASE	f4640000
67
68#include "armada-cp115.dtsi"
69
70#undef CP11X_NAME
71#undef CP11X_BASE
72#undef CP11X_PCIEx_MEM_BASE
73#undef CP11X_PCIEx_MEM_SIZE
74#undef CP11X_PCIE0_BASE
75#undef CP11X_PCIE1_BASE
76#undef CP11X_PCIE2_BASE
77
78&cp1_crypto {
79	status = "disabled";
80};
81
82&cp1_ethernet {
83	status = "okay";
84};
85
86/* CON50 */
87&cp1_eth0 {
88	status = "disabled";
89	phy-mode = "10gbase-kr";
90	/* Generic PHY, providing serdes lanes */
91	phys = <&cp1_comphy4 0>;
92	managed = "in-band-status";
93	sfp = <&cp1_sfp_eth1>;
94};
95
96&cp1_gpio1 {
97	status = "okay";
98};
99
100&cp1_gpio2 {
101	status = "okay";
102};
103
104&cp1_i2c0 {
105	status = "okay";
106	pinctrl-names = "default";
107	pinctrl-0 = <&cp1_i2c0_pins>;
108	clock-frequency = <100000>;
109};
110
111/* CON40 */
112&cp1_pcie0 {
113	pinctrl-names = "default";
114	pinctrl-0 = <&cp1_pcie_reset_pins>;
115	num-lanes = <2>;
116	num-viewport = <8>;
117	marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
118	status = "okay";
119	/* Generic PHY, providing serdes lanes */
120	phys = <&cp1_comphy0 0
121		&cp1_comphy1 0>;
122};
123
124&cp1_sata0 {
125	status = "okay";
126
127	/* CON32 */
128	sata-port@1 {
129		/* Generic PHY, providing serdes lanes */
130		phys = <&cp1_comphy5 1>;
131	};
132};
133
134/* U24 */
135&cp1_spi1 {
136	status = "okay";
137	pinctrl-names = "default";
138	pinctrl-0 = <&cp1_spi0_pins>;
139	reg = <0x700680 0x50>;
140
141	spi-flash@0 {
142		#address-cells = <0x1>;
143		#size-cells = <0x1>;
144		compatible = "jedec,spi-nor";
145		reg = <0x0>;
146		/* On-board MUX does not allow higher frequencies */
147		spi-max-frequency = <40000000>;
148
149		partitions {
150			compatible = "fixed-partitions";
151			#address-cells = <1>;
152			#size-cells = <1>;
153
154			partition@0 {
155				label = "U-Boot-1";
156				reg = <0x0 0x200000>;
157			};
158
159			partition@400000 {
160				label = "Filesystem-1";
161				reg = <0x200000 0xe00000>;
162			};
163		};
164	};
165
166};
167
168&cp1_syscon0 {
169	cp1_pinctrl: pinctrl {
170		compatible = "marvell,cp115-standalone-pinctrl";
171
172		cp1_i2c0_pins: cp1-i2c-pins-0 {
173			marvell,pins = "mpp37", "mpp38";
174			marvell,function = "i2c0";
175		};
176		cp1_spi0_pins: cp1-spi-pins-0 {
177			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
178			marvell,function = "spi1";
179		};
180		cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
181			marvell,pins = "mpp3";
182			marvell,function = "gpio";
183		};
184		cp1_sfp_pins: sfp-pins {
185			marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
186			marvell,function = "gpio";
187		};
188		cp1_pcie_reset_pins: cp1-pcie-reset-pins {
189			marvell,pins = "mpp0";
190			marvell,function = "gpio";
191		};
192	};
193};
194
195/* CON58 */
196&cp1_usb3_1 {
197	status = "okay";
198	usb-phy = <&cp1_usb3_0_phy0>;
199	/* Generic PHY, providing serdes lanes */
200	phys = <&cp1_comphy3 1>;
201	phy-names = "usb";
202};
203