1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ti-sysc.c - Texas Instruments sysc interconnect target driver 4 */ 5 6 #include <linux/io.h> 7 #include <linux/clk.h> 8 #include <linux/clkdev.h> 9 #include <linux/delay.h> 10 #include <linux/list.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_domain.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <linux/of_address.h> 17 #include <linux/of_platform.h> 18 #include <linux/slab.h> 19 #include <linux/sys_soc.h> 20 #include <linux/iopoll.h> 21 22 #include <linux/platform_data/ti-sysc.h> 23 24 #include <dt-bindings/bus/ti-sysc.h> 25 26 #define DIS_ISP BIT(2) 27 #define DIS_IVA BIT(1) 28 #define DIS_SGX BIT(0) 29 30 #define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), } 31 32 #define MAX_MODULE_SOFTRESET_WAIT 10000 33 34 enum sysc_soc { 35 SOC_UNKNOWN, 36 SOC_2420, 37 SOC_2430, 38 SOC_3430, 39 SOC_3630, 40 SOC_4430, 41 SOC_4460, 42 SOC_4470, 43 SOC_5430, 44 SOC_AM3, 45 SOC_AM4, 46 SOC_DRA7, 47 }; 48 49 struct sysc_address { 50 unsigned long base; 51 struct list_head node; 52 }; 53 54 struct sysc_soc_info { 55 unsigned long general_purpose:1; 56 enum sysc_soc soc; 57 struct mutex list_lock; /* disabled modules list lock */ 58 struct list_head disabled_modules; 59 }; 60 61 enum sysc_clocks { 62 SYSC_FCK, 63 SYSC_ICK, 64 SYSC_OPTFCK0, 65 SYSC_OPTFCK1, 66 SYSC_OPTFCK2, 67 SYSC_OPTFCK3, 68 SYSC_OPTFCK4, 69 SYSC_OPTFCK5, 70 SYSC_OPTFCK6, 71 SYSC_OPTFCK7, 72 SYSC_MAX_CLOCKS, 73 }; 74 75 static struct sysc_soc_info *sysc_soc; 76 static const char * const reg_names[] = { "rev", "sysc", "syss", }; 77 static const char * const clock_names[SYSC_MAX_CLOCKS] = { 78 "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4", 79 "opt5", "opt6", "opt7", 80 }; 81 82 #define SYSC_IDLEMODE_MASK 3 83 #define SYSC_CLOCKACTIVITY_MASK 3 84 85 /** 86 * struct sysc - TI sysc interconnect target module registers and capabilities 87 * @dev: struct device pointer 88 * @module_pa: physical address of the interconnect target module 89 * @module_size: size of the interconnect target module 90 * @module_va: virtual address of the interconnect target module 91 * @offsets: register offsets from module base 92 * @mdata: ti-sysc to hwmod translation data for a module 93 * @clocks: clocks used by the interconnect target module 94 * @clock_roles: clock role names for the found clocks 95 * @nr_clocks: number of clocks used by the interconnect target module 96 * @rsts: resets used by the interconnect target module 97 * @legacy_mode: configured for legacy mode if set 98 * @cap: interconnect target module capabilities 99 * @cfg: interconnect target module configuration 100 * @cookie: data used by legacy platform callbacks 101 * @name: name if available 102 * @revision: interconnect target module revision 103 * @enabled: sysc runtime enabled status 104 * @needs_resume: runtime resume needed on resume from suspend 105 * @child_needs_resume: runtime resume needed for child on resume from suspend 106 * @disable_on_idle: status flag used for disabling modules with resets 107 * @idle_work: work structure used to perform delayed idle on a module 108 * @pre_reset_quirk: module specific pre-reset quirk 109 * @post_reset_quirk: module specific post-reset quirk 110 * @reset_done_quirk: module specific reset done quirk 111 * @module_enable_quirk: module specific enable quirk 112 * @module_disable_quirk: module specific disable quirk 113 * @module_unlock_quirk: module specific sysconfig unlock quirk 114 * @module_lock_quirk: module specific sysconfig lock quirk 115 */ 116 struct sysc { 117 struct device *dev; 118 u64 module_pa; 119 u32 module_size; 120 void __iomem *module_va; 121 int offsets[SYSC_MAX_REGS]; 122 struct ti_sysc_module_data *mdata; 123 struct clk **clocks; 124 const char **clock_roles; 125 int nr_clocks; 126 struct reset_control *rsts; 127 const char *legacy_mode; 128 const struct sysc_capabilities *cap; 129 struct sysc_config cfg; 130 struct ti_sysc_cookie cookie; 131 const char *name; 132 u32 revision; 133 unsigned int enabled:1; 134 unsigned int needs_resume:1; 135 unsigned int child_needs_resume:1; 136 struct delayed_work idle_work; 137 void (*pre_reset_quirk)(struct sysc *sysc); 138 void (*post_reset_quirk)(struct sysc *sysc); 139 void (*reset_done_quirk)(struct sysc *sysc); 140 void (*module_enable_quirk)(struct sysc *sysc); 141 void (*module_disable_quirk)(struct sysc *sysc); 142 void (*module_unlock_quirk)(struct sysc *sysc); 143 void (*module_lock_quirk)(struct sysc *sysc); 144 }; 145 146 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 147 bool is_child); 148 149 static void sysc_write(struct sysc *ddata, int offset, u32 value) 150 { 151 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 152 writew_relaxed(value & 0xffff, ddata->module_va + offset); 153 154 /* Only i2c revision has LO and HI register with stride of 4 */ 155 if (ddata->offsets[SYSC_REVISION] >= 0 && 156 offset == ddata->offsets[SYSC_REVISION]) { 157 u16 hi = value >> 16; 158 159 writew_relaxed(hi, ddata->module_va + offset + 4); 160 } 161 162 return; 163 } 164 165 writel_relaxed(value, ddata->module_va + offset); 166 } 167 168 static u32 sysc_read(struct sysc *ddata, int offset) 169 { 170 if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) { 171 u32 val; 172 173 val = readw_relaxed(ddata->module_va + offset); 174 175 /* Only i2c revision has LO and HI register with stride of 4 */ 176 if (ddata->offsets[SYSC_REVISION] >= 0 && 177 offset == ddata->offsets[SYSC_REVISION]) { 178 u16 tmp = readw_relaxed(ddata->module_va + offset + 4); 179 180 val |= tmp << 16; 181 } 182 183 return val; 184 } 185 186 return readl_relaxed(ddata->module_va + offset); 187 } 188 189 static bool sysc_opt_clks_needed(struct sysc *ddata) 190 { 191 return !!(ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_NEEDED); 192 } 193 194 static u32 sysc_read_revision(struct sysc *ddata) 195 { 196 int offset = ddata->offsets[SYSC_REVISION]; 197 198 if (offset < 0) 199 return 0; 200 201 return sysc_read(ddata, offset); 202 } 203 204 static u32 sysc_read_sysconfig(struct sysc *ddata) 205 { 206 int offset = ddata->offsets[SYSC_SYSCONFIG]; 207 208 if (offset < 0) 209 return 0; 210 211 return sysc_read(ddata, offset); 212 } 213 214 static u32 sysc_read_sysstatus(struct sysc *ddata) 215 { 216 int offset = ddata->offsets[SYSC_SYSSTATUS]; 217 218 if (offset < 0) 219 return 0; 220 221 return sysc_read(ddata, offset); 222 } 223 224 /* Poll on reset status */ 225 static int sysc_wait_softreset(struct sysc *ddata) 226 { 227 u32 sysc_mask, syss_done, rstval; 228 int syss_offset, error = 0; 229 230 syss_offset = ddata->offsets[SYSC_SYSSTATUS]; 231 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 232 233 if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED) 234 syss_done = 0; 235 else 236 syss_done = ddata->cfg.syss_mask; 237 238 if (syss_offset >= 0) { 239 error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata, 240 rstval, (rstval & ddata->cfg.syss_mask) == 241 syss_done, 100, MAX_MODULE_SOFTRESET_WAIT); 242 243 } else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) { 244 error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata, 245 rstval, !(rstval & sysc_mask), 246 100, MAX_MODULE_SOFTRESET_WAIT); 247 } 248 249 return error; 250 } 251 252 static int sysc_add_named_clock_from_child(struct sysc *ddata, 253 const char *name, 254 const char *optfck_name) 255 { 256 struct device_node *np = ddata->dev->of_node; 257 struct device_node *child; 258 struct clk_lookup *cl; 259 struct clk *clock; 260 const char *n; 261 262 if (name) 263 n = name; 264 else 265 n = optfck_name; 266 267 /* Does the clock alias already exist? */ 268 clock = of_clk_get_by_name(np, n); 269 if (!IS_ERR(clock)) { 270 clk_put(clock); 271 272 return 0; 273 } 274 275 child = of_get_next_available_child(np, NULL); 276 if (!child) 277 return -ENODEV; 278 279 clock = devm_get_clk_from_child(ddata->dev, child, name); 280 if (IS_ERR(clock)) 281 return PTR_ERR(clock); 282 283 /* 284 * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID 285 * limit for clk_get(). If cl ever needs to be freed, it should be done 286 * with clkdev_drop(). 287 */ 288 cl = kcalloc(1, sizeof(*cl), GFP_KERNEL); 289 if (!cl) 290 return -ENOMEM; 291 292 cl->con_id = n; 293 cl->dev_id = dev_name(ddata->dev); 294 cl->clk = clock; 295 clkdev_add(cl); 296 297 clk_put(clock); 298 299 return 0; 300 } 301 302 static int sysc_init_ext_opt_clock(struct sysc *ddata, const char *name) 303 { 304 const char *optfck_name; 305 int error, index; 306 307 if (ddata->nr_clocks < SYSC_OPTFCK0) 308 index = SYSC_OPTFCK0; 309 else 310 index = ddata->nr_clocks; 311 312 if (name) 313 optfck_name = name; 314 else 315 optfck_name = clock_names[index]; 316 317 error = sysc_add_named_clock_from_child(ddata, name, optfck_name); 318 if (error) 319 return error; 320 321 ddata->clock_roles[index] = optfck_name; 322 ddata->nr_clocks++; 323 324 return 0; 325 } 326 327 static int sysc_get_one_clock(struct sysc *ddata, const char *name) 328 { 329 int error, i, index = -ENODEV; 330 331 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 332 index = SYSC_FCK; 333 else if (!strncmp(clock_names[SYSC_ICK], name, 3)) 334 index = SYSC_ICK; 335 336 if (index < 0) { 337 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 338 if (!ddata->clocks[i]) { 339 index = i; 340 break; 341 } 342 } 343 } 344 345 if (index < 0) { 346 dev_err(ddata->dev, "clock %s not added\n", name); 347 return index; 348 } 349 350 ddata->clocks[index] = devm_clk_get(ddata->dev, name); 351 if (IS_ERR(ddata->clocks[index])) { 352 dev_err(ddata->dev, "clock get error for %s: %li\n", 353 name, PTR_ERR(ddata->clocks[index])); 354 355 return PTR_ERR(ddata->clocks[index]); 356 } 357 358 error = clk_prepare(ddata->clocks[index]); 359 if (error) { 360 dev_err(ddata->dev, "clock prepare error for %s: %i\n", 361 name, error); 362 363 return error; 364 } 365 366 return 0; 367 } 368 369 static int sysc_get_clocks(struct sysc *ddata) 370 { 371 struct device_node *np = ddata->dev->of_node; 372 struct property *prop; 373 const char *name; 374 int nr_fck = 0, nr_ick = 0, i, error = 0; 375 376 ddata->clock_roles = devm_kcalloc(ddata->dev, 377 SYSC_MAX_CLOCKS, 378 sizeof(*ddata->clock_roles), 379 GFP_KERNEL); 380 if (!ddata->clock_roles) 381 return -ENOMEM; 382 383 of_property_for_each_string(np, "clock-names", prop, name) { 384 if (!strncmp(clock_names[SYSC_FCK], name, 3)) 385 nr_fck++; 386 if (!strncmp(clock_names[SYSC_ICK], name, 3)) 387 nr_ick++; 388 ddata->clock_roles[ddata->nr_clocks] = name; 389 ddata->nr_clocks++; 390 } 391 392 if (ddata->nr_clocks < 1) 393 return 0; 394 395 if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) { 396 error = sysc_init_ext_opt_clock(ddata, NULL); 397 if (error) 398 return error; 399 } 400 401 if (ddata->nr_clocks > SYSC_MAX_CLOCKS) { 402 dev_err(ddata->dev, "too many clocks for %pOF\n", np); 403 404 return -EINVAL; 405 } 406 407 if (nr_fck > 1 || nr_ick > 1) { 408 dev_err(ddata->dev, "max one fck and ick for %pOF\n", np); 409 410 return -EINVAL; 411 } 412 413 /* Always add a slot for main clocks fck and ick even if unused */ 414 if (!nr_fck) 415 ddata->nr_clocks++; 416 if (!nr_ick) 417 ddata->nr_clocks++; 418 419 ddata->clocks = devm_kcalloc(ddata->dev, 420 ddata->nr_clocks, sizeof(*ddata->clocks), 421 GFP_KERNEL); 422 if (!ddata->clocks) 423 return -ENOMEM; 424 425 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 426 const char *name = ddata->clock_roles[i]; 427 428 if (!name) 429 continue; 430 431 error = sysc_get_one_clock(ddata, name); 432 if (error) 433 return error; 434 } 435 436 return 0; 437 } 438 439 static int sysc_enable_main_clocks(struct sysc *ddata) 440 { 441 struct clk *clock; 442 int i, error; 443 444 if (!ddata->clocks) 445 return 0; 446 447 for (i = 0; i < SYSC_OPTFCK0; i++) { 448 clock = ddata->clocks[i]; 449 450 /* Main clocks may not have ick */ 451 if (IS_ERR_OR_NULL(clock)) 452 continue; 453 454 error = clk_enable(clock); 455 if (error) 456 goto err_disable; 457 } 458 459 return 0; 460 461 err_disable: 462 for (i--; i >= 0; i--) { 463 clock = ddata->clocks[i]; 464 465 /* Main clocks may not have ick */ 466 if (IS_ERR_OR_NULL(clock)) 467 continue; 468 469 clk_disable(clock); 470 } 471 472 return error; 473 } 474 475 static void sysc_disable_main_clocks(struct sysc *ddata) 476 { 477 struct clk *clock; 478 int i; 479 480 if (!ddata->clocks) 481 return; 482 483 for (i = 0; i < SYSC_OPTFCK0; i++) { 484 clock = ddata->clocks[i]; 485 if (IS_ERR_OR_NULL(clock)) 486 continue; 487 488 clk_disable(clock); 489 } 490 } 491 492 static int sysc_enable_opt_clocks(struct sysc *ddata) 493 { 494 struct clk *clock; 495 int i, error; 496 497 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 498 return 0; 499 500 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 501 clock = ddata->clocks[i]; 502 503 /* Assume no holes for opt clocks */ 504 if (IS_ERR_OR_NULL(clock)) 505 return 0; 506 507 error = clk_enable(clock); 508 if (error) 509 goto err_disable; 510 } 511 512 return 0; 513 514 err_disable: 515 for (i--; i >= 0; i--) { 516 clock = ddata->clocks[i]; 517 if (IS_ERR_OR_NULL(clock)) 518 continue; 519 520 clk_disable(clock); 521 } 522 523 return error; 524 } 525 526 static void sysc_disable_opt_clocks(struct sysc *ddata) 527 { 528 struct clk *clock; 529 int i; 530 531 if (!ddata->clocks || ddata->nr_clocks < SYSC_OPTFCK0 + 1) 532 return; 533 534 for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) { 535 clock = ddata->clocks[i]; 536 537 /* Assume no holes for opt clocks */ 538 if (IS_ERR_OR_NULL(clock)) 539 return; 540 541 clk_disable(clock); 542 } 543 } 544 545 static void sysc_clkdm_deny_idle(struct sysc *ddata) 546 { 547 struct ti_sysc_platform_data *pdata; 548 549 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 550 return; 551 552 pdata = dev_get_platdata(ddata->dev); 553 if (pdata && pdata->clkdm_deny_idle) 554 pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie); 555 } 556 557 static void sysc_clkdm_allow_idle(struct sysc *ddata) 558 { 559 struct ti_sysc_platform_data *pdata; 560 561 if (ddata->legacy_mode || (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO)) 562 return; 563 564 pdata = dev_get_platdata(ddata->dev); 565 if (pdata && pdata->clkdm_allow_idle) 566 pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie); 567 } 568 569 /** 570 * sysc_init_resets - init rstctrl reset line if configured 571 * @ddata: device driver data 572 * 573 * See sysc_rstctrl_reset_deassert(). 574 */ 575 static int sysc_init_resets(struct sysc *ddata) 576 { 577 ddata->rsts = 578 devm_reset_control_get_optional_shared(ddata->dev, "rstctrl"); 579 580 return PTR_ERR_OR_ZERO(ddata->rsts); 581 } 582 583 /** 584 * sysc_parse_and_check_child_range - parses module IO region from ranges 585 * @ddata: device driver data 586 * 587 * In general we only need rev, syss, and sysc registers and not the whole 588 * module range. But we do want the offsets for these registers from the 589 * module base. This allows us to check them against the legacy hwmod 590 * platform data. Let's also check the ranges are configured properly. 591 */ 592 static int sysc_parse_and_check_child_range(struct sysc *ddata) 593 { 594 struct device_node *np = ddata->dev->of_node; 595 const __be32 *ranges; 596 u32 nr_addr, nr_size; 597 int len, error; 598 599 ranges = of_get_property(np, "ranges", &len); 600 if (!ranges) { 601 dev_err(ddata->dev, "missing ranges for %pOF\n", np); 602 603 return -ENOENT; 604 } 605 606 len /= sizeof(*ranges); 607 608 if (len < 3) { 609 dev_err(ddata->dev, "incomplete ranges for %pOF\n", np); 610 611 return -EINVAL; 612 } 613 614 error = of_property_read_u32(np, "#address-cells", &nr_addr); 615 if (error) 616 return -ENOENT; 617 618 error = of_property_read_u32(np, "#size-cells", &nr_size); 619 if (error) 620 return -ENOENT; 621 622 if (nr_addr != 1 || nr_size != 1) { 623 dev_err(ddata->dev, "invalid ranges for %pOF\n", np); 624 625 return -EINVAL; 626 } 627 628 ranges++; 629 ddata->module_pa = of_translate_address(np, ranges++); 630 ddata->module_size = be32_to_cpup(ranges); 631 632 return 0; 633 } 634 635 static struct device_node *stdout_path; 636 637 static void sysc_init_stdout_path(struct sysc *ddata) 638 { 639 struct device_node *np = NULL; 640 const char *uart; 641 642 if (IS_ERR(stdout_path)) 643 return; 644 645 if (stdout_path) 646 return; 647 648 np = of_find_node_by_path("/chosen"); 649 if (!np) 650 goto err; 651 652 uart = of_get_property(np, "stdout-path", NULL); 653 if (!uart) 654 goto err; 655 656 np = of_find_node_by_path(uart); 657 if (!np) 658 goto err; 659 660 stdout_path = np; 661 662 return; 663 664 err: 665 stdout_path = ERR_PTR(-ENODEV); 666 } 667 668 static void sysc_check_quirk_stdout(struct sysc *ddata, 669 struct device_node *np) 670 { 671 sysc_init_stdout_path(ddata); 672 if (np != stdout_path) 673 return; 674 675 ddata->cfg.quirks |= SYSC_QUIRK_NO_IDLE_ON_INIT | 676 SYSC_QUIRK_NO_RESET_ON_INIT; 677 } 678 679 /** 680 * sysc_check_one_child - check child configuration 681 * @ddata: device driver data 682 * @np: child device node 683 * 684 * Let's avoid messy situations where we have new interconnect target 685 * node but children have "ti,hwmods". These belong to the interconnect 686 * target node and are managed by this driver. 687 */ 688 static void sysc_check_one_child(struct sysc *ddata, 689 struct device_node *np) 690 { 691 const char *name; 692 693 name = of_get_property(np, "ti,hwmods", NULL); 694 if (name && !of_device_is_compatible(np, "ti,sysc")) 695 dev_warn(ddata->dev, "really a child ti,hwmods property?"); 696 697 sysc_check_quirk_stdout(ddata, np); 698 sysc_parse_dts_quirks(ddata, np, true); 699 } 700 701 static void sysc_check_children(struct sysc *ddata) 702 { 703 struct device_node *child; 704 705 for_each_child_of_node(ddata->dev->of_node, child) 706 sysc_check_one_child(ddata, child); 707 } 708 709 /* 710 * So far only I2C uses 16-bit read access with clockactivity with revision 711 * in two registers with stride of 4. We can detect this based on the rev 712 * register size to configure things far enough to be able to properly read 713 * the revision register. 714 */ 715 static void sysc_check_quirk_16bit(struct sysc *ddata, struct resource *res) 716 { 717 if (resource_size(res) == 8) 718 ddata->cfg.quirks |= SYSC_QUIRK_16BIT | SYSC_QUIRK_USE_CLOCKACT; 719 } 720 721 /** 722 * sysc_parse_one - parses the interconnect target module registers 723 * @ddata: device driver data 724 * @reg: register to parse 725 */ 726 static int sysc_parse_one(struct sysc *ddata, enum sysc_registers reg) 727 { 728 struct resource *res; 729 const char *name; 730 731 switch (reg) { 732 case SYSC_REVISION: 733 case SYSC_SYSCONFIG: 734 case SYSC_SYSSTATUS: 735 name = reg_names[reg]; 736 break; 737 default: 738 return -EINVAL; 739 } 740 741 res = platform_get_resource_byname(to_platform_device(ddata->dev), 742 IORESOURCE_MEM, name); 743 if (!res) { 744 ddata->offsets[reg] = -ENODEV; 745 746 return 0; 747 } 748 749 ddata->offsets[reg] = res->start - ddata->module_pa; 750 if (reg == SYSC_REVISION) 751 sysc_check_quirk_16bit(ddata, res); 752 753 return 0; 754 } 755 756 static int sysc_parse_registers(struct sysc *ddata) 757 { 758 int i, error; 759 760 for (i = 0; i < SYSC_MAX_REGS; i++) { 761 error = sysc_parse_one(ddata, i); 762 if (error) 763 return error; 764 } 765 766 return 0; 767 } 768 769 /** 770 * sysc_check_registers - check for misconfigured register overlaps 771 * @ddata: device driver data 772 */ 773 static int sysc_check_registers(struct sysc *ddata) 774 { 775 int i, j, nr_regs = 0, nr_matches = 0; 776 777 for (i = 0; i < SYSC_MAX_REGS; i++) { 778 if (ddata->offsets[i] < 0) 779 continue; 780 781 if (ddata->offsets[i] > (ddata->module_size - 4)) { 782 dev_err(ddata->dev, "register outside module range"); 783 784 return -EINVAL; 785 } 786 787 for (j = 0; j < SYSC_MAX_REGS; j++) { 788 if (ddata->offsets[j] < 0) 789 continue; 790 791 if (ddata->offsets[i] == ddata->offsets[j]) 792 nr_matches++; 793 } 794 nr_regs++; 795 } 796 797 if (nr_matches > nr_regs) { 798 dev_err(ddata->dev, "overlapping registers: (%i/%i)", 799 nr_regs, nr_matches); 800 801 return -EINVAL; 802 } 803 804 return 0; 805 } 806 807 /** 808 * syc_ioremap - ioremap register space for the interconnect target module 809 * @ddata: device driver data 810 * 811 * Note that the interconnect target module registers can be anywhere 812 * within the interconnect target module range. For example, SGX has 813 * them at offset 0x1fc00 in the 32MB module address space. And cpsw 814 * has them at offset 0x1200 in the CPSW_WR child. Usually the 815 * the interconnect target module registers are at the beginning of 816 * the module range though. 817 */ 818 static int sysc_ioremap(struct sysc *ddata) 819 { 820 int size; 821 822 if (ddata->offsets[SYSC_REVISION] < 0 && 823 ddata->offsets[SYSC_SYSCONFIG] < 0 && 824 ddata->offsets[SYSC_SYSSTATUS] < 0) { 825 size = ddata->module_size; 826 } else { 827 size = max3(ddata->offsets[SYSC_REVISION], 828 ddata->offsets[SYSC_SYSCONFIG], 829 ddata->offsets[SYSC_SYSSTATUS]); 830 831 if (size < SZ_1K) 832 size = SZ_1K; 833 834 if ((size + sizeof(u32)) > ddata->module_size) 835 size = ddata->module_size; 836 } 837 838 ddata->module_va = devm_ioremap(ddata->dev, 839 ddata->module_pa, 840 size + sizeof(u32)); 841 if (!ddata->module_va) 842 return -EIO; 843 844 return 0; 845 } 846 847 /** 848 * sysc_map_and_check_registers - ioremap and check device registers 849 * @ddata: device driver data 850 */ 851 static int sysc_map_and_check_registers(struct sysc *ddata) 852 { 853 int error; 854 855 error = sysc_parse_and_check_child_range(ddata); 856 if (error) 857 return error; 858 859 sysc_check_children(ddata); 860 861 error = sysc_parse_registers(ddata); 862 if (error) 863 return error; 864 865 error = sysc_ioremap(ddata); 866 if (error) 867 return error; 868 869 error = sysc_check_registers(ddata); 870 if (error) 871 return error; 872 873 return 0; 874 } 875 876 /** 877 * sysc_show_rev - read and show interconnect target module revision 878 * @bufp: buffer to print the information to 879 * @ddata: device driver data 880 */ 881 static int sysc_show_rev(char *bufp, struct sysc *ddata) 882 { 883 int len; 884 885 if (ddata->offsets[SYSC_REVISION] < 0) 886 return sprintf(bufp, ":NA"); 887 888 len = sprintf(bufp, ":%08x", ddata->revision); 889 890 return len; 891 } 892 893 static int sysc_show_reg(struct sysc *ddata, 894 char *bufp, enum sysc_registers reg) 895 { 896 if (ddata->offsets[reg] < 0) 897 return sprintf(bufp, ":NA"); 898 899 return sprintf(bufp, ":%x", ddata->offsets[reg]); 900 } 901 902 static int sysc_show_name(char *bufp, struct sysc *ddata) 903 { 904 if (!ddata->name) 905 return 0; 906 907 return sprintf(bufp, ":%s", ddata->name); 908 } 909 910 /** 911 * sysc_show_registers - show information about interconnect target module 912 * @ddata: device driver data 913 */ 914 static void sysc_show_registers(struct sysc *ddata) 915 { 916 char buf[128]; 917 char *bufp = buf; 918 int i; 919 920 for (i = 0; i < SYSC_MAX_REGS; i++) 921 bufp += sysc_show_reg(ddata, bufp, i); 922 923 bufp += sysc_show_rev(bufp, ddata); 924 bufp += sysc_show_name(bufp, ddata); 925 926 dev_dbg(ddata->dev, "%llx:%x%s\n", 927 ddata->module_pa, ddata->module_size, 928 buf); 929 } 930 931 /** 932 * sysc_write_sysconfig - handle sysconfig quirks for register write 933 * @ddata: device driver data 934 * @value: register value 935 */ 936 static void sysc_write_sysconfig(struct sysc *ddata, u32 value) 937 { 938 if (ddata->module_unlock_quirk) 939 ddata->module_unlock_quirk(ddata); 940 941 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value); 942 943 if (ddata->module_lock_quirk) 944 ddata->module_lock_quirk(ddata); 945 } 946 947 #define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1) 948 #define SYSC_CLOCACT_ICK 2 949 950 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 951 static int sysc_enable_module(struct device *dev) 952 { 953 struct sysc *ddata; 954 const struct sysc_regbits *regbits; 955 u32 reg, idlemodes, best_mode; 956 int error; 957 958 ddata = dev_get_drvdata(dev); 959 960 /* 961 * Some modules like DSS reset automatically on idle. Enable optional 962 * reset clocks and wait for OCP softreset to complete. 963 */ 964 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) { 965 error = sysc_enable_opt_clocks(ddata); 966 if (error) { 967 dev_err(ddata->dev, 968 "Optional clocks failed for enable: %i\n", 969 error); 970 return error; 971 } 972 } 973 error = sysc_wait_softreset(ddata); 974 if (error) 975 dev_warn(ddata->dev, "OCP softreset timed out\n"); 976 if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) 977 sysc_disable_opt_clocks(ddata); 978 979 /* 980 * Some subsystem private interconnects, like DSS top level module, 981 * need only the automatic OCP softreset handling with no sysconfig 982 * register bits to configure. 983 */ 984 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 985 return 0; 986 987 regbits = ddata->cap->regbits; 988 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 989 990 /* 991 * Set CLOCKACTIVITY, we only use it for ick. And we only configure it 992 * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware 993 * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag. 994 */ 995 if (regbits->clkact_shift >= 0 && 996 (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT)) 997 reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift; 998 999 /* Set SIDLE mode */ 1000 idlemodes = ddata->cfg.sidlemodes; 1001 if (!idlemodes || regbits->sidle_shift < 0) 1002 goto set_midle; 1003 1004 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE | 1005 SYSC_QUIRK_SWSUP_SIDLE_ACT)) { 1006 best_mode = SYSC_IDLE_NO; 1007 } else { 1008 best_mode = fls(ddata->cfg.sidlemodes) - 1; 1009 if (best_mode > SYSC_IDLE_MASK) { 1010 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1011 return -EINVAL; 1012 } 1013 1014 /* Set WAKEUP */ 1015 if (regbits->enwkup_shift >= 0 && 1016 ddata->cfg.sysc_val & BIT(regbits->enwkup_shift)) 1017 reg |= BIT(regbits->enwkup_shift); 1018 } 1019 1020 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1021 reg |= best_mode << regbits->sidle_shift; 1022 sysc_write_sysconfig(ddata, reg); 1023 1024 set_midle: 1025 /* Set MIDLE mode */ 1026 idlemodes = ddata->cfg.midlemodes; 1027 if (!idlemodes || regbits->midle_shift < 0) 1028 goto set_autoidle; 1029 1030 best_mode = fls(ddata->cfg.midlemodes) - 1; 1031 if (best_mode > SYSC_IDLE_MASK) { 1032 dev_err(dev, "%s: invalid midlemode\n", __func__); 1033 return -EINVAL; 1034 } 1035 1036 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY) 1037 best_mode = SYSC_IDLE_NO; 1038 1039 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1040 reg |= best_mode << regbits->midle_shift; 1041 sysc_write_sysconfig(ddata, reg); 1042 1043 set_autoidle: 1044 /* Autoidle bit must enabled separately if available */ 1045 if (regbits->autoidle_shift >= 0 && 1046 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) { 1047 reg |= 1 << regbits->autoidle_shift; 1048 sysc_write_sysconfig(ddata, reg); 1049 } 1050 1051 /* Flush posted write */ 1052 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1053 1054 if (ddata->module_enable_quirk) 1055 ddata->module_enable_quirk(ddata); 1056 1057 return 0; 1058 } 1059 1060 static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode) 1061 { 1062 if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP)) 1063 *best_mode = SYSC_IDLE_SMART_WKUP; 1064 else if (idlemodes & BIT(SYSC_IDLE_SMART)) 1065 *best_mode = SYSC_IDLE_SMART; 1066 else if (idlemodes & BIT(SYSC_IDLE_FORCE)) 1067 *best_mode = SYSC_IDLE_FORCE; 1068 else 1069 return -EINVAL; 1070 1071 return 0; 1072 } 1073 1074 /* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */ 1075 static int sysc_disable_module(struct device *dev) 1076 { 1077 struct sysc *ddata; 1078 const struct sysc_regbits *regbits; 1079 u32 reg, idlemodes, best_mode; 1080 int ret; 1081 1082 ddata = dev_get_drvdata(dev); 1083 if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV) 1084 return 0; 1085 1086 if (ddata->module_disable_quirk) 1087 ddata->module_disable_quirk(ddata); 1088 1089 regbits = ddata->cap->regbits; 1090 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1091 1092 /* Set MIDLE mode */ 1093 idlemodes = ddata->cfg.midlemodes; 1094 if (!idlemodes || regbits->midle_shift < 0) 1095 goto set_sidle; 1096 1097 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1098 if (ret) { 1099 dev_err(dev, "%s: invalid midlemode\n", __func__); 1100 return ret; 1101 } 1102 1103 if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) || 1104 ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY)) 1105 best_mode = SYSC_IDLE_FORCE; 1106 1107 reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift); 1108 reg |= best_mode << regbits->midle_shift; 1109 sysc_write_sysconfig(ddata, reg); 1110 1111 set_sidle: 1112 /* Set SIDLE mode */ 1113 idlemodes = ddata->cfg.sidlemodes; 1114 if (!idlemodes || regbits->sidle_shift < 0) 1115 return 0; 1116 1117 if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) { 1118 best_mode = SYSC_IDLE_FORCE; 1119 } else { 1120 ret = sysc_best_idle_mode(idlemodes, &best_mode); 1121 if (ret) { 1122 dev_err(dev, "%s: invalid sidlemode\n", __func__); 1123 return ret; 1124 } 1125 } 1126 1127 reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift); 1128 reg |= best_mode << regbits->sidle_shift; 1129 if (regbits->autoidle_shift >= 0 && 1130 ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) 1131 reg |= 1 << regbits->autoidle_shift; 1132 sysc_write_sysconfig(ddata, reg); 1133 1134 /* Flush posted write */ 1135 sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1136 1137 return 0; 1138 } 1139 1140 static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev, 1141 struct sysc *ddata) 1142 { 1143 struct ti_sysc_platform_data *pdata; 1144 int error; 1145 1146 pdata = dev_get_platdata(ddata->dev); 1147 if (!pdata) 1148 return 0; 1149 1150 if (!pdata->idle_module) 1151 return -ENODEV; 1152 1153 error = pdata->idle_module(dev, &ddata->cookie); 1154 if (error) 1155 dev_err(dev, "%s: could not idle: %i\n", 1156 __func__, error); 1157 1158 reset_control_assert(ddata->rsts); 1159 1160 return 0; 1161 } 1162 1163 static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev, 1164 struct sysc *ddata) 1165 { 1166 struct ti_sysc_platform_data *pdata; 1167 int error; 1168 1169 pdata = dev_get_platdata(ddata->dev); 1170 if (!pdata) 1171 return 0; 1172 1173 if (!pdata->enable_module) 1174 return -ENODEV; 1175 1176 error = pdata->enable_module(dev, &ddata->cookie); 1177 if (error) 1178 dev_err(dev, "%s: could not enable: %i\n", 1179 __func__, error); 1180 1181 reset_control_deassert(ddata->rsts); 1182 1183 return 0; 1184 } 1185 1186 static int __maybe_unused sysc_runtime_suspend(struct device *dev) 1187 { 1188 struct sysc *ddata; 1189 int error = 0; 1190 1191 ddata = dev_get_drvdata(dev); 1192 1193 if (!ddata->enabled) 1194 return 0; 1195 1196 sysc_clkdm_deny_idle(ddata); 1197 1198 if (ddata->legacy_mode) { 1199 error = sysc_runtime_suspend_legacy(dev, ddata); 1200 if (error) 1201 goto err_allow_idle; 1202 } else { 1203 error = sysc_disable_module(dev); 1204 if (error) 1205 goto err_allow_idle; 1206 } 1207 1208 sysc_disable_main_clocks(ddata); 1209 1210 if (sysc_opt_clks_needed(ddata)) 1211 sysc_disable_opt_clocks(ddata); 1212 1213 ddata->enabled = false; 1214 1215 err_allow_idle: 1216 reset_control_assert(ddata->rsts); 1217 1218 sysc_clkdm_allow_idle(ddata); 1219 1220 return error; 1221 } 1222 1223 static int __maybe_unused sysc_runtime_resume(struct device *dev) 1224 { 1225 struct sysc *ddata; 1226 int error = 0; 1227 1228 ddata = dev_get_drvdata(dev); 1229 1230 if (ddata->enabled) 1231 return 0; 1232 1233 1234 sysc_clkdm_deny_idle(ddata); 1235 1236 if (sysc_opt_clks_needed(ddata)) { 1237 error = sysc_enable_opt_clocks(ddata); 1238 if (error) 1239 goto err_allow_idle; 1240 } 1241 1242 error = sysc_enable_main_clocks(ddata); 1243 if (error) 1244 goto err_opt_clocks; 1245 1246 reset_control_deassert(ddata->rsts); 1247 1248 if (ddata->legacy_mode) { 1249 error = sysc_runtime_resume_legacy(dev, ddata); 1250 if (error) 1251 goto err_main_clocks; 1252 } else { 1253 error = sysc_enable_module(dev); 1254 if (error) 1255 goto err_main_clocks; 1256 } 1257 1258 ddata->enabled = true; 1259 1260 sysc_clkdm_allow_idle(ddata); 1261 1262 return 0; 1263 1264 err_main_clocks: 1265 sysc_disable_main_clocks(ddata); 1266 err_opt_clocks: 1267 if (sysc_opt_clks_needed(ddata)) 1268 sysc_disable_opt_clocks(ddata); 1269 err_allow_idle: 1270 sysc_clkdm_allow_idle(ddata); 1271 1272 return error; 1273 } 1274 1275 static int __maybe_unused sysc_noirq_suspend(struct device *dev) 1276 { 1277 struct sysc *ddata; 1278 1279 ddata = dev_get_drvdata(dev); 1280 1281 if (ddata->cfg.quirks & 1282 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1283 return 0; 1284 1285 return pm_runtime_force_suspend(dev); 1286 } 1287 1288 static int __maybe_unused sysc_noirq_resume(struct device *dev) 1289 { 1290 struct sysc *ddata; 1291 1292 ddata = dev_get_drvdata(dev); 1293 1294 if (ddata->cfg.quirks & 1295 (SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_NO_IDLE)) 1296 return 0; 1297 1298 return pm_runtime_force_resume(dev); 1299 } 1300 1301 static const struct dev_pm_ops sysc_pm_ops = { 1302 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume) 1303 SET_RUNTIME_PM_OPS(sysc_runtime_suspend, 1304 sysc_runtime_resume, 1305 NULL) 1306 }; 1307 1308 /* Module revision register based quirks */ 1309 struct sysc_revision_quirk { 1310 const char *name; 1311 u32 base; 1312 int rev_offset; 1313 int sysc_offset; 1314 int syss_offset; 1315 u32 revision; 1316 u32 revision_mask; 1317 u32 quirks; 1318 }; 1319 1320 #define SYSC_QUIRK(optname, optbase, optrev, optsysc, optsyss, \ 1321 optrev_val, optrevmask, optquirkmask) \ 1322 { \ 1323 .name = (optname), \ 1324 .base = (optbase), \ 1325 .rev_offset = (optrev), \ 1326 .sysc_offset = (optsysc), \ 1327 .syss_offset = (optsyss), \ 1328 .revision = (optrev_val), \ 1329 .revision_mask = (optrevmask), \ 1330 .quirks = (optquirkmask), \ 1331 } 1332 1333 static const struct sysc_revision_quirk sysc_revision_quirks[] = { 1334 /* These drivers need to be fixed to not use pm_runtime_irq_safe() */ 1335 SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff, 1336 SYSC_QUIRK_LEGACY_IDLE | SYSC_QUIRK_OPT_CLKS_IN_RESET), 1337 SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff, 1338 SYSC_QUIRK_LEGACY_IDLE), 1339 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff, 1340 SYSC_QUIRK_LEGACY_IDLE), 1341 SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff, 1342 SYSC_QUIRK_LEGACY_IDLE), 1343 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff, 1344 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1345 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff, 1346 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), 1347 /* Uarts on omap4 and later */ 1348 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff, 1349 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), 1350 SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, 1351 SYSC_QUIRK_SWSUP_SIDLE_ACT | SYSC_QUIRK_LEGACY_IDLE), 1352 1353 /* Quirks that need to be set based on the module address */ 1354 SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, 1355 SYSC_QUIRK_EXT_OPT_CLOCK | SYSC_QUIRK_NO_RESET_ON_INIT | 1356 SYSC_QUIRK_SWSUP_SIDLE), 1357 1358 /* Quirks that need to be set based on detected module */ 1359 SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff, 1360 SYSC_MODULE_QUIRK_AESS), 1361 SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 1362 SYSC_QUIRK_CLKDM_NOAUTO), 1363 SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff, 1364 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1365 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff, 1366 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1367 SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff, 1368 SYSC_QUIRK_OPT_CLKS_IN_RESET | SYSC_MODULE_QUIRK_DSS_RESET), 1369 SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1370 SYSC_QUIRK_CLKDM_NOAUTO), 1371 SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 1372 SYSC_QUIRK_CLKDM_NOAUTO), 1373 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, 1374 SYSC_QUIRK_OPT_CLKS_NEEDED), 1375 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 1376 SYSC_MODULE_QUIRK_HDQ1W), 1377 SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff, 1378 SYSC_MODULE_QUIRK_HDQ1W), 1379 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff, 1380 SYSC_MODULE_QUIRK_I2C), 1381 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff, 1382 SYSC_MODULE_QUIRK_I2C), 1383 SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff, 1384 SYSC_MODULE_QUIRK_I2C), 1385 SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0, 1386 SYSC_MODULE_QUIRK_I2C), 1387 SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0), 1388 SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 1389 SYSC_MODULE_QUIRK_SGX), 1390 SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff, 1391 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1392 SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0, 1393 SYSC_MODULE_QUIRK_RTC_UNLOCK), 1394 SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff, 1395 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1396 SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff, 1397 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1398 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 1399 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1400 SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff, 1401 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1402 SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050, 1403 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1404 SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff, 1405 SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_SWSUP_MSTANDBY), 1406 SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1407 SYSC_MODULE_QUIRK_WDT), 1408 /* PRUSS on am3, am4 and am5 */ 1409 SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000, 1410 SYSC_MODULE_QUIRK_PRUSS), 1411 /* Watchdog on am3 and am4 */ 1412 SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0, 1413 SYSC_MODULE_QUIRK_WDT | SYSC_QUIRK_SWSUP_SIDLE), 1414 1415 #ifdef DEBUG 1416 SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0), 1417 SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0), 1418 SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0), 1419 SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1420 SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902, 1421 0xffff00f0, 0), 1422 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0), 1423 SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0), 1424 SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1425 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1426 SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0), 1427 SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0), 1428 SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1429 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0), 1430 SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1431 SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0), 1432 SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0), 1433 SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1434 SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1435 SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0), 1436 SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0), 1437 SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0), 1438 SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0), 1439 SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0), 1440 SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0), 1441 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0), 1442 SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0), 1443 SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0), 1444 SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0), 1445 SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0), 1446 SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0), 1447 SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0), 1448 SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0), 1449 SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0), 1450 SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0), 1451 SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0), 1452 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0), 1453 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0), 1454 SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0), 1455 SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1456 SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0), 1457 SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0), 1458 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0), 1459 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0), 1460 SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0), 1461 SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0), 1462 SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0), 1463 SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0), 1464 SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0), 1465 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0), 1466 SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0), 1467 SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0), 1468 SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0), 1469 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0), 1470 SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0), 1471 /* Some timers on omap4 and later */ 1472 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0), 1473 SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0), 1474 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0), 1475 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0), 1476 SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0), 1477 SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0), 1478 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0), 1479 SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0), 1480 SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0), 1481 SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0), 1482 #endif 1483 }; 1484 1485 /* 1486 * Early quirks based on module base and register offsets only that are 1487 * needed before the module revision can be read 1488 */ 1489 static void sysc_init_early_quirks(struct sysc *ddata) 1490 { 1491 const struct sysc_revision_quirk *q; 1492 int i; 1493 1494 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1495 q = &sysc_revision_quirks[i]; 1496 1497 if (!q->base) 1498 continue; 1499 1500 if (q->base != ddata->module_pa) 1501 continue; 1502 1503 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1504 continue; 1505 1506 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1507 continue; 1508 1509 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1510 continue; 1511 1512 ddata->name = q->name; 1513 ddata->cfg.quirks |= q->quirks; 1514 } 1515 } 1516 1517 /* Quirks that also consider the revision register value */ 1518 static void sysc_init_revision_quirks(struct sysc *ddata) 1519 { 1520 const struct sysc_revision_quirk *q; 1521 int i; 1522 1523 for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) { 1524 q = &sysc_revision_quirks[i]; 1525 1526 if (q->base && q->base != ddata->module_pa) 1527 continue; 1528 1529 if (q->rev_offset != ddata->offsets[SYSC_REVISION]) 1530 continue; 1531 1532 if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG]) 1533 continue; 1534 1535 if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS]) 1536 continue; 1537 1538 if (q->revision == ddata->revision || 1539 (q->revision & q->revision_mask) == 1540 (ddata->revision & q->revision_mask)) { 1541 ddata->name = q->name; 1542 ddata->cfg.quirks |= q->quirks; 1543 } 1544 } 1545 } 1546 1547 /* 1548 * DSS needs dispc outputs disabled to reset modules. Returns mask of 1549 * enabled DSS interrupts. Eventually we may be able to do this on 1550 * dispc init rather than top-level DSS init. 1551 */ 1552 static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset, 1553 bool disable) 1554 { 1555 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; 1556 const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1); 1557 int manager_count; 1558 bool framedonetv_irq = true; 1559 u32 val, irq_mask = 0; 1560 1561 switch (sysc_soc->soc) { 1562 case SOC_2420 ... SOC_3630: 1563 manager_count = 2; 1564 framedonetv_irq = false; 1565 break; 1566 case SOC_4430 ... SOC_4470: 1567 manager_count = 3; 1568 break; 1569 case SOC_5430: 1570 case SOC_DRA7: 1571 manager_count = 4; 1572 break; 1573 case SOC_AM4: 1574 manager_count = 1; 1575 framedonetv_irq = false; 1576 break; 1577 case SOC_UNKNOWN: 1578 default: 1579 return 0; 1580 }; 1581 1582 /* Remap the whole module range to be able to reset dispc outputs */ 1583 devm_iounmap(ddata->dev, ddata->module_va); 1584 ddata->module_va = devm_ioremap(ddata->dev, 1585 ddata->module_pa, 1586 ddata->module_size); 1587 if (!ddata->module_va) 1588 return -EIO; 1589 1590 /* DISP_CONTROL */ 1591 val = sysc_read(ddata, dispc_offset + 0x40); 1592 lcd_en = val & lcd_en_mask; 1593 digit_en = val & digit_en_mask; 1594 if (lcd_en) 1595 irq_mask |= BIT(0); /* FRAMEDONE */ 1596 if (digit_en) { 1597 if (framedonetv_irq) 1598 irq_mask |= BIT(24); /* FRAMEDONETV */ 1599 else 1600 irq_mask |= BIT(2) | BIT(3); /* EVSYNC bits */ 1601 } 1602 if (disable & (lcd_en | digit_en)) 1603 sysc_write(ddata, dispc_offset + 0x40, 1604 val & ~(lcd_en_mask | digit_en_mask)); 1605 1606 if (manager_count <= 2) 1607 return irq_mask; 1608 1609 /* DISPC_CONTROL2 */ 1610 val = sysc_read(ddata, dispc_offset + 0x238); 1611 lcd2_en = val & lcd_en_mask; 1612 if (lcd2_en) 1613 irq_mask |= BIT(22); /* FRAMEDONE2 */ 1614 if (disable && lcd2_en) 1615 sysc_write(ddata, dispc_offset + 0x238, 1616 val & ~lcd_en_mask); 1617 1618 if (manager_count <= 3) 1619 return irq_mask; 1620 1621 /* DISPC_CONTROL3 */ 1622 val = sysc_read(ddata, dispc_offset + 0x848); 1623 lcd3_en = val & lcd_en_mask; 1624 if (lcd3_en) 1625 irq_mask |= BIT(30); /* FRAMEDONE3 */ 1626 if (disable && lcd3_en) 1627 sysc_write(ddata, dispc_offset + 0x848, 1628 val & ~lcd_en_mask); 1629 1630 return irq_mask; 1631 } 1632 1633 /* DSS needs child outputs disabled and SDI registers cleared for reset */ 1634 static void sysc_pre_reset_quirk_dss(struct sysc *ddata) 1635 { 1636 const int dispc_offset = 0x1000; 1637 int error; 1638 u32 irq_mask, val; 1639 1640 /* Get enabled outputs */ 1641 irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false); 1642 if (!irq_mask) 1643 return; 1644 1645 /* Clear IRQSTATUS */ 1646 sysc_write(ddata, dispc_offset + 0x18, irq_mask); 1647 1648 /* Disable outputs */ 1649 val = sysc_quirk_dispc(ddata, dispc_offset, true); 1650 1651 /* Poll IRQSTATUS */ 1652 error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18, 1653 val, val != irq_mask, 100, 50); 1654 if (error) 1655 dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n", 1656 __func__, val, irq_mask); 1657 1658 if (sysc_soc->soc == SOC_3430) { 1659 /* Clear DSS_SDI_CONTROL */ 1660 sysc_write(ddata, 0x44, 0); 1661 1662 /* Clear DSS_PLL_CONTROL */ 1663 sysc_write(ddata, 0x48, 0); 1664 } 1665 1666 /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */ 1667 sysc_write(ddata, 0x40, 0); 1668 } 1669 1670 /* 1-wire needs module's internal clocks enabled for reset */ 1671 static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata) 1672 { 1673 int offset = 0x0c; /* HDQ_CTRL_STATUS */ 1674 u16 val; 1675 1676 val = sysc_read(ddata, offset); 1677 val |= BIT(5); 1678 sysc_write(ddata, offset, val); 1679 } 1680 1681 /* AESS (Audio Engine SubSystem) needs autogating set after enable */ 1682 static void sysc_module_enable_quirk_aess(struct sysc *ddata) 1683 { 1684 int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */ 1685 1686 sysc_write(ddata, offset, 1); 1687 } 1688 1689 /* I2C needs to be disabled for reset */ 1690 static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable) 1691 { 1692 int offset; 1693 u16 val; 1694 1695 /* I2C_CON, omap2/3 is different from omap4 and later */ 1696 if ((ddata->revision & 0xffffff00) == 0x001f0000) 1697 offset = 0x24; 1698 else 1699 offset = 0xa4; 1700 1701 /* I2C_EN */ 1702 val = sysc_read(ddata, offset); 1703 if (enable) 1704 val |= BIT(15); 1705 else 1706 val &= ~BIT(15); 1707 sysc_write(ddata, offset, val); 1708 } 1709 1710 static void sysc_pre_reset_quirk_i2c(struct sysc *ddata) 1711 { 1712 sysc_clk_quirk_i2c(ddata, false); 1713 } 1714 1715 static void sysc_post_reset_quirk_i2c(struct sysc *ddata) 1716 { 1717 sysc_clk_quirk_i2c(ddata, true); 1718 } 1719 1720 /* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */ 1721 static void sysc_quirk_rtc(struct sysc *ddata, bool lock) 1722 { 1723 u32 val, kick0_val = 0, kick1_val = 0; 1724 unsigned long flags; 1725 int error; 1726 1727 if (!lock) { 1728 kick0_val = 0x83e70b13; 1729 kick1_val = 0x95a4f1e0; 1730 } 1731 1732 local_irq_save(flags); 1733 /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */ 1734 error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val, 1735 !(val & BIT(0)), 100, 50); 1736 if (error) 1737 dev_warn(ddata->dev, "rtc busy timeout\n"); 1738 /* Now we have ~15 microseconds to read/write various registers */ 1739 sysc_write(ddata, 0x6c, kick0_val); 1740 sysc_write(ddata, 0x70, kick1_val); 1741 local_irq_restore(flags); 1742 } 1743 1744 static void sysc_module_unlock_quirk_rtc(struct sysc *ddata) 1745 { 1746 sysc_quirk_rtc(ddata, false); 1747 } 1748 1749 static void sysc_module_lock_quirk_rtc(struct sysc *ddata) 1750 { 1751 sysc_quirk_rtc(ddata, true); 1752 } 1753 1754 /* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */ 1755 static void sysc_module_enable_quirk_sgx(struct sysc *ddata) 1756 { 1757 int offset = 0xff08; /* OCP_DEBUG_CONFIG */ 1758 u32 val = BIT(31); /* THALIA_INT_BYPASS */ 1759 1760 sysc_write(ddata, offset, val); 1761 } 1762 1763 /* Watchdog timer needs a disable sequence after reset */ 1764 static void sysc_reset_done_quirk_wdt(struct sysc *ddata) 1765 { 1766 int wps, spr, error; 1767 u32 val; 1768 1769 wps = 0x34; 1770 spr = 0x48; 1771 1772 sysc_write(ddata, spr, 0xaaaa); 1773 error = readl_poll_timeout(ddata->module_va + wps, val, 1774 !(val & 0x10), 100, 1775 MAX_MODULE_SOFTRESET_WAIT); 1776 if (error) 1777 dev_warn(ddata->dev, "wdt disable step1 failed\n"); 1778 1779 sysc_write(ddata, spr, 0x5555); 1780 error = readl_poll_timeout(ddata->module_va + wps, val, 1781 !(val & 0x10), 100, 1782 MAX_MODULE_SOFTRESET_WAIT); 1783 if (error) 1784 dev_warn(ddata->dev, "wdt disable step2 failed\n"); 1785 } 1786 1787 /* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */ 1788 static void sysc_module_disable_quirk_pruss(struct sysc *ddata) 1789 { 1790 u32 reg; 1791 1792 reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]); 1793 reg |= SYSC_PRUSS_STANDBY_INIT; 1794 sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg); 1795 } 1796 1797 static void sysc_init_module_quirks(struct sysc *ddata) 1798 { 1799 if (ddata->legacy_mode || !ddata->name) 1800 return; 1801 1802 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) { 1803 ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w; 1804 1805 return; 1806 } 1807 1808 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { 1809 ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; 1810 ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; 1811 1812 return; 1813 } 1814 1815 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS) 1816 ddata->module_enable_quirk = sysc_module_enable_quirk_aess; 1817 1818 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET) 1819 ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss; 1820 1821 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) { 1822 ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc; 1823 ddata->module_lock_quirk = sysc_module_lock_quirk_rtc; 1824 1825 return; 1826 } 1827 1828 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX) 1829 ddata->module_enable_quirk = sysc_module_enable_quirk_sgx; 1830 1831 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) { 1832 ddata->reset_done_quirk = sysc_reset_done_quirk_wdt; 1833 ddata->module_disable_quirk = sysc_reset_done_quirk_wdt; 1834 } 1835 1836 if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS) 1837 ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; 1838 } 1839 1840 static int sysc_clockdomain_init(struct sysc *ddata) 1841 { 1842 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1843 struct clk *fck = NULL, *ick = NULL; 1844 int error; 1845 1846 if (!pdata || !pdata->init_clockdomain) 1847 return 0; 1848 1849 switch (ddata->nr_clocks) { 1850 case 2: 1851 ick = ddata->clocks[SYSC_ICK]; 1852 /* fallthrough */ 1853 case 1: 1854 fck = ddata->clocks[SYSC_FCK]; 1855 break; 1856 case 0: 1857 return 0; 1858 } 1859 1860 error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie); 1861 if (!error || error == -ENODEV) 1862 return 0; 1863 1864 return error; 1865 } 1866 1867 /* 1868 * Note that pdata->init_module() typically does a reset first. After 1869 * pdata->init_module() is done, PM runtime can be used for the interconnect 1870 * target module. 1871 */ 1872 static int sysc_legacy_init(struct sysc *ddata) 1873 { 1874 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 1875 int error; 1876 1877 if (!pdata || !pdata->init_module) 1878 return 0; 1879 1880 error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie); 1881 if (error == -EEXIST) 1882 error = 0; 1883 1884 return error; 1885 } 1886 1887 /* 1888 * Note that the caller must ensure the interconnect target module is enabled 1889 * before calling reset. Otherwise reset will not complete. 1890 */ 1891 static int sysc_reset(struct sysc *ddata) 1892 { 1893 int sysc_offset, sysc_val, error; 1894 u32 sysc_mask; 1895 1896 sysc_offset = ddata->offsets[SYSC_SYSCONFIG]; 1897 1898 if (ddata->legacy_mode || 1899 ddata->cap->regbits->srst_shift < 0 || 1900 ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) 1901 return 0; 1902 1903 sysc_mask = BIT(ddata->cap->regbits->srst_shift); 1904 1905 if (ddata->pre_reset_quirk) 1906 ddata->pre_reset_quirk(ddata); 1907 1908 if (sysc_offset >= 0) { 1909 sysc_val = sysc_read_sysconfig(ddata); 1910 sysc_val |= sysc_mask; 1911 sysc_write(ddata, sysc_offset, sysc_val); 1912 } 1913 1914 if (ddata->cfg.srst_udelay) 1915 usleep_range(ddata->cfg.srst_udelay, 1916 ddata->cfg.srst_udelay * 2); 1917 1918 if (ddata->post_reset_quirk) 1919 ddata->post_reset_quirk(ddata); 1920 1921 error = sysc_wait_softreset(ddata); 1922 if (error) 1923 dev_warn(ddata->dev, "OCP softreset timed out\n"); 1924 1925 if (ddata->reset_done_quirk) 1926 ddata->reset_done_quirk(ddata); 1927 1928 return error; 1929 } 1930 1931 /* 1932 * At this point the module is configured enough to read the revision but 1933 * module may not be completely configured yet to use PM runtime. Enable 1934 * all clocks directly during init to configure the quirks needed for PM 1935 * runtime based on the revision register. 1936 */ 1937 static int sysc_init_module(struct sysc *ddata) 1938 { 1939 int error = 0; 1940 1941 error = sysc_clockdomain_init(ddata); 1942 if (error) 1943 return error; 1944 1945 sysc_clkdm_deny_idle(ddata); 1946 1947 /* 1948 * Always enable clocks. The bootloader may or may not have enabled 1949 * the related clocks. 1950 */ 1951 error = sysc_enable_opt_clocks(ddata); 1952 if (error) 1953 return error; 1954 1955 error = sysc_enable_main_clocks(ddata); 1956 if (error) 1957 goto err_opt_clocks; 1958 1959 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) { 1960 error = reset_control_deassert(ddata->rsts); 1961 if (error) 1962 goto err_main_clocks; 1963 } 1964 1965 ddata->revision = sysc_read_revision(ddata); 1966 sysc_init_revision_quirks(ddata); 1967 sysc_init_module_quirks(ddata); 1968 1969 if (ddata->legacy_mode) { 1970 error = sysc_legacy_init(ddata); 1971 if (error) 1972 goto err_reset; 1973 } 1974 1975 if (!ddata->legacy_mode) { 1976 error = sysc_enable_module(ddata->dev); 1977 if (error) 1978 goto err_reset; 1979 } 1980 1981 error = sysc_reset(ddata); 1982 if (error) 1983 dev_err(ddata->dev, "Reset failed with %d\n", error); 1984 1985 if (error && !ddata->legacy_mode) 1986 sysc_disable_module(ddata->dev); 1987 1988 err_reset: 1989 if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 1990 reset_control_assert(ddata->rsts); 1991 1992 err_main_clocks: 1993 if (error) 1994 sysc_disable_main_clocks(ddata); 1995 err_opt_clocks: 1996 /* No re-enable of clockdomain autoidle to prevent module autoidle */ 1997 if (error) { 1998 sysc_disable_opt_clocks(ddata); 1999 sysc_clkdm_allow_idle(ddata); 2000 } 2001 2002 return error; 2003 } 2004 2005 static int sysc_init_sysc_mask(struct sysc *ddata) 2006 { 2007 struct device_node *np = ddata->dev->of_node; 2008 int error; 2009 u32 val; 2010 2011 error = of_property_read_u32(np, "ti,sysc-mask", &val); 2012 if (error) 2013 return 0; 2014 2015 ddata->cfg.sysc_val = val & ddata->cap->sysc_mask; 2016 2017 return 0; 2018 } 2019 2020 static int sysc_init_idlemode(struct sysc *ddata, u8 *idlemodes, 2021 const char *name) 2022 { 2023 struct device_node *np = ddata->dev->of_node; 2024 struct property *prop; 2025 const __be32 *p; 2026 u32 val; 2027 2028 of_property_for_each_u32(np, name, prop, p, val) { 2029 if (val >= SYSC_NR_IDLEMODES) { 2030 dev_err(ddata->dev, "invalid idlemode: %i\n", val); 2031 return -EINVAL; 2032 } 2033 *idlemodes |= (1 << val); 2034 } 2035 2036 return 0; 2037 } 2038 2039 static int sysc_init_idlemodes(struct sysc *ddata) 2040 { 2041 int error; 2042 2043 error = sysc_init_idlemode(ddata, &ddata->cfg.midlemodes, 2044 "ti,sysc-midle"); 2045 if (error) 2046 return error; 2047 2048 error = sysc_init_idlemode(ddata, &ddata->cfg.sidlemodes, 2049 "ti,sysc-sidle"); 2050 if (error) 2051 return error; 2052 2053 return 0; 2054 } 2055 2056 /* 2057 * Only some devices on omap4 and later have SYSCONFIG reset done 2058 * bit. We can detect this if there is no SYSSTATUS at all, or the 2059 * SYSTATUS bit 0 is not used. Note that some SYSSTATUS registers 2060 * have multiple bits for the child devices like OHCI and EHCI. 2061 * Depends on SYSC being parsed first. 2062 */ 2063 static int sysc_init_syss_mask(struct sysc *ddata) 2064 { 2065 struct device_node *np = ddata->dev->of_node; 2066 int error; 2067 u32 val; 2068 2069 error = of_property_read_u32(np, "ti,syss-mask", &val); 2070 if (error) { 2071 if ((ddata->cap->type == TI_SYSC_OMAP4 || 2072 ddata->cap->type == TI_SYSC_OMAP4_TIMER) && 2073 (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2074 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2075 2076 return 0; 2077 } 2078 2079 if (!(val & 1) && (ddata->cfg.sysc_val & SYSC_OMAP4_SOFTRESET)) 2080 ddata->cfg.quirks |= SYSC_QUIRK_RESET_STATUS; 2081 2082 ddata->cfg.syss_mask = val; 2083 2084 return 0; 2085 } 2086 2087 /* 2088 * Many child device drivers need to have fck and opt clocks available 2089 * to get the clock rate for device internal configuration etc. 2090 */ 2091 static int sysc_child_add_named_clock(struct sysc *ddata, 2092 struct device *child, 2093 const char *name) 2094 { 2095 struct clk *clk; 2096 struct clk_lookup *l; 2097 int error = 0; 2098 2099 if (!name) 2100 return 0; 2101 2102 clk = clk_get(child, name); 2103 if (!IS_ERR(clk)) { 2104 error = -EEXIST; 2105 goto put_clk; 2106 } 2107 2108 clk = clk_get(ddata->dev, name); 2109 if (IS_ERR(clk)) 2110 return -ENODEV; 2111 2112 l = clkdev_create(clk, name, dev_name(child)); 2113 if (!l) 2114 error = -ENOMEM; 2115 put_clk: 2116 clk_put(clk); 2117 2118 return error; 2119 } 2120 2121 static int sysc_child_add_clocks(struct sysc *ddata, 2122 struct device *child) 2123 { 2124 int i, error; 2125 2126 for (i = 0; i < ddata->nr_clocks; i++) { 2127 error = sysc_child_add_named_clock(ddata, 2128 child, 2129 ddata->clock_roles[i]); 2130 if (error && error != -EEXIST) { 2131 dev_err(ddata->dev, "could not add child clock %s: %i\n", 2132 ddata->clock_roles[i], error); 2133 2134 return error; 2135 } 2136 } 2137 2138 return 0; 2139 } 2140 2141 static struct device_type sysc_device_type = { 2142 }; 2143 2144 static struct sysc *sysc_child_to_parent(struct device *dev) 2145 { 2146 struct device *parent = dev->parent; 2147 2148 if (!parent || parent->type != &sysc_device_type) 2149 return NULL; 2150 2151 return dev_get_drvdata(parent); 2152 } 2153 2154 static int __maybe_unused sysc_child_runtime_suspend(struct device *dev) 2155 { 2156 struct sysc *ddata; 2157 int error; 2158 2159 ddata = sysc_child_to_parent(dev); 2160 2161 error = pm_generic_runtime_suspend(dev); 2162 if (error) 2163 return error; 2164 2165 if (!ddata->enabled) 2166 return 0; 2167 2168 return sysc_runtime_suspend(ddata->dev); 2169 } 2170 2171 static int __maybe_unused sysc_child_runtime_resume(struct device *dev) 2172 { 2173 struct sysc *ddata; 2174 int error; 2175 2176 ddata = sysc_child_to_parent(dev); 2177 2178 if (!ddata->enabled) { 2179 error = sysc_runtime_resume(ddata->dev); 2180 if (error < 0) 2181 dev_err(ddata->dev, 2182 "%s error: %i\n", __func__, error); 2183 } 2184 2185 return pm_generic_runtime_resume(dev); 2186 } 2187 2188 #ifdef CONFIG_PM_SLEEP 2189 static int sysc_child_suspend_noirq(struct device *dev) 2190 { 2191 struct sysc *ddata; 2192 int error; 2193 2194 ddata = sysc_child_to_parent(dev); 2195 2196 dev_dbg(ddata->dev, "%s %s\n", __func__, 2197 ddata->name ? ddata->name : ""); 2198 2199 error = pm_generic_suspend_noirq(dev); 2200 if (error) { 2201 dev_err(dev, "%s error at %i: %i\n", 2202 __func__, __LINE__, error); 2203 2204 return error; 2205 } 2206 2207 if (!pm_runtime_status_suspended(dev)) { 2208 error = pm_generic_runtime_suspend(dev); 2209 if (error) { 2210 dev_dbg(dev, "%s busy at %i: %i\n", 2211 __func__, __LINE__, error); 2212 2213 return 0; 2214 } 2215 2216 error = sysc_runtime_suspend(ddata->dev); 2217 if (error) { 2218 dev_err(dev, "%s error at %i: %i\n", 2219 __func__, __LINE__, error); 2220 2221 return error; 2222 } 2223 2224 ddata->child_needs_resume = true; 2225 } 2226 2227 return 0; 2228 } 2229 2230 static int sysc_child_resume_noirq(struct device *dev) 2231 { 2232 struct sysc *ddata; 2233 int error; 2234 2235 ddata = sysc_child_to_parent(dev); 2236 2237 dev_dbg(ddata->dev, "%s %s\n", __func__, 2238 ddata->name ? ddata->name : ""); 2239 2240 if (ddata->child_needs_resume) { 2241 ddata->child_needs_resume = false; 2242 2243 error = sysc_runtime_resume(ddata->dev); 2244 if (error) 2245 dev_err(ddata->dev, 2246 "%s runtime resume error: %i\n", 2247 __func__, error); 2248 2249 error = pm_generic_runtime_resume(dev); 2250 if (error) 2251 dev_err(ddata->dev, 2252 "%s generic runtime resume: %i\n", 2253 __func__, error); 2254 } 2255 2256 return pm_generic_resume_noirq(dev); 2257 } 2258 #endif 2259 2260 static struct dev_pm_domain sysc_child_pm_domain = { 2261 .ops = { 2262 SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend, 2263 sysc_child_runtime_resume, 2264 NULL) 2265 USE_PLATFORM_PM_SLEEP_OPS 2266 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_child_suspend_noirq, 2267 sysc_child_resume_noirq) 2268 } 2269 }; 2270 2271 /** 2272 * sysc_legacy_idle_quirk - handle children in omap_device compatible way 2273 * @ddata: device driver data 2274 * @child: child device driver 2275 * 2276 * Allow idle for child devices as done with _od_runtime_suspend(). 2277 * Otherwise many child devices will not idle because of the permanent 2278 * parent usecount set in pm_runtime_irq_safe(). 2279 * 2280 * Note that the long term solution is to just modify the child device 2281 * drivers to not set pm_runtime_irq_safe() and then this can be just 2282 * dropped. 2283 */ 2284 static void sysc_legacy_idle_quirk(struct sysc *ddata, struct device *child) 2285 { 2286 if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE) 2287 dev_pm_domain_set(child, &sysc_child_pm_domain); 2288 } 2289 2290 static int sysc_notifier_call(struct notifier_block *nb, 2291 unsigned long event, void *device) 2292 { 2293 struct device *dev = device; 2294 struct sysc *ddata; 2295 int error; 2296 2297 ddata = sysc_child_to_parent(dev); 2298 if (!ddata) 2299 return NOTIFY_DONE; 2300 2301 switch (event) { 2302 case BUS_NOTIFY_ADD_DEVICE: 2303 error = sysc_child_add_clocks(ddata, dev); 2304 if (error) 2305 return error; 2306 sysc_legacy_idle_quirk(ddata, dev); 2307 break; 2308 default: 2309 break; 2310 } 2311 2312 return NOTIFY_DONE; 2313 } 2314 2315 static struct notifier_block sysc_nb = { 2316 .notifier_call = sysc_notifier_call, 2317 }; 2318 2319 /* Device tree configured quirks */ 2320 struct sysc_dts_quirk { 2321 const char *name; 2322 u32 mask; 2323 }; 2324 2325 static const struct sysc_dts_quirk sysc_dts_quirks[] = { 2326 { .name = "ti,no-idle-on-init", 2327 .mask = SYSC_QUIRK_NO_IDLE_ON_INIT, }, 2328 { .name = "ti,no-reset-on-init", 2329 .mask = SYSC_QUIRK_NO_RESET_ON_INIT, }, 2330 { .name = "ti,no-idle", 2331 .mask = SYSC_QUIRK_NO_IDLE, }, 2332 }; 2333 2334 static void sysc_parse_dts_quirks(struct sysc *ddata, struct device_node *np, 2335 bool is_child) 2336 { 2337 const struct property *prop; 2338 int i, len; 2339 2340 for (i = 0; i < ARRAY_SIZE(sysc_dts_quirks); i++) { 2341 const char *name = sysc_dts_quirks[i].name; 2342 2343 prop = of_get_property(np, name, &len); 2344 if (!prop) 2345 continue; 2346 2347 ddata->cfg.quirks |= sysc_dts_quirks[i].mask; 2348 if (is_child) { 2349 dev_warn(ddata->dev, 2350 "dts flag should be at module level for %s\n", 2351 name); 2352 } 2353 } 2354 } 2355 2356 static int sysc_init_dts_quirks(struct sysc *ddata) 2357 { 2358 struct device_node *np = ddata->dev->of_node; 2359 int error; 2360 u32 val; 2361 2362 ddata->legacy_mode = of_get_property(np, "ti,hwmods", NULL); 2363 2364 sysc_parse_dts_quirks(ddata, np, false); 2365 error = of_property_read_u32(np, "ti,sysc-delay-us", &val); 2366 if (!error) { 2367 if (val > 255) { 2368 dev_warn(ddata->dev, "bad ti,sysc-delay-us: %i\n", 2369 val); 2370 } 2371 2372 ddata->cfg.srst_udelay = (u8)val; 2373 } 2374 2375 return 0; 2376 } 2377 2378 static void sysc_unprepare(struct sysc *ddata) 2379 { 2380 int i; 2381 2382 if (!ddata->clocks) 2383 return; 2384 2385 for (i = 0; i < SYSC_MAX_CLOCKS; i++) { 2386 if (!IS_ERR_OR_NULL(ddata->clocks[i])) 2387 clk_unprepare(ddata->clocks[i]); 2388 } 2389 } 2390 2391 /* 2392 * Common sysc register bits found on omap2, also known as type1 2393 */ 2394 static const struct sysc_regbits sysc_regbits_omap2 = { 2395 .dmadisable_shift = -ENODEV, 2396 .midle_shift = 12, 2397 .sidle_shift = 3, 2398 .clkact_shift = 8, 2399 .emufree_shift = 5, 2400 .enwkup_shift = 2, 2401 .srst_shift = 1, 2402 .autoidle_shift = 0, 2403 }; 2404 2405 static const struct sysc_capabilities sysc_omap2 = { 2406 .type = TI_SYSC_OMAP2, 2407 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2408 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2409 SYSC_OMAP2_AUTOIDLE, 2410 .regbits = &sysc_regbits_omap2, 2411 }; 2412 2413 /* All omap2 and 3 timers, and timers 1, 2 & 10 on omap 4 and 5 */ 2414 static const struct sysc_capabilities sysc_omap2_timer = { 2415 .type = TI_SYSC_OMAP2_TIMER, 2416 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY | SYSC_OMAP2_EMUFREE | 2417 SYSC_OMAP2_ENAWAKEUP | SYSC_OMAP2_SOFTRESET | 2418 SYSC_OMAP2_AUTOIDLE, 2419 .regbits = &sysc_regbits_omap2, 2420 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT, 2421 }; 2422 2423 /* 2424 * SHAM2 (SHA1/MD5) sysc found on omap3, a variant of sysc_regbits_omap2 2425 * with different sidle position 2426 */ 2427 static const struct sysc_regbits sysc_regbits_omap3_sham = { 2428 .dmadisable_shift = -ENODEV, 2429 .midle_shift = -ENODEV, 2430 .sidle_shift = 4, 2431 .clkact_shift = -ENODEV, 2432 .enwkup_shift = -ENODEV, 2433 .srst_shift = 1, 2434 .autoidle_shift = 0, 2435 .emufree_shift = -ENODEV, 2436 }; 2437 2438 static const struct sysc_capabilities sysc_omap3_sham = { 2439 .type = TI_SYSC_OMAP3_SHAM, 2440 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2441 .regbits = &sysc_regbits_omap3_sham, 2442 }; 2443 2444 /* 2445 * AES register bits found on omap3 and later, a variant of 2446 * sysc_regbits_omap2 with different sidle position 2447 */ 2448 static const struct sysc_regbits sysc_regbits_omap3_aes = { 2449 .dmadisable_shift = -ENODEV, 2450 .midle_shift = -ENODEV, 2451 .sidle_shift = 6, 2452 .clkact_shift = -ENODEV, 2453 .enwkup_shift = -ENODEV, 2454 .srst_shift = 1, 2455 .autoidle_shift = 0, 2456 .emufree_shift = -ENODEV, 2457 }; 2458 2459 static const struct sysc_capabilities sysc_omap3_aes = { 2460 .type = TI_SYSC_OMAP3_AES, 2461 .sysc_mask = SYSC_OMAP2_SOFTRESET | SYSC_OMAP2_AUTOIDLE, 2462 .regbits = &sysc_regbits_omap3_aes, 2463 }; 2464 2465 /* 2466 * Common sysc register bits found on omap4, also known as type2 2467 */ 2468 static const struct sysc_regbits sysc_regbits_omap4 = { 2469 .dmadisable_shift = 16, 2470 .midle_shift = 4, 2471 .sidle_shift = 2, 2472 .clkact_shift = -ENODEV, 2473 .enwkup_shift = -ENODEV, 2474 .emufree_shift = 1, 2475 .srst_shift = 0, 2476 .autoidle_shift = -ENODEV, 2477 }; 2478 2479 static const struct sysc_capabilities sysc_omap4 = { 2480 .type = TI_SYSC_OMAP4, 2481 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2482 SYSC_OMAP4_SOFTRESET, 2483 .regbits = &sysc_regbits_omap4, 2484 }; 2485 2486 static const struct sysc_capabilities sysc_omap4_timer = { 2487 .type = TI_SYSC_OMAP4_TIMER, 2488 .sysc_mask = SYSC_OMAP4_DMADISABLE | SYSC_OMAP4_FREEEMU | 2489 SYSC_OMAP4_SOFTRESET, 2490 .regbits = &sysc_regbits_omap4, 2491 }; 2492 2493 /* 2494 * Common sysc register bits found on omap4, also known as type3 2495 */ 2496 static const struct sysc_regbits sysc_regbits_omap4_simple = { 2497 .dmadisable_shift = -ENODEV, 2498 .midle_shift = 2, 2499 .sidle_shift = 0, 2500 .clkact_shift = -ENODEV, 2501 .enwkup_shift = -ENODEV, 2502 .srst_shift = -ENODEV, 2503 .emufree_shift = -ENODEV, 2504 .autoidle_shift = -ENODEV, 2505 }; 2506 2507 static const struct sysc_capabilities sysc_omap4_simple = { 2508 .type = TI_SYSC_OMAP4_SIMPLE, 2509 .regbits = &sysc_regbits_omap4_simple, 2510 }; 2511 2512 /* 2513 * SmartReflex sysc found on omap34xx 2514 */ 2515 static const struct sysc_regbits sysc_regbits_omap34xx_sr = { 2516 .dmadisable_shift = -ENODEV, 2517 .midle_shift = -ENODEV, 2518 .sidle_shift = -ENODEV, 2519 .clkact_shift = 20, 2520 .enwkup_shift = -ENODEV, 2521 .srst_shift = -ENODEV, 2522 .emufree_shift = -ENODEV, 2523 .autoidle_shift = -ENODEV, 2524 }; 2525 2526 static const struct sysc_capabilities sysc_34xx_sr = { 2527 .type = TI_SYSC_OMAP34XX_SR, 2528 .sysc_mask = SYSC_OMAP2_CLOCKACTIVITY, 2529 .regbits = &sysc_regbits_omap34xx_sr, 2530 .mod_quirks = SYSC_QUIRK_USE_CLOCKACT | SYSC_QUIRK_UNCACHED | 2531 SYSC_QUIRK_LEGACY_IDLE, 2532 }; 2533 2534 /* 2535 * SmartReflex sysc found on omap36xx and later 2536 */ 2537 static const struct sysc_regbits sysc_regbits_omap36xx_sr = { 2538 .dmadisable_shift = -ENODEV, 2539 .midle_shift = -ENODEV, 2540 .sidle_shift = 24, 2541 .clkact_shift = -ENODEV, 2542 .enwkup_shift = 26, 2543 .srst_shift = -ENODEV, 2544 .emufree_shift = -ENODEV, 2545 .autoidle_shift = -ENODEV, 2546 }; 2547 2548 static const struct sysc_capabilities sysc_36xx_sr = { 2549 .type = TI_SYSC_OMAP36XX_SR, 2550 .sysc_mask = SYSC_OMAP3_SR_ENAWAKEUP, 2551 .regbits = &sysc_regbits_omap36xx_sr, 2552 .mod_quirks = SYSC_QUIRK_UNCACHED | SYSC_QUIRK_LEGACY_IDLE, 2553 }; 2554 2555 static const struct sysc_capabilities sysc_omap4_sr = { 2556 .type = TI_SYSC_OMAP4_SR, 2557 .regbits = &sysc_regbits_omap36xx_sr, 2558 .mod_quirks = SYSC_QUIRK_LEGACY_IDLE, 2559 }; 2560 2561 /* 2562 * McASP register bits found on omap4 and later 2563 */ 2564 static const struct sysc_regbits sysc_regbits_omap4_mcasp = { 2565 .dmadisable_shift = -ENODEV, 2566 .midle_shift = -ENODEV, 2567 .sidle_shift = 0, 2568 .clkact_shift = -ENODEV, 2569 .enwkup_shift = -ENODEV, 2570 .srst_shift = -ENODEV, 2571 .emufree_shift = -ENODEV, 2572 .autoidle_shift = -ENODEV, 2573 }; 2574 2575 static const struct sysc_capabilities sysc_omap4_mcasp = { 2576 .type = TI_SYSC_OMAP4_MCASP, 2577 .regbits = &sysc_regbits_omap4_mcasp, 2578 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2579 }; 2580 2581 /* 2582 * McASP found on dra7 and later 2583 */ 2584 static const struct sysc_capabilities sysc_dra7_mcasp = { 2585 .type = TI_SYSC_OMAP4_SIMPLE, 2586 .regbits = &sysc_regbits_omap4_simple, 2587 .mod_quirks = SYSC_QUIRK_OPT_CLKS_NEEDED, 2588 }; 2589 2590 /* 2591 * FS USB host found on omap4 and later 2592 */ 2593 static const struct sysc_regbits sysc_regbits_omap4_usb_host_fs = { 2594 .dmadisable_shift = -ENODEV, 2595 .midle_shift = -ENODEV, 2596 .sidle_shift = 24, 2597 .clkact_shift = -ENODEV, 2598 .enwkup_shift = 26, 2599 .srst_shift = -ENODEV, 2600 .emufree_shift = -ENODEV, 2601 .autoidle_shift = -ENODEV, 2602 }; 2603 2604 static const struct sysc_capabilities sysc_omap4_usb_host_fs = { 2605 .type = TI_SYSC_OMAP4_USB_HOST_FS, 2606 .sysc_mask = SYSC_OMAP2_ENAWAKEUP, 2607 .regbits = &sysc_regbits_omap4_usb_host_fs, 2608 }; 2609 2610 static const struct sysc_regbits sysc_regbits_dra7_mcan = { 2611 .dmadisable_shift = -ENODEV, 2612 .midle_shift = -ENODEV, 2613 .sidle_shift = -ENODEV, 2614 .clkact_shift = -ENODEV, 2615 .enwkup_shift = 4, 2616 .srst_shift = 0, 2617 .emufree_shift = -ENODEV, 2618 .autoidle_shift = -ENODEV, 2619 }; 2620 2621 static const struct sysc_capabilities sysc_dra7_mcan = { 2622 .type = TI_SYSC_DRA7_MCAN, 2623 .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET, 2624 .regbits = &sysc_regbits_dra7_mcan, 2625 .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED, 2626 }; 2627 2628 /* 2629 * PRUSS found on some AM33xx, AM437x and AM57xx SoCs 2630 */ 2631 static const struct sysc_capabilities sysc_pruss = { 2632 .type = TI_SYSC_PRUSS, 2633 .sysc_mask = SYSC_PRUSS_STANDBY_INIT | SYSC_PRUSS_SUB_MWAIT, 2634 .regbits = &sysc_regbits_omap4_simple, 2635 .mod_quirks = SYSC_MODULE_QUIRK_PRUSS, 2636 }; 2637 2638 static int sysc_init_pdata(struct sysc *ddata) 2639 { 2640 struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev); 2641 struct ti_sysc_module_data *mdata; 2642 2643 if (!pdata) 2644 return 0; 2645 2646 mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL); 2647 if (!mdata) 2648 return -ENOMEM; 2649 2650 if (ddata->legacy_mode) { 2651 mdata->name = ddata->legacy_mode; 2652 mdata->module_pa = ddata->module_pa; 2653 mdata->module_size = ddata->module_size; 2654 mdata->offsets = ddata->offsets; 2655 mdata->nr_offsets = SYSC_MAX_REGS; 2656 mdata->cap = ddata->cap; 2657 mdata->cfg = &ddata->cfg; 2658 } 2659 2660 ddata->mdata = mdata; 2661 2662 return 0; 2663 } 2664 2665 static int sysc_init_match(struct sysc *ddata) 2666 { 2667 const struct sysc_capabilities *cap; 2668 2669 cap = of_device_get_match_data(ddata->dev); 2670 if (!cap) 2671 return -EINVAL; 2672 2673 ddata->cap = cap; 2674 if (ddata->cap) 2675 ddata->cfg.quirks |= ddata->cap->mod_quirks; 2676 2677 return 0; 2678 } 2679 2680 static void ti_sysc_idle(struct work_struct *work) 2681 { 2682 struct sysc *ddata; 2683 2684 ddata = container_of(work, struct sysc, idle_work.work); 2685 2686 /* 2687 * One time decrement of clock usage counts if left on from init. 2688 * Note that we disable opt clocks unconditionally in this case 2689 * as they are enabled unconditionally during init without 2690 * considering sysc_opt_clks_needed() at that point. 2691 */ 2692 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 2693 SYSC_QUIRK_NO_IDLE_ON_INIT)) { 2694 sysc_disable_main_clocks(ddata); 2695 sysc_disable_opt_clocks(ddata); 2696 sysc_clkdm_allow_idle(ddata); 2697 } 2698 2699 /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */ 2700 if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE) 2701 return; 2702 2703 /* 2704 * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT 2705 * and SYSC_QUIRK_NO_RESET_ON_INIT 2706 */ 2707 if (pm_runtime_active(ddata->dev)) 2708 pm_runtime_put_sync(ddata->dev); 2709 } 2710 2711 /* 2712 * SoC model and features detection. Only needed for SoCs that need 2713 * special handling for quirks, no need to list others. 2714 */ 2715 static const struct soc_device_attribute sysc_soc_match[] = { 2716 SOC_FLAG("OMAP242*", SOC_2420), 2717 SOC_FLAG("OMAP243*", SOC_2430), 2718 SOC_FLAG("OMAP3[45]*", SOC_3430), 2719 SOC_FLAG("OMAP3[67]*", SOC_3630), 2720 SOC_FLAG("OMAP443*", SOC_4430), 2721 SOC_FLAG("OMAP446*", SOC_4460), 2722 SOC_FLAG("OMAP447*", SOC_4470), 2723 SOC_FLAG("OMAP54*", SOC_5430), 2724 SOC_FLAG("AM433", SOC_AM3), 2725 SOC_FLAG("AM43*", SOC_AM4), 2726 SOC_FLAG("DRA7*", SOC_DRA7), 2727 2728 { /* sentinel */ }, 2729 }; 2730 2731 /* 2732 * List of SoCs variants with disabled features. By default we assume all 2733 * devices in the device tree are available so no need to list those SoCs. 2734 */ 2735 static const struct soc_device_attribute sysc_soc_feat_match[] = { 2736 /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */ 2737 SOC_FLAG("AM3505", DIS_SGX), 2738 SOC_FLAG("OMAP3525", DIS_SGX), 2739 SOC_FLAG("OMAP3515", DIS_IVA | DIS_SGX), 2740 SOC_FLAG("OMAP3503", DIS_ISP | DIS_IVA | DIS_SGX), 2741 2742 /* OMAP3630/DM3730 variants with some accelerators disabled */ 2743 SOC_FLAG("AM3703", DIS_IVA | DIS_SGX), 2744 SOC_FLAG("DM3725", DIS_SGX), 2745 SOC_FLAG("OMAP3611", DIS_ISP | DIS_IVA | DIS_SGX), 2746 SOC_FLAG("OMAP3615/AM3715", DIS_IVA), 2747 SOC_FLAG("OMAP3621", DIS_ISP), 2748 2749 { /* sentinel */ }, 2750 }; 2751 2752 static int sysc_add_disabled(unsigned long base) 2753 { 2754 struct sysc_address *disabled_module; 2755 2756 disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL); 2757 if (!disabled_module) 2758 return -ENOMEM; 2759 2760 disabled_module->base = base; 2761 2762 mutex_lock(&sysc_soc->list_lock); 2763 list_add(&disabled_module->node, &sysc_soc->disabled_modules); 2764 mutex_unlock(&sysc_soc->list_lock); 2765 2766 return 0; 2767 } 2768 2769 /* 2770 * One time init to detect the booted SoC and disable unavailable features. 2771 * Note that we initialize static data shared across all ti-sysc instances 2772 * so ddata is only used for SoC type. This can be called from module_init 2773 * once we no longer need to rely on platform data. 2774 */ 2775 static int sysc_init_soc(struct sysc *ddata) 2776 { 2777 const struct soc_device_attribute *match; 2778 struct ti_sysc_platform_data *pdata; 2779 unsigned long features = 0; 2780 2781 if (sysc_soc) 2782 return 0; 2783 2784 sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL); 2785 if (!sysc_soc) 2786 return -ENOMEM; 2787 2788 mutex_init(&sysc_soc->list_lock); 2789 INIT_LIST_HEAD(&sysc_soc->disabled_modules); 2790 sysc_soc->general_purpose = true; 2791 2792 pdata = dev_get_platdata(ddata->dev); 2793 if (pdata && pdata->soc_type_gp) 2794 sysc_soc->general_purpose = pdata->soc_type_gp(); 2795 2796 match = soc_device_match(sysc_soc_match); 2797 if (match && match->data) 2798 sysc_soc->soc = (int)match->data; 2799 2800 /* Ignore devices that are not available on HS and EMU SoCs */ 2801 if (!sysc_soc->general_purpose) { 2802 switch (sysc_soc->soc) { 2803 case SOC_3430 ... SOC_3630: 2804 sysc_add_disabled(0x48304000); /* timer12 */ 2805 break; 2806 default: 2807 break; 2808 }; 2809 } 2810 2811 match = soc_device_match(sysc_soc_feat_match); 2812 if (!match) 2813 return 0; 2814 2815 if (match->data) 2816 features = (unsigned long)match->data; 2817 2818 /* 2819 * Add disabled devices to the list based on the module base. 2820 * Note that this must be done before we attempt to access the 2821 * device and have module revision checks working. 2822 */ 2823 if (features & DIS_ISP) 2824 sysc_add_disabled(0x480bd400); 2825 if (features & DIS_IVA) 2826 sysc_add_disabled(0x5d000000); 2827 if (features & DIS_SGX) 2828 sysc_add_disabled(0x50000000); 2829 2830 return 0; 2831 } 2832 2833 static void sysc_cleanup_soc(void) 2834 { 2835 struct sysc_address *disabled_module; 2836 struct list_head *pos, *tmp; 2837 2838 if (!sysc_soc) 2839 return; 2840 2841 mutex_lock(&sysc_soc->list_lock); 2842 list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) { 2843 disabled_module = list_entry(pos, struct sysc_address, node); 2844 list_del(pos); 2845 kfree(disabled_module); 2846 } 2847 mutex_unlock(&sysc_soc->list_lock); 2848 } 2849 2850 static int sysc_check_disabled_devices(struct sysc *ddata) 2851 { 2852 struct sysc_address *disabled_module; 2853 struct list_head *pos; 2854 int error = 0; 2855 2856 mutex_lock(&sysc_soc->list_lock); 2857 list_for_each(pos, &sysc_soc->disabled_modules) { 2858 disabled_module = list_entry(pos, struct sysc_address, node); 2859 if (ddata->module_pa == disabled_module->base) { 2860 dev_dbg(ddata->dev, "module disabled for this SoC\n"); 2861 error = -ENODEV; 2862 break; 2863 } 2864 } 2865 mutex_unlock(&sysc_soc->list_lock); 2866 2867 return error; 2868 } 2869 2870 /* 2871 * Ignore timers tagged with no-reset and no-idle. These are likely in use, 2872 * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks 2873 * are needed, we could also look at the timer register configuration. 2874 */ 2875 static int sysc_check_active_timer(struct sysc *ddata) 2876 { 2877 if (ddata->cap->type != TI_SYSC_OMAP2_TIMER && 2878 ddata->cap->type != TI_SYSC_OMAP4_TIMER) 2879 return 0; 2880 2881 if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) && 2882 (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)) 2883 return -EBUSY; 2884 2885 return 0; 2886 } 2887 2888 static const struct of_device_id sysc_match_table[] = { 2889 { .compatible = "simple-bus", }, 2890 { /* sentinel */ }, 2891 }; 2892 2893 static int sysc_probe(struct platform_device *pdev) 2894 { 2895 struct ti_sysc_platform_data *pdata = dev_get_platdata(&pdev->dev); 2896 struct sysc *ddata; 2897 int error; 2898 2899 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 2900 if (!ddata) 2901 return -ENOMEM; 2902 2903 ddata->dev = &pdev->dev; 2904 platform_set_drvdata(pdev, ddata); 2905 2906 error = sysc_init_soc(ddata); 2907 if (error) 2908 return error; 2909 2910 error = sysc_init_match(ddata); 2911 if (error) 2912 return error; 2913 2914 error = sysc_init_dts_quirks(ddata); 2915 if (error) 2916 return error; 2917 2918 error = sysc_map_and_check_registers(ddata); 2919 if (error) 2920 return error; 2921 2922 error = sysc_init_sysc_mask(ddata); 2923 if (error) 2924 return error; 2925 2926 error = sysc_init_idlemodes(ddata); 2927 if (error) 2928 return error; 2929 2930 error = sysc_init_syss_mask(ddata); 2931 if (error) 2932 return error; 2933 2934 error = sysc_init_pdata(ddata); 2935 if (error) 2936 return error; 2937 2938 sysc_init_early_quirks(ddata); 2939 2940 error = sysc_check_disabled_devices(ddata); 2941 if (error) 2942 return error; 2943 2944 error = sysc_check_active_timer(ddata); 2945 if (error) 2946 return error; 2947 2948 error = sysc_get_clocks(ddata); 2949 if (error) 2950 return error; 2951 2952 error = sysc_init_resets(ddata); 2953 if (error) 2954 goto unprepare; 2955 2956 error = sysc_init_module(ddata); 2957 if (error) 2958 goto unprepare; 2959 2960 pm_runtime_enable(ddata->dev); 2961 error = pm_runtime_get_sync(ddata->dev); 2962 if (error < 0) { 2963 pm_runtime_put_noidle(ddata->dev); 2964 pm_runtime_disable(ddata->dev); 2965 goto unprepare; 2966 } 2967 2968 /* Balance use counts as PM runtime should have enabled these all */ 2969 if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) 2970 reset_control_assert(ddata->rsts); 2971 2972 if (!(ddata->cfg.quirks & 2973 (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { 2974 sysc_disable_main_clocks(ddata); 2975 sysc_disable_opt_clocks(ddata); 2976 sysc_clkdm_allow_idle(ddata); 2977 } 2978 2979 sysc_show_registers(ddata); 2980 2981 ddata->dev->type = &sysc_device_type; 2982 error = of_platform_populate(ddata->dev->of_node, sysc_match_table, 2983 pdata ? pdata->auxdata : NULL, 2984 ddata->dev); 2985 if (error) 2986 goto err; 2987 2988 INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle); 2989 2990 /* At least earlycon won't survive without deferred idle */ 2991 if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | 2992 SYSC_QUIRK_NO_IDLE_ON_INIT | 2993 SYSC_QUIRK_NO_RESET_ON_INIT)) { 2994 schedule_delayed_work(&ddata->idle_work, 3000); 2995 } else { 2996 pm_runtime_put(&pdev->dev); 2997 } 2998 2999 return 0; 3000 3001 err: 3002 pm_runtime_put_sync(&pdev->dev); 3003 pm_runtime_disable(&pdev->dev); 3004 unprepare: 3005 sysc_unprepare(ddata); 3006 3007 return error; 3008 } 3009 3010 static int sysc_remove(struct platform_device *pdev) 3011 { 3012 struct sysc *ddata = platform_get_drvdata(pdev); 3013 int error; 3014 3015 cancel_delayed_work_sync(&ddata->idle_work); 3016 3017 error = pm_runtime_get_sync(ddata->dev); 3018 if (error < 0) { 3019 pm_runtime_put_noidle(ddata->dev); 3020 pm_runtime_disable(ddata->dev); 3021 goto unprepare; 3022 } 3023 3024 of_platform_depopulate(&pdev->dev); 3025 3026 pm_runtime_put_sync(&pdev->dev); 3027 pm_runtime_disable(&pdev->dev); 3028 reset_control_assert(ddata->rsts); 3029 3030 unprepare: 3031 sysc_unprepare(ddata); 3032 3033 return 0; 3034 } 3035 3036 static const struct of_device_id sysc_match[] = { 3037 { .compatible = "ti,sysc-omap2", .data = &sysc_omap2, }, 3038 { .compatible = "ti,sysc-omap2-timer", .data = &sysc_omap2_timer, }, 3039 { .compatible = "ti,sysc-omap4", .data = &sysc_omap4, }, 3040 { .compatible = "ti,sysc-omap4-timer", .data = &sysc_omap4_timer, }, 3041 { .compatible = "ti,sysc-omap4-simple", .data = &sysc_omap4_simple, }, 3042 { .compatible = "ti,sysc-omap3430-sr", .data = &sysc_34xx_sr, }, 3043 { .compatible = "ti,sysc-omap3630-sr", .data = &sysc_36xx_sr, }, 3044 { .compatible = "ti,sysc-omap4-sr", .data = &sysc_omap4_sr, }, 3045 { .compatible = "ti,sysc-omap3-sham", .data = &sysc_omap3_sham, }, 3046 { .compatible = "ti,sysc-omap-aes", .data = &sysc_omap3_aes, }, 3047 { .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, }, 3048 { .compatible = "ti,sysc-dra7-mcasp", .data = &sysc_dra7_mcasp, }, 3049 { .compatible = "ti,sysc-usb-host-fs", 3050 .data = &sysc_omap4_usb_host_fs, }, 3051 { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, }, 3052 { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, 3053 { }, 3054 }; 3055 MODULE_DEVICE_TABLE(of, sysc_match); 3056 3057 static struct platform_driver sysc_driver = { 3058 .probe = sysc_probe, 3059 .remove = sysc_remove, 3060 .driver = { 3061 .name = "ti-sysc", 3062 .of_match_table = sysc_match, 3063 .pm = &sysc_pm_ops, 3064 }, 3065 }; 3066 3067 static int __init sysc_init(void) 3068 { 3069 bus_register_notifier(&platform_bus_type, &sysc_nb); 3070 3071 return platform_driver_register(&sysc_driver); 3072 } 3073 module_init(sysc_init); 3074 3075 static void __exit sysc_exit(void) 3076 { 3077 bus_unregister_notifier(&platform_bus_type, &sysc_nb); 3078 platform_driver_unregister(&sysc_driver); 3079 sysc_cleanup_soc(); 3080 } 3081 module_exit(sysc_exit); 3082 3083 MODULE_DESCRIPTION("TI sysc interconnect target driver"); 3084 MODULE_LICENSE("GPL v2"); 3085