1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "../dmub_srv.h" 27 #include "dmub_dcn20.h" 28 #include "dmub_dcn21.h" 29 #include "dmub_fw_meta.h" 30 #include "os_types.h" 31 /* 32 * Note: the DMUB service is standalone. No additional headers should be 33 * added below or above this line unless they reside within the DMUB 34 * folder. 35 */ 36 37 /* Alignment for framebuffer memory. */ 38 #define DMUB_FB_ALIGNMENT (1024 * 1024) 39 40 /* Stack size. */ 41 #define DMUB_STACK_SIZE (128 * 1024) 42 43 /* Context size. */ 44 #define DMUB_CONTEXT_SIZE (512 * 1024) 45 46 /* Mailbox size */ 47 #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE) 48 49 /* Default state size if meta is absent. */ 50 #define DMUB_FW_STATE_SIZE (1024) 51 52 /* Default tracebuffer size if meta is absent. */ 53 #define DMUB_TRACE_BUFFER_SIZE (1024) 54 55 /* Default scratch mem size. */ 56 #define DMUB_SCRATCH_MEM_SIZE (256) 57 58 /* Number of windows in use. */ 59 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_TOTAL) 60 /* Base addresses. */ 61 62 #define DMUB_CW0_BASE (0x60000000) 63 #define DMUB_CW1_BASE (0x61000000) 64 #define DMUB_CW3_BASE (0x63000000) 65 #define DMUB_CW5_BASE (0x65000000) 66 #define DMUB_CW6_BASE (0x66000000) 67 68 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 69 { 70 return (val + factor - 1) / factor * factor; 71 } 72 73 void dmub_flush_buffer_mem(const struct dmub_fb *fb) 74 { 75 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 76 uint8_t buf[64]; 77 uint32_t pos, end; 78 79 /** 80 * Read 64-byte chunks since we don't want to store a 81 * large temporary buffer for this purpose. 82 */ 83 end = fb->size / sizeof(buf) * sizeof(buf); 84 85 for (pos = 0; pos < end; pos += sizeof(buf)) 86 dmub_memcpy(buf, base + pos, sizeof(buf)); 87 88 /* Read anything leftover into the buffer. */ 89 if (end < fb->size) 90 dmub_memcpy(buf, base + pos, fb->size - end); 91 } 92 93 static const struct dmub_fw_meta_info * 94 dmub_get_fw_meta_info(const struct dmub_srv_region_params *params) 95 { 96 const union dmub_fw_meta *meta; 97 const uint8_t *blob = NULL; 98 uint32_t blob_size = 0; 99 uint32_t meta_offset = 0; 100 101 if (params->fw_bss_data) { 102 /* Legacy metadata region. */ 103 blob = params->fw_bss_data; 104 blob_size = params->bss_data_size; 105 meta_offset = DMUB_FW_META_OFFSET; 106 } else if (params->fw_inst_const) { 107 /* Combined metadata region. */ 108 blob = params->fw_inst_const; 109 blob_size = params->inst_const_size; 110 meta_offset = 0; 111 } 112 113 if (!blob || !blob_size) 114 return NULL; 115 116 if (blob_size < sizeof(union dmub_fw_meta) + meta_offset) 117 return NULL; 118 119 meta = (const union dmub_fw_meta *)(blob + blob_size - meta_offset - 120 sizeof(union dmub_fw_meta)); 121 122 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 123 return NULL; 124 125 return &meta->info; 126 } 127 128 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 129 { 130 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 131 132 switch (asic) { 133 case DMUB_ASIC_DCN20: 134 case DMUB_ASIC_DCN21: 135 dmub->regs = &dmub_srv_dcn20_regs; 136 137 funcs->reset = dmub_dcn20_reset; 138 funcs->reset_release = dmub_dcn20_reset_release; 139 funcs->backdoor_load = dmub_dcn20_backdoor_load; 140 funcs->setup_windows = dmub_dcn20_setup_windows; 141 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 142 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 143 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 144 funcs->is_supported = dmub_dcn20_is_supported; 145 funcs->is_hw_init = dmub_dcn20_is_hw_init; 146 funcs->set_gpint = dmub_dcn20_set_gpint; 147 funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked; 148 funcs->get_gpint_response = dmub_dcn20_get_gpint_response; 149 150 if (asic == DMUB_ASIC_DCN21) { 151 dmub->regs = &dmub_srv_dcn21_regs; 152 153 funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done; 154 funcs->is_phy_init = dmub_dcn21_is_phy_init; 155 } 156 break; 157 158 default: 159 return false; 160 } 161 162 return true; 163 } 164 165 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 166 const struct dmub_srv_create_params *params) 167 { 168 enum dmub_status status = DMUB_STATUS_OK; 169 170 dmub_memset(dmub, 0, sizeof(*dmub)); 171 172 dmub->funcs = params->funcs; 173 dmub->user_ctx = params->user_ctx; 174 dmub->asic = params->asic; 175 dmub->is_virtual = params->is_virtual; 176 177 /* Setup asic dependent hardware funcs. */ 178 if (!dmub_srv_hw_setup(dmub, params->asic)) { 179 status = DMUB_STATUS_INVALID; 180 goto cleanup; 181 } 182 183 /* Override (some) hardware funcs based on user params. */ 184 if (params->hw_funcs) { 185 if (params->hw_funcs->get_inbox1_rptr) 186 dmub->hw_funcs.get_inbox1_rptr = 187 params->hw_funcs->get_inbox1_rptr; 188 189 if (params->hw_funcs->set_inbox1_wptr) 190 dmub->hw_funcs.set_inbox1_wptr = 191 params->hw_funcs->set_inbox1_wptr; 192 193 if (params->hw_funcs->is_supported) 194 dmub->hw_funcs.is_supported = 195 params->hw_funcs->is_supported; 196 } 197 198 /* Sanity checks for required hw func pointers. */ 199 if (!dmub->hw_funcs.get_inbox1_rptr || 200 !dmub->hw_funcs.set_inbox1_wptr) { 201 status = DMUB_STATUS_INVALID; 202 goto cleanup; 203 } 204 205 cleanup: 206 if (status == DMUB_STATUS_OK) 207 dmub->sw_init = true; 208 else 209 dmub_srv_destroy(dmub); 210 211 return status; 212 } 213 214 void dmub_srv_destroy(struct dmub_srv *dmub) 215 { 216 dmub_memset(dmub, 0, sizeof(*dmub)); 217 } 218 219 enum dmub_status 220 dmub_srv_calc_region_info(struct dmub_srv *dmub, 221 const struct dmub_srv_region_params *params, 222 struct dmub_srv_region_info *out) 223 { 224 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 225 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 226 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 227 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 228 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 229 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 230 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 231 struct dmub_region *scratch_mem = &out->regions[DMUB_WINDOW_7_SCRATCH_MEM]; 232 const struct dmub_fw_meta_info *fw_info; 233 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 234 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 235 uint32_t scratch_mem_size = DMUB_SCRATCH_MEM_SIZE; 236 237 if (!dmub->sw_init) 238 return DMUB_STATUS_INVALID; 239 240 memset(out, 0, sizeof(*out)); 241 242 out->num_regions = DMUB_NUM_WINDOWS; 243 244 inst->base = 0x0; 245 inst->top = inst->base + params->inst_const_size; 246 247 data->base = dmub_align(inst->top, 256); 248 data->top = data->base + params->bss_data_size; 249 250 /* 251 * All cache windows below should be aligned to the size 252 * of the DMCUB cache line, 64 bytes. 253 */ 254 255 stack->base = dmub_align(data->top, 256); 256 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 257 258 bios->base = dmub_align(stack->top, 256); 259 bios->top = bios->base + params->vbios_size; 260 261 mail->base = dmub_align(bios->top, 256); 262 mail->top = mail->base + DMUB_MAILBOX_SIZE; 263 264 fw_info = dmub_get_fw_meta_info(params); 265 266 if (fw_info) { 267 fw_state_size = fw_info->fw_region_size; 268 trace_buffer_size = fw_info->trace_buffer_size; 269 } 270 271 trace_buff->base = dmub_align(mail->top, 256); 272 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 273 274 fw_state->base = dmub_align(trace_buff->top, 256); 275 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 276 277 scratch_mem->base = dmub_align(fw_state->top, 256); 278 scratch_mem->top = scratch_mem->base + dmub_align(scratch_mem_size, 64); 279 280 out->fb_size = dmub_align(scratch_mem->top, 4096); 281 282 return DMUB_STATUS_OK; 283 } 284 285 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 286 const struct dmub_srv_fb_params *params, 287 struct dmub_srv_fb_info *out) 288 { 289 uint8_t *cpu_base; 290 uint64_t gpu_base; 291 uint32_t i; 292 293 if (!dmub->sw_init) 294 return DMUB_STATUS_INVALID; 295 296 memset(out, 0, sizeof(*out)); 297 298 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 299 return DMUB_STATUS_INVALID; 300 301 cpu_base = (uint8_t *)params->cpu_addr; 302 gpu_base = params->gpu_addr; 303 304 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 305 const struct dmub_region *reg = 306 ¶ms->region_info->regions[i]; 307 308 out->fb[i].cpu_addr = cpu_base + reg->base; 309 out->fb[i].gpu_addr = gpu_base + reg->base; 310 out->fb[i].size = reg->top - reg->base; 311 } 312 313 out->num_fb = DMUB_NUM_WINDOWS; 314 315 return DMUB_STATUS_OK; 316 } 317 318 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 319 bool *is_supported) 320 { 321 *is_supported = false; 322 323 if (!dmub->sw_init) 324 return DMUB_STATUS_INVALID; 325 326 if (dmub->hw_funcs.is_supported) 327 *is_supported = dmub->hw_funcs.is_supported(dmub); 328 329 return DMUB_STATUS_OK; 330 } 331 332 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 333 { 334 *is_hw_init = false; 335 336 if (!dmub->sw_init) 337 return DMUB_STATUS_INVALID; 338 339 if (!dmub->hw_init) 340 return DMUB_STATUS_OK; 341 342 if (dmub->hw_funcs.is_hw_init) 343 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 344 345 return DMUB_STATUS_OK; 346 } 347 348 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 349 const struct dmub_srv_hw_params *params) 350 { 351 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 352 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 353 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 354 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 355 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 356 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 357 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 358 struct dmub_fb *scratch_mem_fb = params->fb[DMUB_WINDOW_7_SCRATCH_MEM]; 359 360 struct dmub_rb_init_params rb_params; 361 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 362 struct dmub_region inbox1; 363 364 if (!dmub->sw_init) 365 return DMUB_STATUS_INVALID; 366 367 dmub->fb_base = params->fb_base; 368 dmub->fb_offset = params->fb_offset; 369 dmub->psp_version = params->psp_version; 370 371 if (inst_fb && data_fb) { 372 cw0.offset.quad_part = inst_fb->gpu_addr; 373 cw0.region.base = DMUB_CW0_BASE; 374 cw0.region.top = cw0.region.base + inst_fb->size - 1; 375 376 cw1.offset.quad_part = stack_fb->gpu_addr; 377 cw1.region.base = DMUB_CW1_BASE; 378 cw1.region.top = cw1.region.base + stack_fb->size - 1; 379 380 /** 381 * Read back all the instruction memory so we don't hang the 382 * DMCUB when backdoor loading if the write from x86 hasn't been 383 * flushed yet. This only occurs in backdoor loading. 384 */ 385 dmub_flush_buffer_mem(inst_fb); 386 387 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) 388 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 389 } 390 391 if (dmub->hw_funcs.reset) 392 dmub->hw_funcs.reset(dmub); 393 394 if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && 395 fw_state_fb && scratch_mem_fb) { 396 cw2.offset.quad_part = data_fb->gpu_addr; 397 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 398 cw2.region.top = cw2.region.base + data_fb->size; 399 400 cw3.offset.quad_part = bios_fb->gpu_addr; 401 cw3.region.base = DMUB_CW3_BASE; 402 cw3.region.top = cw3.region.base + bios_fb->size; 403 404 cw4.offset.quad_part = mail_fb->gpu_addr; 405 cw4.region.base = cw3.region.top + 1; 406 cw4.region.top = cw4.region.base + mail_fb->size; 407 408 inbox1.base = cw4.region.base; 409 inbox1.top = cw4.region.top; 410 411 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 412 cw5.region.base = DMUB_CW5_BASE; 413 cw5.region.top = cw5.region.base + tracebuff_fb->size; 414 415 cw6.offset.quad_part = fw_state_fb->gpu_addr; 416 cw6.region.base = DMUB_CW6_BASE; 417 cw6.region.top = cw6.region.base + fw_state_fb->size; 418 419 dmub->fw_state = fw_state_fb->cpu_addr; 420 421 dmub->scratch_mem_fb = *scratch_mem_fb; 422 423 if (dmub->hw_funcs.setup_windows) 424 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, 425 &cw5, &cw6); 426 427 if (dmub->hw_funcs.setup_mailbox) 428 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 429 } 430 431 if (mail_fb) { 432 dmub_memset(&rb_params, 0, sizeof(rb_params)); 433 rb_params.ctx = dmub; 434 rb_params.base_address = mail_fb->cpu_addr; 435 rb_params.capacity = DMUB_RB_SIZE; 436 437 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 438 } 439 440 if (dmub->hw_funcs.reset_release) 441 dmub->hw_funcs.reset_release(dmub); 442 443 dmub->hw_init = true; 444 445 return DMUB_STATUS_OK; 446 } 447 448 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 449 { 450 if (!dmub->sw_init) 451 return DMUB_STATUS_INVALID; 452 453 if (dmub->hw_init == false) 454 return DMUB_STATUS_OK; 455 456 if (dmub->hw_funcs.reset) 457 dmub->hw_funcs.reset(dmub); 458 459 dmub->hw_init = false; 460 461 return DMUB_STATUS_OK; 462 } 463 464 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 465 const union dmub_rb_cmd *cmd) 466 { 467 if (!dmub->hw_init) 468 return DMUB_STATUS_INVALID; 469 470 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 471 return DMUB_STATUS_OK; 472 473 return DMUB_STATUS_QUEUE_FULL; 474 } 475 476 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 477 { 478 if (!dmub->hw_init) 479 return DMUB_STATUS_INVALID; 480 481 /** 482 * Read back all the queued commands to ensure that they've 483 * been flushed to framebuffer memory. Otherwise DMCUB might 484 * read back stale, fully invalid or partially invalid data. 485 */ 486 dmub_rb_flush_pending(&dmub->inbox1_rb); 487 488 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 489 return DMUB_STATUS_OK; 490 } 491 492 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 493 uint32_t timeout_us) 494 { 495 uint32_t i; 496 497 if (!dmub->hw_init) 498 return DMUB_STATUS_INVALID; 499 500 if (!dmub->hw_funcs.is_auto_load_done) 501 return DMUB_STATUS_OK; 502 503 for (i = 0; i <= timeout_us; i += 100) { 504 if (dmub->hw_funcs.is_auto_load_done(dmub)) 505 return DMUB_STATUS_OK; 506 507 udelay(100); 508 } 509 510 return DMUB_STATUS_TIMEOUT; 511 } 512 513 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 514 uint32_t timeout_us) 515 { 516 uint32_t i = 0; 517 518 if (!dmub->hw_init) 519 return DMUB_STATUS_INVALID; 520 521 if (!dmub->hw_funcs.is_phy_init) 522 return DMUB_STATUS_OK; 523 524 for (i = 0; i <= timeout_us; i += 10) { 525 if (dmub->hw_funcs.is_phy_init(dmub)) 526 return DMUB_STATUS_OK; 527 528 udelay(10); 529 } 530 531 return DMUB_STATUS_TIMEOUT; 532 } 533 534 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 535 uint32_t timeout_us) 536 { 537 uint32_t i; 538 539 if (!dmub->hw_init) 540 return DMUB_STATUS_INVALID; 541 542 for (i = 0; i <= timeout_us; ++i) { 543 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 544 if (dmub_rb_empty(&dmub->inbox1_rb)) 545 return DMUB_STATUS_OK; 546 547 udelay(1); 548 } 549 550 return DMUB_STATUS_TIMEOUT; 551 } 552 553 enum dmub_status 554 dmub_srv_send_gpint_command(struct dmub_srv *dmub, 555 enum dmub_gpint_command command_code, 556 uint16_t param, uint32_t timeout_us) 557 { 558 union dmub_gpint_data_register reg; 559 uint32_t i; 560 561 if (!dmub->sw_init) 562 return DMUB_STATUS_INVALID; 563 564 if (!dmub->hw_funcs.set_gpint) 565 return DMUB_STATUS_INVALID; 566 567 if (!dmub->hw_funcs.is_gpint_acked) 568 return DMUB_STATUS_INVALID; 569 570 reg.bits.status = 1; 571 reg.bits.command_code = command_code; 572 reg.bits.param = param; 573 574 dmub->hw_funcs.set_gpint(dmub, reg); 575 576 for (i = 0; i < timeout_us; ++i) { 577 if (dmub->hw_funcs.is_gpint_acked(dmub, reg)) 578 return DMUB_STATUS_OK; 579 } 580 581 return DMUB_STATUS_TIMEOUT; 582 } 583 584 enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub, 585 uint32_t *response) 586 { 587 *response = 0; 588 589 if (!dmub->sw_init) 590 return DMUB_STATUS_INVALID; 591 592 if (!dmub->hw_funcs.get_gpint_response) 593 return DMUB_STATUS_INVALID; 594 595 *response = dmub->hw_funcs.get_gpint_response(dmub); 596 597 return DMUB_STATUS_OK; 598 } 599