1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/pm_runtime.h> 8 #include <linux/soc/mediatek/mtk-cmdq.h> 9 10 #include <asm/barrier.h> 11 #include <soc/mediatek/smi.h> 12 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_plane_helper.h> 15 #include <drm/drm_probe_helper.h> 16 #include <drm/drm_vblank.h> 17 18 #include "mtk_drm_drv.h" 19 #include "mtk_drm_crtc.h" 20 #include "mtk_drm_ddp.h" 21 #include "mtk_drm_ddp_comp.h" 22 #include "mtk_drm_gem.h" 23 #include "mtk_drm_plane.h" 24 25 /** 26 * struct mtk_drm_crtc - MediaTek specific crtc structure. 27 * @base: crtc object. 28 * @enabled: records whether crtc_enable succeeded 29 * @planes: array of 4 drm_plane structures, one for each overlay plane 30 * @pending_planes: whether any plane has pending changes to be applied 31 * @config_regs: memory mapped mmsys configuration register space 32 * @mutex: handle to one of the ten disp_mutex streams 33 * @ddp_comp_nr: number of components in ddp_comp 34 * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc 35 */ 36 struct mtk_drm_crtc { 37 struct drm_crtc base; 38 bool enabled; 39 40 bool pending_needs_vblank; 41 struct drm_pending_vblank_event *event; 42 43 struct drm_plane *planes; 44 unsigned int layer_nr; 45 bool pending_planes; 46 bool pending_async_planes; 47 48 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 49 struct cmdq_client *cmdq_client; 50 u32 cmdq_event; 51 #endif 52 53 void __iomem *config_regs; 54 struct mtk_disp_mutex *mutex; 55 unsigned int ddp_comp_nr; 56 struct mtk_ddp_comp **ddp_comp; 57 58 /* lock for display hardware access */ 59 struct mutex hw_lock; 60 }; 61 62 struct mtk_crtc_state { 63 struct drm_crtc_state base; 64 65 bool pending_config; 66 unsigned int pending_width; 67 unsigned int pending_height; 68 unsigned int pending_vrefresh; 69 }; 70 71 static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) 72 { 73 return container_of(c, struct mtk_drm_crtc, base); 74 } 75 76 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s) 77 { 78 return container_of(s, struct mtk_crtc_state, base); 79 } 80 81 static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 82 { 83 struct drm_crtc *crtc = &mtk_crtc->base; 84 unsigned long flags; 85 86 spin_lock_irqsave(&crtc->dev->event_lock, flags); 87 drm_crtc_send_vblank_event(crtc, mtk_crtc->event); 88 drm_crtc_vblank_put(crtc); 89 mtk_crtc->event = NULL; 90 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 91 } 92 93 static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) 94 { 95 drm_crtc_handle_vblank(&mtk_crtc->base); 96 if (mtk_crtc->pending_needs_vblank) { 97 mtk_drm_crtc_finish_page_flip(mtk_crtc); 98 mtk_crtc->pending_needs_vblank = false; 99 } 100 } 101 102 static void mtk_drm_crtc_destroy(struct drm_crtc *crtc) 103 { 104 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 105 106 mtk_disp_mutex_put(mtk_crtc->mutex); 107 108 drm_crtc_cleanup(crtc); 109 } 110 111 static void mtk_drm_crtc_reset(struct drm_crtc *crtc) 112 { 113 struct mtk_crtc_state *state; 114 115 if (crtc->state) { 116 __drm_atomic_helper_crtc_destroy_state(crtc->state); 117 118 state = to_mtk_crtc_state(crtc->state); 119 memset(state, 0, sizeof(*state)); 120 } else { 121 state = kzalloc(sizeof(*state), GFP_KERNEL); 122 if (!state) 123 return; 124 crtc->state = &state->base; 125 } 126 127 state->base.crtc = crtc; 128 } 129 130 static struct drm_crtc_state *mtk_drm_crtc_duplicate_state(struct drm_crtc *crtc) 131 { 132 struct mtk_crtc_state *state; 133 134 state = kzalloc(sizeof(*state), GFP_KERNEL); 135 if (!state) 136 return NULL; 137 138 __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); 139 140 WARN_ON(state->base.crtc != crtc); 141 state->base.crtc = crtc; 142 143 return &state->base; 144 } 145 146 static void mtk_drm_crtc_destroy_state(struct drm_crtc *crtc, 147 struct drm_crtc_state *state) 148 { 149 __drm_atomic_helper_crtc_destroy_state(state); 150 kfree(to_mtk_crtc_state(state)); 151 } 152 153 static bool mtk_drm_crtc_mode_fixup(struct drm_crtc *crtc, 154 const struct drm_display_mode *mode, 155 struct drm_display_mode *adjusted_mode) 156 { 157 /* Nothing to do here, but this callback is mandatory. */ 158 return true; 159 } 160 161 static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 162 { 163 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 164 165 state->pending_width = crtc->mode.hdisplay; 166 state->pending_height = crtc->mode.vdisplay; 167 state->pending_vrefresh = crtc->mode.vrefresh; 168 wmb(); /* Make sure the above parameters are set before update */ 169 state->pending_config = true; 170 } 171 172 static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 173 { 174 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 175 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 176 177 mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base); 178 179 return 0; 180 } 181 182 static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc) 183 { 184 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 185 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 186 187 mtk_ddp_comp_disable_vblank(comp); 188 } 189 190 static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc) 191 { 192 int ret; 193 int i; 194 195 DRM_DEBUG_DRIVER("%s\n", __func__); 196 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 197 ret = clk_prepare_enable(mtk_crtc->ddp_comp[i]->clk); 198 if (ret) { 199 DRM_ERROR("Failed to enable clock %d: %d\n", i, ret); 200 goto err; 201 } 202 } 203 204 return 0; 205 err: 206 while (--i >= 0) 207 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 208 return ret; 209 } 210 211 static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc) 212 { 213 int i; 214 215 DRM_DEBUG_DRIVER("%s\n", __func__); 216 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 217 clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk); 218 } 219 220 static 221 struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, 222 struct drm_plane *plane, 223 unsigned int *local_layer) 224 { 225 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 226 struct mtk_ddp_comp *comp; 227 int i, count = 0; 228 unsigned int local_index = plane - mtk_crtc->planes; 229 230 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 231 comp = mtk_crtc->ddp_comp[i]; 232 if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { 233 *local_layer = local_index - count; 234 return comp; 235 } 236 count += mtk_ddp_comp_layer_nr(comp); 237 } 238 239 WARN(1, "Failed to find component for plane %d\n", plane->index); 240 return NULL; 241 } 242 243 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 244 static void ddp_cmdq_cb(struct cmdq_cb_data data) 245 { 246 cmdq_pkt_destroy(data.data); 247 } 248 #endif 249 250 static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 251 { 252 struct drm_crtc *crtc = &mtk_crtc->base; 253 struct drm_connector *connector; 254 struct drm_encoder *encoder; 255 struct drm_connector_list_iter conn_iter; 256 unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC; 257 int ret; 258 int i; 259 260 DRM_DEBUG_DRIVER("%s\n", __func__); 261 if (WARN_ON(!crtc->state)) 262 return -EINVAL; 263 264 width = crtc->state->adjusted_mode.hdisplay; 265 height = crtc->state->adjusted_mode.vdisplay; 266 vrefresh = crtc->state->adjusted_mode.vrefresh; 267 268 drm_for_each_encoder(encoder, crtc->dev) { 269 if (encoder->crtc != crtc) 270 continue; 271 272 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 273 drm_for_each_connector_iter(connector, &conn_iter) { 274 if (connector->encoder != encoder) 275 continue; 276 if (connector->display_info.bpc != 0 && 277 bpc > connector->display_info.bpc) 278 bpc = connector->display_info.bpc; 279 } 280 drm_connector_list_iter_end(&conn_iter); 281 } 282 283 ret = pm_runtime_get_sync(crtc->dev->dev); 284 if (ret < 0) { 285 DRM_ERROR("Failed to enable power domain: %d\n", ret); 286 return ret; 287 } 288 289 ret = mtk_disp_mutex_prepare(mtk_crtc->mutex); 290 if (ret < 0) { 291 DRM_ERROR("Failed to enable mutex clock: %d\n", ret); 292 goto err_pm_runtime_put; 293 } 294 295 ret = mtk_crtc_ddp_clk_enable(mtk_crtc); 296 if (ret < 0) { 297 DRM_ERROR("Failed to enable component clocks: %d\n", ret); 298 goto err_mutex_unprepare; 299 } 300 301 DRM_DEBUG_DRIVER("mediatek_ddp_ddp_path_setup\n"); 302 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 303 mtk_ddp_add_comp_to_path(mtk_crtc->config_regs, 304 mtk_crtc->ddp_comp[i]->id, 305 mtk_crtc->ddp_comp[i + 1]->id); 306 mtk_disp_mutex_add_comp(mtk_crtc->mutex, 307 mtk_crtc->ddp_comp[i]->id); 308 } 309 mtk_disp_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 310 mtk_disp_mutex_enable(mtk_crtc->mutex); 311 312 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 313 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i]; 314 315 if (i == 1) 316 mtk_ddp_comp_bgclr_in_on(comp); 317 318 mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL); 319 mtk_ddp_comp_start(comp); 320 } 321 322 /* Initially configure all planes */ 323 for (i = 0; i < mtk_crtc->layer_nr; i++) { 324 struct drm_plane *plane = &mtk_crtc->planes[i]; 325 struct mtk_plane_state *plane_state; 326 struct mtk_ddp_comp *comp; 327 unsigned int local_layer; 328 329 plane_state = to_mtk_plane_state(plane->state); 330 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 331 if (comp) 332 mtk_ddp_comp_layer_config(comp, local_layer, 333 plane_state, NULL); 334 } 335 336 return 0; 337 338 err_mutex_unprepare: 339 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 340 err_pm_runtime_put: 341 pm_runtime_put(crtc->dev->dev); 342 return ret; 343 } 344 345 static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) 346 { 347 struct drm_device *drm = mtk_crtc->base.dev; 348 struct drm_crtc *crtc = &mtk_crtc->base; 349 int i; 350 351 DRM_DEBUG_DRIVER("%s\n", __func__); 352 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 353 mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]); 354 if (i == 1) 355 mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]); 356 } 357 358 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 359 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 360 mtk_crtc->ddp_comp[i]->id); 361 mtk_disp_mutex_disable(mtk_crtc->mutex); 362 for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { 363 mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs, 364 mtk_crtc->ddp_comp[i]->id, 365 mtk_crtc->ddp_comp[i + 1]->id); 366 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, 367 mtk_crtc->ddp_comp[i]->id); 368 } 369 mtk_disp_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); 370 mtk_crtc_ddp_clk_disable(mtk_crtc); 371 mtk_disp_mutex_unprepare(mtk_crtc->mutex); 372 373 pm_runtime_put(drm->dev); 374 375 if (crtc->state->event && !crtc->state->active) { 376 spin_lock_irq(&crtc->dev->event_lock); 377 drm_crtc_send_vblank_event(crtc, crtc->state->event); 378 crtc->state->event = NULL; 379 spin_unlock_irq(&crtc->dev->event_lock); 380 } 381 } 382 383 static void mtk_crtc_ddp_config(struct drm_crtc *crtc, 384 struct cmdq_pkt *cmdq_handle) 385 { 386 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 387 struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state); 388 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 389 unsigned int i; 390 unsigned int local_layer; 391 392 /* 393 * TODO: instead of updating the registers here, we should prepare 394 * working registers in atomic_commit and let the hardware command 395 * queue update module registers on vblank. 396 */ 397 if (state->pending_config) { 398 mtk_ddp_comp_config(comp, state->pending_width, 399 state->pending_height, 400 state->pending_vrefresh, 0, 401 cmdq_handle); 402 403 state->pending_config = false; 404 } 405 406 if (mtk_crtc->pending_planes) { 407 for (i = 0; i < mtk_crtc->layer_nr; i++) { 408 struct drm_plane *plane = &mtk_crtc->planes[i]; 409 struct mtk_plane_state *plane_state; 410 411 plane_state = to_mtk_plane_state(plane->state); 412 413 if (!plane_state->pending.config) 414 continue; 415 416 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 417 &local_layer); 418 419 if (comp) 420 mtk_ddp_comp_layer_config(comp, local_layer, 421 plane_state, 422 cmdq_handle); 423 plane_state->pending.config = false; 424 } 425 mtk_crtc->pending_planes = false; 426 } 427 428 if (mtk_crtc->pending_async_planes) { 429 for (i = 0; i < mtk_crtc->layer_nr; i++) { 430 struct drm_plane *plane = &mtk_crtc->planes[i]; 431 struct mtk_plane_state *plane_state; 432 433 plane_state = to_mtk_plane_state(plane->state); 434 435 if (!plane_state->pending.async_config) 436 continue; 437 438 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, 439 &local_layer); 440 441 if (comp) 442 mtk_ddp_comp_layer_config(comp, local_layer, 443 plane_state, 444 cmdq_handle); 445 plane_state->pending.async_config = false; 446 } 447 mtk_crtc->pending_async_planes = false; 448 } 449 } 450 451 static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) 452 { 453 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 454 struct cmdq_pkt *cmdq_handle; 455 #endif 456 struct drm_crtc *crtc = &mtk_crtc->base; 457 struct mtk_drm_private *priv = crtc->dev->dev_private; 458 unsigned int pending_planes = 0, pending_async_planes = 0; 459 int i; 460 461 mutex_lock(&mtk_crtc->hw_lock); 462 for (i = 0; i < mtk_crtc->layer_nr; i++) { 463 struct drm_plane *plane = &mtk_crtc->planes[i]; 464 struct mtk_plane_state *plane_state; 465 466 plane_state = to_mtk_plane_state(plane->state); 467 if (plane_state->pending.dirty) { 468 plane_state->pending.config = true; 469 plane_state->pending.dirty = false; 470 pending_planes |= BIT(i); 471 } else if (plane_state->pending.async_dirty) { 472 plane_state->pending.async_config = true; 473 plane_state->pending.async_dirty = false; 474 pending_async_planes |= BIT(i); 475 } 476 } 477 if (pending_planes) 478 mtk_crtc->pending_planes = true; 479 if (pending_async_planes) 480 mtk_crtc->pending_async_planes = true; 481 482 if (priv->data->shadow_register) { 483 mtk_disp_mutex_acquire(mtk_crtc->mutex); 484 mtk_crtc_ddp_config(crtc, NULL); 485 mtk_disp_mutex_release(mtk_crtc->mutex); 486 } 487 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 488 if (mtk_crtc->cmdq_client) { 489 mbox_flush(mtk_crtc->cmdq_client->chan, 2000); 490 cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); 491 cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); 492 cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event); 493 mtk_crtc_ddp_config(crtc, cmdq_handle); 494 cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); 495 } 496 #endif 497 mutex_unlock(&mtk_crtc->hw_lock); 498 } 499 500 int mtk_drm_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, 501 struct mtk_plane_state *state) 502 { 503 unsigned int local_layer; 504 struct mtk_ddp_comp *comp; 505 506 comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); 507 if (comp) 508 return mtk_ddp_comp_layer_check(comp, local_layer, state); 509 return 0; 510 } 511 512 void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, 513 struct drm_plane_state *new_state) 514 { 515 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 516 const struct drm_plane_helper_funcs *plane_helper_funcs = 517 plane->helper_private; 518 519 if (!mtk_crtc->enabled) 520 return; 521 522 plane_helper_funcs->atomic_update(plane, new_state); 523 mtk_drm_crtc_hw_config(mtk_crtc); 524 } 525 526 static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 527 struct drm_crtc_state *old_state) 528 { 529 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 530 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 531 int ret; 532 533 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 534 535 ret = mtk_smi_larb_get(comp->larb_dev); 536 if (ret) { 537 DRM_ERROR("Failed to get larb: %d\n", ret); 538 return; 539 } 540 541 ret = mtk_crtc_ddp_hw_init(mtk_crtc); 542 if (ret) { 543 mtk_smi_larb_put(comp->larb_dev); 544 return; 545 } 546 547 drm_crtc_vblank_on(crtc); 548 mtk_crtc->enabled = true; 549 } 550 551 static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 552 struct drm_crtc_state *old_state) 553 { 554 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 555 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; 556 int i; 557 558 DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id); 559 if (!mtk_crtc->enabled) 560 return; 561 562 /* Set all pending plane state to disabled */ 563 for (i = 0; i < mtk_crtc->layer_nr; i++) { 564 struct drm_plane *plane = &mtk_crtc->planes[i]; 565 struct mtk_plane_state *plane_state; 566 567 plane_state = to_mtk_plane_state(plane->state); 568 plane_state->pending.enable = false; 569 plane_state->pending.config = true; 570 } 571 mtk_crtc->pending_planes = true; 572 573 mtk_drm_crtc_hw_config(mtk_crtc); 574 /* Wait for planes to be disabled */ 575 drm_crtc_wait_one_vblank(crtc); 576 577 drm_crtc_vblank_off(crtc); 578 mtk_crtc_ddp_hw_fini(mtk_crtc); 579 mtk_smi_larb_put(comp->larb_dev); 580 581 mtk_crtc->enabled = false; 582 } 583 584 static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, 585 struct drm_crtc_state *old_crtc_state) 586 { 587 struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); 588 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 589 590 if (mtk_crtc->event && state->base.event) 591 DRM_ERROR("new event while there is still a pending event\n"); 592 593 if (state->base.event) { 594 state->base.event->pipe = drm_crtc_index(crtc); 595 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 596 mtk_crtc->event = state->base.event; 597 state->base.event = NULL; 598 } 599 } 600 601 static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 602 struct drm_crtc_state *old_crtc_state) 603 { 604 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 605 int i; 606 607 if (mtk_crtc->event) 608 mtk_crtc->pending_needs_vblank = true; 609 if (crtc->state->color_mgmt_changed) 610 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 611 mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state); 612 mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); 613 } 614 mtk_drm_crtc_hw_config(mtk_crtc); 615 } 616 617 static const struct drm_crtc_funcs mtk_crtc_funcs = { 618 .set_config = drm_atomic_helper_set_config, 619 .page_flip = drm_atomic_helper_page_flip, 620 .destroy = mtk_drm_crtc_destroy, 621 .reset = mtk_drm_crtc_reset, 622 .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, 623 .atomic_destroy_state = mtk_drm_crtc_destroy_state, 624 .gamma_set = drm_atomic_helper_legacy_gamma_set, 625 .enable_vblank = mtk_drm_crtc_enable_vblank, 626 .disable_vblank = mtk_drm_crtc_disable_vblank, 627 }; 628 629 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { 630 .mode_fixup = mtk_drm_crtc_mode_fixup, 631 .mode_set_nofb = mtk_drm_crtc_mode_set_nofb, 632 .atomic_begin = mtk_drm_crtc_atomic_begin, 633 .atomic_flush = mtk_drm_crtc_atomic_flush, 634 .atomic_enable = mtk_drm_crtc_atomic_enable, 635 .atomic_disable = mtk_drm_crtc_atomic_disable, 636 }; 637 638 static int mtk_drm_crtc_init(struct drm_device *drm, 639 struct mtk_drm_crtc *mtk_crtc, 640 unsigned int pipe) 641 { 642 struct drm_plane *primary = NULL; 643 struct drm_plane *cursor = NULL; 644 int i, ret; 645 646 for (i = 0; i < mtk_crtc->layer_nr; i++) { 647 if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY) 648 primary = &mtk_crtc->planes[i]; 649 else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR) 650 cursor = &mtk_crtc->planes[i]; 651 } 652 653 ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, 654 &mtk_crtc_funcs, NULL); 655 if (ret) 656 goto err_cleanup_crtc; 657 658 drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs); 659 660 return 0; 661 662 err_cleanup_crtc: 663 drm_crtc_cleanup(&mtk_crtc->base); 664 return ret; 665 } 666 667 void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp) 668 { 669 struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); 670 struct mtk_drm_private *priv = crtc->dev->dev_private; 671 672 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 673 if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) 674 #else 675 if (!priv->data->shadow_register) 676 #endif 677 mtk_crtc_ddp_config(crtc, NULL); 678 679 mtk_drm_finish_page_flip(mtk_crtc); 680 } 681 682 static int mtk_drm_crtc_num_comp_planes(struct mtk_drm_crtc *mtk_crtc, 683 int comp_idx) 684 { 685 struct mtk_ddp_comp *comp; 686 687 if (comp_idx > 1) 688 return 0; 689 690 comp = mtk_crtc->ddp_comp[comp_idx]; 691 if (!comp->funcs) 692 return 0; 693 694 if (comp_idx == 1 && !comp->funcs->bgclr_in_on) 695 return 0; 696 697 return mtk_ddp_comp_layer_nr(comp); 698 } 699 700 static inline 701 enum drm_plane_type mtk_drm_crtc_plane_type(unsigned int plane_idx, 702 unsigned int num_planes) 703 { 704 if (plane_idx == 0) 705 return DRM_PLANE_TYPE_PRIMARY; 706 else if (plane_idx == (num_planes - 1)) 707 return DRM_PLANE_TYPE_CURSOR; 708 else 709 return DRM_PLANE_TYPE_OVERLAY; 710 711 } 712 713 static int mtk_drm_crtc_init_comp_planes(struct drm_device *drm_dev, 714 struct mtk_drm_crtc *mtk_crtc, 715 int comp_idx, int pipe) 716 { 717 int num_planes = mtk_drm_crtc_num_comp_planes(mtk_crtc, comp_idx); 718 struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx]; 719 int i, ret; 720 721 for (i = 0; i < num_planes; i++) { 722 ret = mtk_plane_init(drm_dev, 723 &mtk_crtc->planes[mtk_crtc->layer_nr], 724 BIT(pipe), 725 mtk_drm_crtc_plane_type(mtk_crtc->layer_nr, 726 num_planes), 727 mtk_ddp_comp_supported_rotations(comp)); 728 if (ret) 729 return ret; 730 731 mtk_crtc->layer_nr++; 732 } 733 return 0; 734 } 735 736 int mtk_drm_crtc_create(struct drm_device *drm_dev, 737 const enum mtk_ddp_comp_id *path, unsigned int path_len) 738 { 739 struct mtk_drm_private *priv = drm_dev->dev_private; 740 struct device *dev = drm_dev->dev; 741 struct mtk_drm_crtc *mtk_crtc; 742 unsigned int num_comp_planes = 0; 743 int pipe = priv->num_pipes; 744 int ret; 745 int i; 746 bool has_ctm = false; 747 uint gamma_lut_size = 0; 748 749 if (!path) 750 return 0; 751 752 for (i = 0; i < path_len; i++) { 753 enum mtk_ddp_comp_id comp_id = path[i]; 754 struct device_node *node; 755 756 node = priv->comp_node[comp_id]; 757 if (!node) { 758 dev_info(dev, 759 "Not creating crtc %d because component %d is disabled or missing\n", 760 pipe, comp_id); 761 return 0; 762 } 763 } 764 765 mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL); 766 if (!mtk_crtc) 767 return -ENOMEM; 768 769 mtk_crtc->config_regs = priv->config_regs; 770 mtk_crtc->ddp_comp_nr = path_len; 771 mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr, 772 sizeof(*mtk_crtc->ddp_comp), 773 GFP_KERNEL); 774 if (!mtk_crtc->ddp_comp) 775 return -ENOMEM; 776 777 mtk_crtc->mutex = mtk_disp_mutex_get(priv->mutex_dev, pipe); 778 if (IS_ERR(mtk_crtc->mutex)) { 779 ret = PTR_ERR(mtk_crtc->mutex); 780 dev_err(dev, "Failed to get mutex: %d\n", ret); 781 return ret; 782 } 783 784 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 785 enum mtk_ddp_comp_id comp_id = path[i]; 786 struct mtk_ddp_comp *comp; 787 struct device_node *node; 788 789 node = priv->comp_node[comp_id]; 790 comp = priv->ddp_comp[comp_id]; 791 if (!comp) { 792 dev_err(dev, "Component %pOF not initialized\n", node); 793 ret = -ENODEV; 794 return ret; 795 } 796 797 mtk_crtc->ddp_comp[i] = comp; 798 799 if (comp->funcs) { 800 if (comp->funcs->gamma_set) 801 gamma_lut_size = MTK_LUT_SIZE; 802 803 if (comp->funcs->ctm_set) 804 has_ctm = true; 805 } 806 } 807 808 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) 809 num_comp_planes += mtk_drm_crtc_num_comp_planes(mtk_crtc, i); 810 811 mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes, 812 sizeof(struct drm_plane), GFP_KERNEL); 813 814 for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { 815 ret = mtk_drm_crtc_init_comp_planes(drm_dev, mtk_crtc, i, 816 pipe); 817 if (ret) 818 return ret; 819 } 820 821 ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, pipe); 822 if (ret < 0) 823 return ret; 824 825 if (gamma_lut_size) 826 drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); 827 drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); 828 priv->num_pipes++; 829 mutex_init(&mtk_crtc->hw_lock); 830 831 #if IS_REACHABLE(CONFIG_MTK_CMDQ) 832 mtk_crtc->cmdq_client = 833 cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base), 834 2000); 835 if (IS_ERR(mtk_crtc->cmdq_client)) { 836 dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", 837 drm_crtc_index(&mtk_crtc->base)); 838 mtk_crtc->cmdq_client = NULL; 839 } 840 ret = of_property_read_u32_index(priv->mutex_node, 841 "mediatek,gce-events", 842 drm_crtc_index(&mtk_crtc->base), 843 &mtk_crtc->cmdq_event); 844 if (ret) 845 dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n", 846 drm_crtc_index(&mtk_crtc->base)); 847 #endif 848 return 0; 849 } 850