xref: /openbmc/linux/arch/arc/mm/tlbex.S (revision dc6a81c3) 
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * TLB Exception Handling for ARC
4 *
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 *
7 * Vineetg: April 2011 :
8 *  -MMU v1: moved out legacy code into a seperate file
9 *  -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
10 *      helps avoid a shift when preparing PD0 from PTE
11 *
12 * Vineetg: July 2009
13 *  -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
14 *   entry, so that it doesn't knock out it's I-TLB entry
15 *  -Some more fine tuning:
16 *   bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
17 *
18 * Vineetg: July 2009
19 *  -Practically rewrote the I/D TLB Miss handlers
20 *   Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
21 *   Hence Leaner by 1.5 K
22 *   Used Conditional arithmetic to replace excessive branching
23 *   Also used short instructions wherever possible
24 *
25 * Vineetg: Aug 13th 2008
26 *  -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
27 *   more information in case of a Fatality
28 *
29 * Vineetg: March 25th Bug #92690
30 *  -Added Debug Code to check if sw-ASID == hw-ASID
31
32 * Rahul Trivedi, Amit Bhor: Codito Technologies 2004
33 */
34
35#include <linux/linkage.h>
36#include <asm/entry.h>
37#include <asm/mmu.h>
38#include <asm/pgtable.h>
39#include <asm/arcregs.h>
40#include <asm/cache.h>
41#include <asm/processor.h>
42#include <asm/tlb-mmu1.h>
43
44#ifdef CONFIG_ISA_ARCOMPACT
45;-----------------------------------------------------------------
46; ARC700 Exception Handling doesn't auto-switch stack and it only provides
47; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
48;
49; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
50; "global" is used to free-up FIRST core reg to be able to code the rest of
51; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
52; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
53; need to be saved as well by extending the "global" to be 4 words. Hence
54;	".size   ex_saved_reg1, 16"
55; [All of this dance is to avoid stack switching for each TLB Miss, since we
56; only need to save only a handful of regs, as opposed to complete reg file]
57;
58; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
59; core reg as it will not be SMP safe.
60; Thus scratch AUX reg is used (and no longer used to cache task PGD).
61; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
62; Epilogue thus has to locate the "per-cpu" storage for regs.
63; To avoid cache line bouncing the per-cpu global is aligned/sized per
64; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
65;	".size   ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"
66
67; As simple as that....
68;--------------------------------------------------------------------------
69
70; scratch memory to save [r0-r3] used to code TLB refill Handler
71ARCFP_DATA ex_saved_reg1
72	.align 1 << L1_CACHE_SHIFT
73	.type   ex_saved_reg1, @object
74#ifdef CONFIG_SMP
75	.size   ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
76ex_saved_reg1:
77	.zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
78#else
79	.size   ex_saved_reg1, 16
80ex_saved_reg1:
81	.zero 16
82#endif
83
84.macro TLBMISS_FREEUP_REGS
85#ifdef CONFIG_SMP
86	sr  r0, [ARC_REG_SCRATCH_DATA0]	; freeup r0 to code with
87	GET_CPU_ID  r0			; get to per cpu scratch mem,
88	asl r0, r0, L1_CACHE_SHIFT	; cache line wide per cpu
89	add r0, @ex_saved_reg1, r0
90#else
91	st    r0, [@ex_saved_reg1]
92	mov_s r0, @ex_saved_reg1
93#endif
94	st_s  r1, [r0, 4]
95	st_s  r2, [r0, 8]
96	st_s  r3, [r0, 12]
97
98	; VERIFY if the ASID in MMU-PID Reg is same as
99	; one in Linux data structures
100
101	tlb_paranoid_check_asm
102.endm
103
104.macro TLBMISS_RESTORE_REGS
105#ifdef CONFIG_SMP
106	GET_CPU_ID  r0			; get to per cpu scratch mem
107	asl r0, r0, L1_CACHE_SHIFT	; each is cache line wide
108	add r0, @ex_saved_reg1, r0
109	ld_s  r3, [r0,12]
110	ld_s  r2, [r0, 8]
111	ld_s  r1, [r0, 4]
112	lr    r0, [ARC_REG_SCRATCH_DATA0]
113#else
114	mov_s r0, @ex_saved_reg1
115	ld_s  r3, [r0,12]
116	ld_s  r2, [r0, 8]
117	ld_s  r1, [r0, 4]
118	ld_s  r0, [r0]
119#endif
120.endm
121
122#else	/* ARCv2 */
123
124.macro TLBMISS_FREEUP_REGS
125#ifdef CONFIG_ARC_HAS_LL64
126	std   r0, [sp, -16]
127	std   r2, [sp, -8]
128#else
129	PUSH  r0
130	PUSH  r1
131	PUSH  r2
132	PUSH  r3
133#endif
134.endm
135
136.macro TLBMISS_RESTORE_REGS
137#ifdef CONFIG_ARC_HAS_LL64
138	ldd   r0, [sp, -16]
139	ldd   r2, [sp, -8]
140#else
141	POP   r3
142	POP   r2
143	POP   r1
144	POP   r0
145#endif
146.endm
147
148#endif
149
150;============================================================================
151;  Troubleshooting Stuff
152;============================================================================
153
154; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
155; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
156; we use the MMU PID Reg to get current ASID.
157; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
158; So we try to detect this in TLB Mis shandler
159
160.macro tlb_paranoid_check_asm
161
162#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
163
164	GET_CURR_TASK_ON_CPU  r3
165	ld r0, [r3, TASK_ACT_MM]
166	ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
167	breq r0, 0, 55f	; Error if no ASID allocated
168
169	lr r1, [ARC_REG_PID]
170	and r1, r1, 0xFF
171
172	and r2, r0, 0xFF	; MMU PID bits only for comparison
173	breq r1, r2, 5f
174
17555:
176	; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
177	lr  r2, [erstatus]
178	bbit0 r2, STATUS_U_BIT, 5f
179
180	; We sure are in troubled waters, Flag the error, but to do so
181	; need to switch to kernel mode stack to call error routine
182	GET_TSK_STACK_BASE   r3, sp
183
184	; Call printk to shoutout aloud
185	mov r2, 1
186	j print_asid_mismatch
187
1885:	; ASIDs match so proceed normally
189	nop
190
191#endif
192
193.endm
194
195;============================================================================
196;TLB Miss handling Code
197;============================================================================
198
199;-----------------------------------------------------------------------------
200; This macro does the page-table lookup for the faulting address.
201; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
202.macro LOAD_FAULT_PTE
203
204	lr  r2, [efa]
205
206#ifdef ARC_USE_SCRATCH_REG
207	lr  r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
208#else
209	GET_CURR_TASK_ON_CPU  r1
210	ld  r1, [r1, TASK_ACT_MM]
211	ld  r1, [r1, MM_PGD]
212#endif
213
214	lsr     r0, r2, PGDIR_SHIFT     ; Bits for indexing into PGD
215	ld.as   r3, [r1, r0]            ; PGD entry corresp to faulting addr
216	tst	r3, r3
217	bz	do_slow_path_pf         ; if no Page Table, do page fault
218
219#ifdef CONFIG_TRANSPARENT_HUGEPAGE
220	and.f	0, r3, _PAGE_HW_SZ	; Is this Huge PMD (thp)
221	add2.nz	r1, r1, r0
222	bnz.d	2f		; YES: PGD == PMD has THP PTE: stop pgd walk
223	mov.nz	r0, r3
224
225#endif
226	and	r1, r3, PAGE_MASK
227
228	; Get the PTE entry: The idea is
229	; (1) x = addr >> PAGE_SHIFT 	-> masks page-off bits from @fault-addr
230	; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
231	; (3) z = (pgtbl + y * 4)
232
233#ifdef CONFIG_ARC_HAS_PAE40
234#define PTE_SIZE_LOG	3	/* 8 == 2 ^ 3 */
235#else
236#define PTE_SIZE_LOG	2	/* 4 == 2 ^ 2 */
237#endif
238
239	; multiply in step (3) above avoided by shifting lesser in step (1)
240	lsr     r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG )
241	and     r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG )
242	ld.aw   r0, [r1, r0]            ; r0: PTE (lower word only for PAE40)
243					; r1: PTE ptr
244
2452:
246
247.endm
248
249;-----------------------------------------------------------------
250; Convert Linux PTE entry into TLB entry
251; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
252;    (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])
253; IN: r0 = PTE, r1 = ptr to PTE
254
255.macro CONV_PTE_TO_TLB
256	and    r3, r0, PTE_BITS_RWX	;          r  w  x
257	asl    r2, r3, 3		; Kr Kw Kx 0  0  0 (GLOBAL, kernel only)
258	and.f  0,  r0, _PAGE_GLOBAL
259	or.z   r2, r2, r3		; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page)
260
261	and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE
262	or  r3, r3, r2
263
264	sr  r3, [ARC_REG_TLBPD1]    	; paddr[31..13] | Kr Kw Kx Ur Uw Ux | C
265#ifdef	CONFIG_ARC_HAS_PAE40
266	ld	r3, [r1, 4]		; paddr[39..32]
267	sr	r3, [ARC_REG_TLBPD1HI]
268#endif
269
270	and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
271
272	lr  r3,[ARC_REG_TLBPD0]     ; MMU prepares PD0 with vaddr and asid
273
274	or  r3, r3, r2              ; S | vaddr | {sasid|asid}
275	sr  r3,[ARC_REG_TLBPD0]     ; rewrite PD0
276.endm
277
278;-----------------------------------------------------------------
279; Commit the TLB entry into MMU
280
281.macro COMMIT_ENTRY_TO_MMU
282#if (CONFIG_ARC_MMU_VER < 4)
283
284#ifdef CONFIG_EZNPS_MTM_EXT
285	/* verify if entry for this vaddr+ASID already exists */
286	sr    TLBProbe, [ARC_REG_TLBCOMMAND]
287	lr    r0, [ARC_REG_TLBINDEX]
288	bbit0 r0, 31, 88f
289#endif
290
291	/* Get free TLB slot: Set = computed from vaddr, way = random */
292	sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]
293
294	/* Commit the Write */
295	sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
296
297#else
298	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
299#endif
300
30188:
302.endm
303
304
305ARCFP_CODE	;Fast Path Code, candidate for ICCM
306
307;-----------------------------------------------------------------------------
308; I-TLB Miss Exception Handler
309;-----------------------------------------------------------------------------
310
311ENTRY(EV_TLBMissI)
312
313	TLBMISS_FREEUP_REGS
314
315	;----------------------------------------------------------------
316	; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
317	LOAD_FAULT_PTE
318
319	;----------------------------------------------------------------
320	; VERIFY_PTE: Check if PTE permissions approp for executing code
321	cmp_s   r2, VMALLOC_START
322	mov_s   r2, (_PAGE_PRESENT | _PAGE_EXECUTE)
323	or.hs   r2, r2, _PAGE_GLOBAL
324
325	and     r3, r0, r2  ; Mask out NON Flag bits from PTE
326	xor.f   r3, r3, r2  ; check ( ( pte & flags_test ) == flags_test )
327	bnz     do_slow_path_pf
328
329	; Let Linux VM know that the page was accessed
330	or      r0, r0, _PAGE_ACCESSED  ; set Accessed Bit
331	st_s    r0, [r1]                ; Write back PTE
332
333	CONV_PTE_TO_TLB
334	COMMIT_ENTRY_TO_MMU
335	TLBMISS_RESTORE_REGS
336EV_TLBMissI_fast_ret:	; additional label for VDK OS-kit instrumentation
337	rtie
338
339END(EV_TLBMissI)
340
341;-----------------------------------------------------------------------------
342; D-TLB Miss Exception Handler
343;-----------------------------------------------------------------------------
344
345ENTRY(EV_TLBMissD)
346
347	TLBMISS_FREEUP_REGS
348
349	;----------------------------------------------------------------
350	; Get the PTE corresponding to V-addr accessed
351	; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
352	LOAD_FAULT_PTE
353
354	;----------------------------------------------------------------
355	; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W)
356
357	cmp_s	r2, VMALLOC_START
358	mov_s   r2, _PAGE_PRESENT	; common bit for K/U PTE
359	or.hs	r2, r2, _PAGE_GLOBAL	; kernel PTE only
360
361	; Linux PTE [RWX] bits are semantically overloaded:
362	; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc)
363	; -Otherwise they are user-mode permissions, and those are exactly
364	;  same for kernel mode as well (e.g. copy_(to|from)_user)
365
366	lr      r3, [ecr]
367	btst_s  r3, ECR_C_BIT_DTLB_LD_MISS	; Read Access
368	or.nz   r2, r2, _PAGE_READ      	; chk for Read flag in PTE
369	btst_s  r3, ECR_C_BIT_DTLB_ST_MISS	; Write Access
370	or.nz   r2, r2, _PAGE_WRITE     	; chk for Write flag in PTE
371	; Above laddering takes care of XCHG access (both R and W)
372
373	; By now, r2 setup with all the Flags we need to check in PTE
374	and     r3, r0, r2              ; Mask out NON Flag bits from PTE
375	brne.d  r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test)
376
377	;----------------------------------------------------------------
378	; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
379	or      r0, r0, _PAGE_ACCESSED        ; Accessed bit always
380	or.nz   r0, r0, _PAGE_DIRTY           ; if Write, set Dirty bit as well
381	st_s    r0, [r1]                      ; Write back PTE
382
383	CONV_PTE_TO_TLB
384
385#if (CONFIG_ARC_MMU_VER == 1)
386	; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
387	; memcpy where 3 parties contend for 2 ways, ensuing a livelock.
388	; But only for old MMU or one with Metal Fix
389	TLB_WRITE_HEURISTICS
390#endif
391
392	COMMIT_ENTRY_TO_MMU
393	TLBMISS_RESTORE_REGS
394EV_TLBMissD_fast_ret:	; additional label for VDK OS-kit instrumentation
395	rtie
396
397;-------- Common routine to call Linux Page Fault Handler -----------
398do_slow_path_pf:
399
400#ifdef CONFIG_ISA_ARCV2
401	; Set Z flag if exception in U mode. Hardware micro-ops do this on any
402	; taken interrupt/exception, and thus is already the case at the entry
403	; above, but ensuing code would have already clobbered.
404	; EXCEPTION_PROLOGUE called in slow path, relies on correct Z flag set
405
406	lr	r2, [erstatus]
407	and	r2, r2, STATUS_U_MASK
408	bxor.f	0, r2, STATUS_U_BIT
409#endif
410
411	; Restore the 4-scratch regs saved by fast path miss handler
412	TLBMISS_RESTORE_REGS
413
414	; Slow path TLB Miss handled as a regular ARC Exception
415	; (stack switching / save the complete reg-file).
416	b  call_do_page_fault
417END(EV_TLBMissD)
418