1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier PXs3 SoC 4// 5// Copyright (C) 2017 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 compatible = "socionext,uniphier-pxs3"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 core2 { 31 cpu = <&cpu2>; 32 }; 33 core3 { 34 cpu = <&cpu3>; 35 }; 36 }; 37 }; 38 39 cpu0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0 0x000>; 43 clocks = <&sys_clk 33>; 44 enable-method = "psci"; 45 operating-points-v2 = <&cluster0_opp>; 46 #cooling-cells = <2>; 47 }; 48 49 cpu1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0 0x001>; 53 clocks = <&sys_clk 33>; 54 enable-method = "psci"; 55 operating-points-v2 = <&cluster0_opp>; 56 #cooling-cells = <2>; 57 }; 58 59 cpu2: cpu@2 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0 0x002>; 63 clocks = <&sys_clk 33>; 64 enable-method = "psci"; 65 operating-points-v2 = <&cluster0_opp>; 66 #cooling-cells = <2>; 67 }; 68 69 cpu3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0 0x003>; 73 clocks = <&sys_clk 33>; 74 enable-method = "psci"; 75 operating-points-v2 = <&cluster0_opp>; 76 #cooling-cells = <2>; 77 }; 78 }; 79 80 cluster0_opp: opp-table { 81 compatible = "operating-points-v2"; 82 opp-shared; 83 84 opp-250000000 { 85 opp-hz = /bits/ 64 <250000000>; 86 clock-latency-ns = <300>; 87 }; 88 opp-325000000 { 89 opp-hz = /bits/ 64 <325000000>; 90 clock-latency-ns = <300>; 91 }; 92 opp-500000000 { 93 opp-hz = /bits/ 64 <500000000>; 94 clock-latency-ns = <300>; 95 }; 96 opp-650000000 { 97 opp-hz = /bits/ 64 <650000000>; 98 clock-latency-ns = <300>; 99 }; 100 opp-666667000 { 101 opp-hz = /bits/ 64 <666667000>; 102 clock-latency-ns = <300>; 103 }; 104 opp-866667000 { 105 opp-hz = /bits/ 64 <866667000>; 106 clock-latency-ns = <300>; 107 }; 108 opp-1000000000 { 109 opp-hz = /bits/ 64 <1000000000>; 110 clock-latency-ns = <300>; 111 }; 112 opp-1300000000 { 113 opp-hz = /bits/ 64 <1300000000>; 114 clock-latency-ns = <300>; 115 }; 116 }; 117 118 psci { 119 compatible = "arm,psci-1.0"; 120 method = "smc"; 121 }; 122 123 clocks { 124 refclk: ref { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <25000000>; 128 }; 129 }; 130 131 emmc_pwrseq: emmc-pwrseq { 132 compatible = "mmc-pwrseq-emmc"; 133 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; 134 }; 135 136 timer { 137 compatible = "arm,armv8-timer"; 138 interrupts = <1 13 4>, 139 <1 14 4>, 140 <1 11 4>, 141 <1 10 4>; 142 }; 143 144 thermal-zones { 145 cpu-thermal { 146 polling-delay-passive = <250>; /* 250ms */ 147 polling-delay = <1000>; /* 1000ms */ 148 thermal-sensors = <&pvtctl>; 149 150 trips { 151 cpu_crit: cpu-crit { 152 temperature = <110000>; /* 110C */ 153 hysteresis = <2000>; 154 type = "critical"; 155 }; 156 cpu_alert: cpu-alert { 157 temperature = <100000>; /* 100C */ 158 hysteresis = <2000>; 159 type = "passive"; 160 }; 161 }; 162 163 cooling-maps { 164 map0 { 165 trip = <&cpu_alert>; 166 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 167 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 168 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 169 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 170 }; 171 }; 172 }; 173 }; 174 175 reserved-memory { 176 #address-cells = <2>; 177 #size-cells = <2>; 178 ranges; 179 180 secure-memory@81000000 { 181 reg = <0x0 0x81000000 0x0 0x01000000>; 182 no-map; 183 }; 184 }; 185 186 soc@0 { 187 compatible = "simple-bus"; 188 #address-cells = <1>; 189 #size-cells = <1>; 190 ranges = <0 0 0 0xffffffff>; 191 192 spi0: spi@54006000 { 193 compatible = "socionext,uniphier-scssi"; 194 status = "disabled"; 195 reg = <0x54006000 0x100>; 196 interrupts = <0 39 4>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_spi0>; 199 clocks = <&peri_clk 11>; 200 resets = <&peri_rst 11>; 201 }; 202 203 spi1: spi@54006100 { 204 compatible = "socionext,uniphier-scssi"; 205 status = "disabled"; 206 reg = <0x54006100 0x100>; 207 interrupts = <0 216 4>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_spi1>; 210 clocks = <&peri_clk 12>; 211 resets = <&peri_rst 12>; 212 }; 213 214 serial0: serial@54006800 { 215 compatible = "socionext,uniphier-uart"; 216 status = "disabled"; 217 reg = <0x54006800 0x40>; 218 interrupts = <0 33 4>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_uart0>; 221 clocks = <&peri_clk 0>; 222 resets = <&peri_rst 0>; 223 }; 224 225 serial1: serial@54006900 { 226 compatible = "socionext,uniphier-uart"; 227 status = "disabled"; 228 reg = <0x54006900 0x40>; 229 interrupts = <0 35 4>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_uart1>; 232 clocks = <&peri_clk 1>; 233 resets = <&peri_rst 1>; 234 }; 235 236 serial2: serial@54006a00 { 237 compatible = "socionext,uniphier-uart"; 238 status = "disabled"; 239 reg = <0x54006a00 0x40>; 240 interrupts = <0 37 4>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_uart2>; 243 clocks = <&peri_clk 2>; 244 resets = <&peri_rst 2>; 245 }; 246 247 serial3: serial@54006b00 { 248 compatible = "socionext,uniphier-uart"; 249 status = "disabled"; 250 reg = <0x54006b00 0x40>; 251 interrupts = <0 177 4>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_uart3>; 254 clocks = <&peri_clk 3>; 255 resets = <&peri_rst 3>; 256 }; 257 258 gpio: gpio@55000000 { 259 compatible = "socionext,uniphier-gpio"; 260 reg = <0x55000000 0x200>; 261 interrupt-parent = <&aidet>; 262 interrupt-controller; 263 #interrupt-cells = <2>; 264 gpio-controller; 265 #gpio-cells = <2>; 266 gpio-ranges = <&pinctrl 0 0 0>, 267 <&pinctrl 104 0 0>, 268 <&pinctrl 168 0 0>; 269 gpio-ranges-group-names = "gpio_range0", 270 "gpio_range1", 271 "gpio_range2"; 272 ngpios = <286>; 273 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 274 <21 217 3>; 275 }; 276 277 i2c0: i2c@58780000 { 278 compatible = "socionext,uniphier-fi2c"; 279 status = "disabled"; 280 reg = <0x58780000 0x80>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 interrupts = <0 41 4>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_i2c0>; 286 clocks = <&peri_clk 4>; 287 resets = <&peri_rst 4>; 288 clock-frequency = <100000>; 289 }; 290 291 i2c1: i2c@58781000 { 292 compatible = "socionext,uniphier-fi2c"; 293 status = "disabled"; 294 reg = <0x58781000 0x80>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 interrupts = <0 42 4>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_i2c1>; 300 clocks = <&peri_clk 5>; 301 resets = <&peri_rst 5>; 302 clock-frequency = <100000>; 303 }; 304 305 i2c2: i2c@58782000 { 306 compatible = "socionext,uniphier-fi2c"; 307 status = "disabled"; 308 reg = <0x58782000 0x80>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 interrupts = <0 43 4>; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_i2c2>; 314 clocks = <&peri_clk 6>; 315 resets = <&peri_rst 6>; 316 clock-frequency = <100000>; 317 }; 318 319 i2c3: i2c@58783000 { 320 compatible = "socionext,uniphier-fi2c"; 321 status = "disabled"; 322 reg = <0x58783000 0x80>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 interrupts = <0 44 4>; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&pinctrl_i2c3>; 328 clocks = <&peri_clk 7>; 329 resets = <&peri_rst 7>; 330 clock-frequency = <100000>; 331 }; 332 333 /* chip-internal connection for HDMI */ 334 i2c6: i2c@58786000 { 335 compatible = "socionext,uniphier-fi2c"; 336 reg = <0x58786000 0x80>; 337 #address-cells = <1>; 338 #size-cells = <0>; 339 interrupts = <0 26 4>; 340 clocks = <&peri_clk 10>; 341 resets = <&peri_rst 10>; 342 clock-frequency = <400000>; 343 }; 344 345 system_bus: system-bus@58c00000 { 346 compatible = "socionext,uniphier-system-bus"; 347 status = "disabled"; 348 reg = <0x58c00000 0x400>; 349 #address-cells = <2>; 350 #size-cells = <1>; 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_system_bus>; 353 }; 354 355 smpctrl@59801000 { 356 compatible = "socionext,uniphier-smpctrl"; 357 reg = <0x59801000 0x400>; 358 }; 359 360 sdctrl@59810000 { 361 compatible = "socionext,uniphier-pxs3-sdctrl", 362 "simple-mfd", "syscon"; 363 reg = <0x59810000 0x400>; 364 365 sd_clk: clock { 366 compatible = "socionext,uniphier-pxs3-sd-clock"; 367 #clock-cells = <1>; 368 }; 369 370 sd_rst: reset { 371 compatible = "socionext,uniphier-pxs3-sd-reset"; 372 #reset-cells = <1>; 373 }; 374 }; 375 376 perictrl@59820000 { 377 compatible = "socionext,uniphier-pxs3-perictrl", 378 "simple-mfd", "syscon"; 379 reg = <0x59820000 0x200>; 380 381 peri_clk: clock { 382 compatible = "socionext,uniphier-pxs3-peri-clock"; 383 #clock-cells = <1>; 384 }; 385 386 peri_rst: reset { 387 compatible = "socionext,uniphier-pxs3-peri-reset"; 388 #reset-cells = <1>; 389 }; 390 }; 391 392 emmc: mmc@5a000000 { 393 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 394 reg = <0x5a000000 0x400>; 395 interrupts = <0 78 4>; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&pinctrl_emmc>; 398 clocks = <&sys_clk 4>; 399 resets = <&sys_rst 4>; 400 bus-width = <8>; 401 mmc-ddr-1_8v; 402 mmc-hs200-1_8v; 403 mmc-pwrseq = <&emmc_pwrseq>; 404 cdns,phy-input-delay-legacy = <9>; 405 cdns,phy-input-delay-mmc-highspeed = <2>; 406 cdns,phy-input-delay-mmc-ddr = <3>; 407 cdns,phy-dll-delay-sdclk = <21>; 408 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 409 }; 410 411 sd: mmc@5a400000 { 412 compatible = "socionext,uniphier-sd-v3.1.1"; 413 status = "disabled"; 414 reg = <0x5a400000 0x800>; 415 interrupts = <0 76 4>; 416 pinctrl-names = "default", "uhs"; 417 pinctrl-0 = <&pinctrl_sd>; 418 pinctrl-1 = <&pinctrl_sd_uhs>; 419 clocks = <&sd_clk 0>; 420 reset-names = "host"; 421 resets = <&sd_rst 0>; 422 bus-width = <4>; 423 cap-sd-highspeed; 424 sd-uhs-sdr12; 425 sd-uhs-sdr25; 426 sd-uhs-sdr50; 427 }; 428 429 soc_glue: soc-glue@5f800000 { 430 compatible = "socionext,uniphier-pxs3-soc-glue", 431 "simple-mfd", "syscon"; 432 reg = <0x5f800000 0x2000>; 433 434 pinctrl: pinctrl { 435 compatible = "socionext,uniphier-pxs3-pinctrl"; 436 }; 437 }; 438 439 soc-glue@5f900000 { 440 compatible = "socionext,uniphier-pxs3-soc-glue-debug", 441 "simple-mfd"; 442 #address-cells = <1>; 443 #size-cells = <1>; 444 ranges = <0 0x5f900000 0x2000>; 445 446 efuse@100 { 447 compatible = "socionext,uniphier-efuse"; 448 reg = <0x100 0x28>; 449 }; 450 451 efuse@200 { 452 compatible = "socionext,uniphier-efuse"; 453 reg = <0x200 0x68>; 454 #address-cells = <1>; 455 #size-cells = <1>; 456 457 /* USB cells */ 458 usb_rterm0: trim@54,4 { 459 reg = <0x54 1>; 460 bits = <4 2>; 461 }; 462 usb_rterm1: trim@55,4 { 463 reg = <0x55 1>; 464 bits = <4 2>; 465 }; 466 usb_rterm2: trim@58,4 { 467 reg = <0x58 1>; 468 bits = <4 2>; 469 }; 470 usb_rterm3: trim@59,4 { 471 reg = <0x59 1>; 472 bits = <4 2>; 473 }; 474 usb_sel_t0: trim@54,0 { 475 reg = <0x54 1>; 476 bits = <0 4>; 477 }; 478 usb_sel_t1: trim@55,0 { 479 reg = <0x55 1>; 480 bits = <0 4>; 481 }; 482 usb_sel_t2: trim@58,0 { 483 reg = <0x58 1>; 484 bits = <0 4>; 485 }; 486 usb_sel_t3: trim@59,0 { 487 reg = <0x59 1>; 488 bits = <0 4>; 489 }; 490 usb_hs_i0: trim@56,0 { 491 reg = <0x56 1>; 492 bits = <0 4>; 493 }; 494 usb_hs_i2: trim@5a,0 { 495 reg = <0x5a 1>; 496 bits = <0 4>; 497 }; 498 }; 499 }; 500 501 aidet: interrupt-controller@5fc20000 { 502 compatible = "socionext,uniphier-pxs3-aidet"; 503 reg = <0x5fc20000 0x200>; 504 interrupt-controller; 505 #interrupt-cells = <2>; 506 }; 507 508 gic: interrupt-controller@5fe00000 { 509 compatible = "arm,gic-v3"; 510 reg = <0x5fe00000 0x10000>, /* GICD */ 511 <0x5fe80000 0x80000>; /* GICR */ 512 interrupt-controller; 513 #interrupt-cells = <3>; 514 interrupts = <1 9 4>; 515 }; 516 517 sysctrl@61840000 { 518 compatible = "socionext,uniphier-pxs3-sysctrl", 519 "simple-mfd", "syscon"; 520 reg = <0x61840000 0x10000>; 521 522 sys_clk: clock { 523 compatible = "socionext,uniphier-pxs3-clock"; 524 #clock-cells = <1>; 525 }; 526 527 sys_rst: reset { 528 compatible = "socionext,uniphier-pxs3-reset"; 529 #reset-cells = <1>; 530 }; 531 532 watchdog { 533 compatible = "socionext,uniphier-wdt"; 534 }; 535 536 pvtctl: pvtctl { 537 compatible = "socionext,uniphier-pxs3-thermal"; 538 interrupts = <0 3 4>; 539 #thermal-sensor-cells = <0>; 540 socionext,tmod-calibration = <0x0f22 0x68ee>; 541 }; 542 }; 543 544 eth0: ethernet@65000000 { 545 compatible = "socionext,uniphier-pxs3-ave4"; 546 status = "disabled"; 547 reg = <0x65000000 0x8500>; 548 interrupts = <0 66 4>; 549 pinctrl-names = "default"; 550 pinctrl-0 = <&pinctrl_ether_rgmii>; 551 clock-names = "ether"; 552 clocks = <&sys_clk 6>; 553 reset-names = "ether"; 554 resets = <&sys_rst 6>; 555 phy-mode = "rgmii"; 556 local-mac-address = [00 00 00 00 00 00]; 557 socionext,syscon-phy-mode = <&soc_glue 0>; 558 559 mdio0: mdio { 560 #address-cells = <1>; 561 #size-cells = <0>; 562 }; 563 }; 564 565 eth1: ethernet@65200000 { 566 compatible = "socionext,uniphier-pxs3-ave4"; 567 status = "disabled"; 568 reg = <0x65200000 0x8500>; 569 interrupts = <0 67 4>; 570 pinctrl-names = "default"; 571 pinctrl-0 = <&pinctrl_ether1_rgmii>; 572 clock-names = "ether"; 573 clocks = <&sys_clk 7>; 574 reset-names = "ether"; 575 resets = <&sys_rst 7>; 576 phy-mode = "rgmii"; 577 local-mac-address = [00 00 00 00 00 00]; 578 socionext,syscon-phy-mode = <&soc_glue 1>; 579 580 mdio1: mdio { 581 #address-cells = <1>; 582 #size-cells = <0>; 583 }; 584 }; 585 586 usb0: usb@65a00000 { 587 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 588 status = "disabled"; 589 reg = <0x65a00000 0xcd00>; 590 interrupt-names = "host", "peripheral"; 591 interrupts = <0 134 4>, <0 135 4>; 592 pinctrl-names = "default"; 593 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 594 clock-names = "ref", "bus_early", "suspend"; 595 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; 596 resets = <&usb0_rst 15>; 597 phys = <&usb0_hsphy0>, <&usb0_hsphy1>, 598 <&usb0_ssphy0>, <&usb0_ssphy1>; 599 dr_mode = "host"; 600 }; 601 602 usb-glue@65b00000 { 603 compatible = "socionext,uniphier-pxs3-dwc3-glue", 604 "simple-mfd"; 605 #address-cells = <1>; 606 #size-cells = <1>; 607 ranges = <0 0x65b00000 0x400>; 608 609 usb0_rst: reset@0 { 610 compatible = "socionext,uniphier-pxs3-usb3-reset"; 611 reg = <0x0 0x4>; 612 #reset-cells = <1>; 613 clock-names = "link"; 614 clocks = <&sys_clk 12>; 615 reset-names = "link"; 616 resets = <&sys_rst 12>; 617 }; 618 619 usb0_vbus0: regulator@100 { 620 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 621 reg = <0x100 0x10>; 622 clock-names = "link"; 623 clocks = <&sys_clk 12>; 624 reset-names = "link"; 625 resets = <&sys_rst 12>; 626 }; 627 628 usb0_vbus1: regulator@110 { 629 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 630 reg = <0x110 0x10>; 631 clock-names = "link"; 632 clocks = <&sys_clk 12>; 633 reset-names = "link"; 634 resets = <&sys_rst 12>; 635 }; 636 637 usb0_hsphy0: hs-phy@200 { 638 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 639 reg = <0x200 0x10>; 640 #phy-cells = <0>; 641 clock-names = "link", "phy"; 642 clocks = <&sys_clk 12>, <&sys_clk 16>; 643 reset-names = "link", "phy"; 644 resets = <&sys_rst 12>, <&sys_rst 16>; 645 vbus-supply = <&usb0_vbus0>; 646 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 647 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, 648 <&usb_hs_i0>; 649 }; 650 651 usb0_hsphy1: hs-phy@210 { 652 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 653 reg = <0x210 0x10>; 654 #phy-cells = <0>; 655 clock-names = "link", "phy"; 656 clocks = <&sys_clk 12>, <&sys_clk 16>; 657 reset-names = "link", "phy"; 658 resets = <&sys_rst 12>, <&sys_rst 16>; 659 vbus-supply = <&usb0_vbus1>; 660 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 661 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, 662 <&usb_hs_i0>; 663 }; 664 665 usb0_ssphy0: ss-phy@300 { 666 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 667 reg = <0x300 0x10>; 668 #phy-cells = <0>; 669 clock-names = "link", "phy"; 670 clocks = <&sys_clk 12>, <&sys_clk 17>; 671 reset-names = "link", "phy"; 672 resets = <&sys_rst 12>, <&sys_rst 17>; 673 vbus-supply = <&usb0_vbus0>; 674 }; 675 676 usb0_ssphy1: ss-phy@310 { 677 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 678 reg = <0x310 0x10>; 679 #phy-cells = <0>; 680 clock-names = "link", "phy"; 681 clocks = <&sys_clk 12>, <&sys_clk 18>; 682 reset-names = "link", "phy"; 683 resets = <&sys_rst 12>, <&sys_rst 18>; 684 vbus-supply = <&usb0_vbus1>; 685 }; 686 }; 687 688 usb1: usb@65c00000 { 689 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 690 status = "disabled"; 691 reg = <0x65c00000 0xcd00>; 692 interrupt-names = "host", "peripheral"; 693 interrupts = <0 137 4>, <0 138 4>; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 696 clock-names = "ref", "bus_early", "suspend"; 697 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; 698 resets = <&usb1_rst 15>; 699 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, 700 <&usb1_ssphy0>; 701 dr_mode = "host"; 702 }; 703 704 usb-glue@65d00000 { 705 compatible = "socionext,uniphier-pxs3-dwc3-glue", 706 "simple-mfd"; 707 #address-cells = <1>; 708 #size-cells = <1>; 709 ranges = <0 0x65d00000 0x400>; 710 711 usb1_rst: reset@0 { 712 compatible = "socionext,uniphier-pxs3-usb3-reset"; 713 reg = <0x0 0x4>; 714 #reset-cells = <1>; 715 clock-names = "link"; 716 clocks = <&sys_clk 13>; 717 reset-names = "link"; 718 resets = <&sys_rst 13>; 719 }; 720 721 usb1_vbus0: regulator@100 { 722 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 723 reg = <0x100 0x10>; 724 clock-names = "link"; 725 clocks = <&sys_clk 13>; 726 reset-names = "link"; 727 resets = <&sys_rst 13>; 728 }; 729 730 usb1_vbus1: regulator@110 { 731 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 732 reg = <0x110 0x10>; 733 clock-names = "link"; 734 clocks = <&sys_clk 13>; 735 reset-names = "link"; 736 resets = <&sys_rst 13>; 737 }; 738 739 usb1_hsphy0: hs-phy@200 { 740 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 741 reg = <0x200 0x10>; 742 #phy-cells = <0>; 743 clock-names = "link", "phy", "phy-ext"; 744 clocks = <&sys_clk 13>, <&sys_clk 20>, 745 <&sys_clk 14>; 746 reset-names = "link", "phy"; 747 resets = <&sys_rst 13>, <&sys_rst 20>; 748 vbus-supply = <&usb1_vbus0>; 749 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 750 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, 751 <&usb_hs_i2>; 752 }; 753 754 usb1_hsphy1: hs-phy@210 { 755 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 756 reg = <0x210 0x10>; 757 #phy-cells = <0>; 758 clock-names = "link", "phy", "phy-ext"; 759 clocks = <&sys_clk 13>, <&sys_clk 20>, 760 <&sys_clk 14>; 761 reset-names = "link", "phy"; 762 resets = <&sys_rst 13>, <&sys_rst 20>; 763 vbus-supply = <&usb1_vbus1>; 764 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 765 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, 766 <&usb_hs_i2>; 767 }; 768 769 usb1_ssphy0: ss-phy@300 { 770 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 771 reg = <0x300 0x10>; 772 #phy-cells = <0>; 773 clock-names = "link", "phy", "phy-ext"; 774 clocks = <&sys_clk 13>, <&sys_clk 21>, 775 <&sys_clk 14>; 776 reset-names = "link", "phy"; 777 resets = <&sys_rst 13>, <&sys_rst 21>; 778 vbus-supply = <&usb1_vbus0>; 779 }; 780 }; 781 782 pcie: pcie@66000000 { 783 compatible = "socionext,uniphier-pcie", "snps,dw-pcie"; 784 status = "disabled"; 785 reg-names = "dbi", "link", "config"; 786 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, 787 <0x2fff0000 0x10000>; 788 #address-cells = <3>; 789 #size-cells = <2>; 790 clocks = <&sys_clk 24>; 791 resets = <&sys_rst 24>; 792 num-lanes = <1>; 793 num-viewport = <1>; 794 bus-range = <0x0 0xff>; 795 device_type = "pci"; 796 ranges = 797 /* downstream I/O */ 798 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, 799 /* non-prefetchable memory */ 800 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; 801 #interrupt-cells = <1>; 802 interrupt-names = "dma", "msi"; 803 interrupts = <0 224 4>, <0 225 4>; 804 interrupt-map-mask = <0 0 0 7>; 805 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ 806 <0 0 0 2 &pcie_intc 1>, /* INTB */ 807 <0 0 0 3 &pcie_intc 2>, /* INTC */ 808 <0 0 0 4 &pcie_intc 3>; /* INTD */ 809 phy-names = "pcie-phy"; 810 phys = <&pcie_phy>; 811 812 pcie_intc: legacy-interrupt-controller { 813 interrupt-controller; 814 #interrupt-cells = <1>; 815 interrupt-parent = <&gic>; 816 interrupts = <0 226 4>; 817 }; 818 }; 819 820 pcie_phy: phy@66038000 { 821 compatible = "socionext,uniphier-pxs3-pcie-phy"; 822 reg = <0x66038000 0x4000>; 823 #phy-cells = <0>; 824 clocks = <&sys_clk 24>; 825 resets = <&sys_rst 24>; 826 socionext,syscon = <&soc_glue>; 827 }; 828 829 nand: nand-controller@68000000 { 830 compatible = "socionext,uniphier-denali-nand-v5b"; 831 status = "disabled"; 832 reg-names = "nand_data", "denali_reg"; 833 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 834 #address-cells = <1>; 835 #size-cells = <0>; 836 interrupts = <0 65 4>; 837 pinctrl-names = "default"; 838 pinctrl-0 = <&pinctrl_nand>; 839 clock-names = "nand", "nand_x", "ecc"; 840 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 841 reset-names = "nand", "reg"; 842 resets = <&sys_rst 2>, <&sys_rst 2>; 843 }; 844 }; 845}; 846 847#include "uniphier-pinctrl.dtsi" 848