1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2019, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/power/xlnx-zynqmp-power.h> 16 17/ { 18 compatible = "xlnx,zynqmp"; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 compatible = "arm,cortex-a53"; 28 device_type = "cpu"; 29 enable-method = "psci"; 30 operating-points-v2 = <&cpu_opp_table>; 31 reg = <0x0>; 32 cpu-idle-states = <&CPU_SLEEP_0>; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "arm,cortex-a53"; 37 device_type = "cpu"; 38 enable-method = "psci"; 39 reg = <0x1>; 40 operating-points-v2 = <&cpu_opp_table>; 41 cpu-idle-states = <&CPU_SLEEP_0>; 42 }; 43 44 cpu2: cpu@2 { 45 compatible = "arm,cortex-a53"; 46 device_type = "cpu"; 47 enable-method = "psci"; 48 reg = <0x2>; 49 operating-points-v2 = <&cpu_opp_table>; 50 cpu-idle-states = <&CPU_SLEEP_0>; 51 }; 52 53 cpu3: cpu@3 { 54 compatible = "arm,cortex-a53"; 55 device_type = "cpu"; 56 enable-method = "psci"; 57 reg = <0x3>; 58 operating-points-v2 = <&cpu_opp_table>; 59 cpu-idle-states = <&CPU_SLEEP_0>; 60 }; 61 62 idle-states { 63 entry-method = "psci"; 64 65 CPU_SLEEP_0: cpu-sleep-0 { 66 compatible = "arm,idle-state"; 67 arm,psci-suspend-param = <0x40000000>; 68 local-timer-stop; 69 entry-latency-us = <300>; 70 exit-latency-us = <600>; 71 min-residency-us = <10000>; 72 }; 73 }; 74 }; 75 76 cpu_opp_table: cpu-opp-table { 77 compatible = "operating-points-v2"; 78 opp-shared; 79 opp00 { 80 opp-hz = /bits/ 64 <1199999988>; 81 opp-microvolt = <1000000>; 82 clock-latency-ns = <500000>; 83 }; 84 opp01 { 85 opp-hz = /bits/ 64 <599999994>; 86 opp-microvolt = <1000000>; 87 clock-latency-ns = <500000>; 88 }; 89 opp02 { 90 opp-hz = /bits/ 64 <399999996>; 91 opp-microvolt = <1000000>; 92 clock-latency-ns = <500000>; 93 }; 94 opp03 { 95 opp-hz = /bits/ 64 <299999997>; 96 opp-microvolt = <1000000>; 97 clock-latency-ns = <500000>; 98 }; 99 }; 100 101 dcc: dcc { 102 compatible = "arm,dcc"; 103 status = "disabled"; 104 }; 105 106 pmu { 107 compatible = "arm,armv8-pmuv3"; 108 interrupt-parent = <&gic>; 109 interrupts = <0 143 4>, 110 <0 144 4>, 111 <0 145 4>, 112 <0 146 4>; 113 }; 114 115 psci { 116 compatible = "arm,psci-0.2"; 117 method = "smc"; 118 }; 119 120 firmware { 121 zynqmp_firmware: zynqmp-firmware { 122 compatible = "xlnx,zynqmp-firmware"; 123 #power-domain-cells = <1>; 124 method = "smc"; 125 126 zynqmp_power: zynqmp-power { 127 compatible = "xlnx,zynqmp-power"; 128 interrupt-parent = <&gic>; 129 interrupts = <0 35 4>; 130 }; 131 132 zynqmp_clk: clock-controller { 133 u-boot,dm-pre-reloc; 134 #clock-cells = <1>; 135 compatible = "xlnx,zynqmp-clk"; 136 clocks = <&pss_ref_clk>, 137 <&video_clk>, 138 <&pss_alt_ref_clk>, 139 <&aux_ref_clk>, 140 <>_crx_ref_clk>; 141 clock-names = "pss_ref_clk", 142 "video_clk", 143 "pss_alt_ref_clk", 144 "aux_ref_clk", 145 "gt_crx_ref_clk"; 146 }; 147 148 nvmem_firmware { 149 compatible = "xlnx,zynqmp-nvmem-fw"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 153 soc_revision: soc_revision@0 { 154 reg = <0x0 0x4>; 155 }; 156 }; 157 158 zynqmp_pcap: pcap { 159 compatible = "xlnx,zynqmp-pcap-fpga"; 160 }; 161 162 xlnx_aes: zynqmp-aes { 163 compatible = "xlnx,zynqmp-aes"; 164 }; 165 }; 166 }; 167 168 timer { 169 compatible = "arm,armv8-timer"; 170 interrupt-parent = <&gic>; 171 interrupts = <1 13 0xf08>, 172 <1 14 0xf08>, 173 <1 11 0xf08>, 174 <1 10 0xf08>; 175 }; 176 177 fpga_full: fpga-full { 178 compatible = "fpga-region"; 179 fpga-mgr = <&zynqmp_pcap>; 180 #address-cells = <2>; 181 #size-cells = <2>; 182 ranges; 183 }; 184 185 amba_apu: amba-apu@0 { 186 compatible = "simple-bus"; 187 #address-cells = <2>; 188 #size-cells = <1>; 189 ranges = <0 0 0 0 0xffffffff>; 190 191 gic: interrupt-controller@f9010000 { 192 compatible = "arm,gic-400"; 193 #interrupt-cells = <3>; 194 reg = <0x0 0xf9010000 0x10000>, 195 <0x0 0xf9020000 0x20000>, 196 <0x0 0xf9040000 0x20000>, 197 <0x0 0xf9060000 0x20000>; 198 interrupt-controller; 199 interrupt-parent = <&gic>; 200 interrupts = <1 9 0xf04>; 201 }; 202 }; 203 204 amba: amba { 205 compatible = "simple-bus"; 206 #address-cells = <2>; 207 #size-cells = <2>; 208 ranges; 209 210 can0: can@ff060000 { 211 compatible = "xlnx,zynq-can-1.0"; 212 status = "disabled"; 213 clock-names = "can_clk", "pclk"; 214 reg = <0x0 0xff060000 0x0 0x1000>; 215 interrupts = <0 23 4>; 216 interrupt-parent = <&gic>; 217 tx-fifo-depth = <0x40>; 218 rx-fifo-depth = <0x40>; 219 power-domains = <&zynqmp_firmware PD_CAN_0>; 220 }; 221 222 can1: can@ff070000 { 223 compatible = "xlnx,zynq-can-1.0"; 224 status = "disabled"; 225 clock-names = "can_clk", "pclk"; 226 reg = <0x0 0xff070000 0x0 0x1000>; 227 interrupts = <0 24 4>; 228 interrupt-parent = <&gic>; 229 tx-fifo-depth = <0x40>; 230 rx-fifo-depth = <0x40>; 231 power-domains = <&zynqmp_firmware PD_CAN_1>; 232 }; 233 234 cci: cci@fd6e0000 { 235 compatible = "arm,cci-400"; 236 reg = <0x0 0xfd6e0000 0x0 0x9000>; 237 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 238 #address-cells = <1>; 239 #size-cells = <1>; 240 241 pmu@9000 { 242 compatible = "arm,cci-400-pmu,r1"; 243 reg = <0x9000 0x5000>; 244 interrupt-parent = <&gic>; 245 interrupts = <0 123 4>, 246 <0 123 4>, 247 <0 123 4>, 248 <0 123 4>, 249 <0 123 4>; 250 }; 251 }; 252 253 /* GDMA */ 254 fpd_dma_chan1: dma@fd500000 { 255 status = "disabled"; 256 compatible = "xlnx,zynqmp-dma-1.0"; 257 reg = <0x0 0xfd500000 0x0 0x1000>; 258 interrupt-parent = <&gic>; 259 interrupts = <0 124 4>; 260 clock-names = "clk_main", "clk_apb"; 261 xlnx,bus-width = <128>; 262 power-domains = <&zynqmp_firmware PD_GDMA>; 263 }; 264 265 fpd_dma_chan2: dma@fd510000 { 266 status = "disabled"; 267 compatible = "xlnx,zynqmp-dma-1.0"; 268 reg = <0x0 0xfd510000 0x0 0x1000>; 269 interrupt-parent = <&gic>; 270 interrupts = <0 125 4>; 271 clock-names = "clk_main", "clk_apb"; 272 xlnx,bus-width = <128>; 273 power-domains = <&zynqmp_firmware PD_GDMA>; 274 }; 275 276 fpd_dma_chan3: dma@fd520000 { 277 status = "disabled"; 278 compatible = "xlnx,zynqmp-dma-1.0"; 279 reg = <0x0 0xfd520000 0x0 0x1000>; 280 interrupt-parent = <&gic>; 281 interrupts = <0 126 4>; 282 clock-names = "clk_main", "clk_apb"; 283 xlnx,bus-width = <128>; 284 power-domains = <&zynqmp_firmware PD_GDMA>; 285 }; 286 287 fpd_dma_chan4: dma@fd530000 { 288 status = "disabled"; 289 compatible = "xlnx,zynqmp-dma-1.0"; 290 reg = <0x0 0xfd530000 0x0 0x1000>; 291 interrupt-parent = <&gic>; 292 interrupts = <0 127 4>; 293 clock-names = "clk_main", "clk_apb"; 294 xlnx,bus-width = <128>; 295 power-domains = <&zynqmp_firmware PD_GDMA>; 296 }; 297 298 fpd_dma_chan5: dma@fd540000 { 299 status = "disabled"; 300 compatible = "xlnx,zynqmp-dma-1.0"; 301 reg = <0x0 0xfd540000 0x0 0x1000>; 302 interrupt-parent = <&gic>; 303 interrupts = <0 128 4>; 304 clock-names = "clk_main", "clk_apb"; 305 xlnx,bus-width = <128>; 306 power-domains = <&zynqmp_firmware PD_GDMA>; 307 }; 308 309 fpd_dma_chan6: dma@fd550000 { 310 status = "disabled"; 311 compatible = "xlnx,zynqmp-dma-1.0"; 312 reg = <0x0 0xfd550000 0x0 0x1000>; 313 interrupt-parent = <&gic>; 314 interrupts = <0 129 4>; 315 clock-names = "clk_main", "clk_apb"; 316 xlnx,bus-width = <128>; 317 power-domains = <&zynqmp_firmware PD_GDMA>; 318 }; 319 320 fpd_dma_chan7: dma@fd560000 { 321 status = "disabled"; 322 compatible = "xlnx,zynqmp-dma-1.0"; 323 reg = <0x0 0xfd560000 0x0 0x1000>; 324 interrupt-parent = <&gic>; 325 interrupts = <0 130 4>; 326 clock-names = "clk_main", "clk_apb"; 327 xlnx,bus-width = <128>; 328 power-domains = <&zynqmp_firmware PD_GDMA>; 329 }; 330 331 fpd_dma_chan8: dma@fd570000 { 332 status = "disabled"; 333 compatible = "xlnx,zynqmp-dma-1.0"; 334 reg = <0x0 0xfd570000 0x0 0x1000>; 335 interrupt-parent = <&gic>; 336 interrupts = <0 131 4>; 337 clock-names = "clk_main", "clk_apb"; 338 xlnx,bus-width = <128>; 339 power-domains = <&zynqmp_firmware PD_GDMA>; 340 }; 341 342 /* LPDDMA default allows only secured access. inorder to enable 343 * These dma channels, Users should ensure that these dma 344 * Channels are allowed for non secure access. 345 */ 346 lpd_dma_chan1: dma@ffa80000 { 347 status = "disabled"; 348 compatible = "xlnx,zynqmp-dma-1.0"; 349 reg = <0x0 0xffa80000 0x0 0x1000>; 350 interrupt-parent = <&gic>; 351 interrupts = <0 77 4>; 352 clock-names = "clk_main", "clk_apb"; 353 xlnx,bus-width = <64>; 354 power-domains = <&zynqmp_firmware PD_ADMA>; 355 }; 356 357 lpd_dma_chan2: dma@ffa90000 { 358 status = "disabled"; 359 compatible = "xlnx,zynqmp-dma-1.0"; 360 reg = <0x0 0xffa90000 0x0 0x1000>; 361 interrupt-parent = <&gic>; 362 interrupts = <0 78 4>; 363 clock-names = "clk_main", "clk_apb"; 364 xlnx,bus-width = <64>; 365 power-domains = <&zynqmp_firmware PD_ADMA>; 366 }; 367 368 lpd_dma_chan3: dma@ffaa0000 { 369 status = "disabled"; 370 compatible = "xlnx,zynqmp-dma-1.0"; 371 reg = <0x0 0xffaa0000 0x0 0x1000>; 372 interrupt-parent = <&gic>; 373 interrupts = <0 79 4>; 374 clock-names = "clk_main", "clk_apb"; 375 xlnx,bus-width = <64>; 376 power-domains = <&zynqmp_firmware PD_ADMA>; 377 }; 378 379 lpd_dma_chan4: dma@ffab0000 { 380 status = "disabled"; 381 compatible = "xlnx,zynqmp-dma-1.0"; 382 reg = <0x0 0xffab0000 0x0 0x1000>; 383 interrupt-parent = <&gic>; 384 interrupts = <0 80 4>; 385 clock-names = "clk_main", "clk_apb"; 386 xlnx,bus-width = <64>; 387 power-domains = <&zynqmp_firmware PD_ADMA>; 388 }; 389 390 lpd_dma_chan5: dma@ffac0000 { 391 status = "disabled"; 392 compatible = "xlnx,zynqmp-dma-1.0"; 393 reg = <0x0 0xffac0000 0x0 0x1000>; 394 interrupt-parent = <&gic>; 395 interrupts = <0 81 4>; 396 clock-names = "clk_main", "clk_apb"; 397 xlnx,bus-width = <64>; 398 power-domains = <&zynqmp_firmware PD_ADMA>; 399 }; 400 401 lpd_dma_chan6: dma@ffad0000 { 402 status = "disabled"; 403 compatible = "xlnx,zynqmp-dma-1.0"; 404 reg = <0x0 0xffad0000 0x0 0x1000>; 405 interrupt-parent = <&gic>; 406 interrupts = <0 82 4>; 407 clock-names = "clk_main", "clk_apb"; 408 xlnx,bus-width = <64>; 409 power-domains = <&zynqmp_firmware PD_ADMA>; 410 }; 411 412 lpd_dma_chan7: dma@ffae0000 { 413 status = "disabled"; 414 compatible = "xlnx,zynqmp-dma-1.0"; 415 reg = <0x0 0xffae0000 0x0 0x1000>; 416 interrupt-parent = <&gic>; 417 interrupts = <0 83 4>; 418 clock-names = "clk_main", "clk_apb"; 419 xlnx,bus-width = <64>; 420 power-domains = <&zynqmp_firmware PD_ADMA>; 421 }; 422 423 lpd_dma_chan8: dma@ffaf0000 { 424 status = "disabled"; 425 compatible = "xlnx,zynqmp-dma-1.0"; 426 reg = <0x0 0xffaf0000 0x0 0x1000>; 427 interrupt-parent = <&gic>; 428 interrupts = <0 84 4>; 429 clock-names = "clk_main", "clk_apb"; 430 xlnx,bus-width = <64>; 431 power-domains = <&zynqmp_firmware PD_ADMA>; 432 }; 433 434 mc: memory-controller@fd070000 { 435 compatible = "xlnx,zynqmp-ddrc-2.40a"; 436 reg = <0x0 0xfd070000 0x0 0x30000>; 437 interrupt-parent = <&gic>; 438 interrupts = <0 112 4>; 439 }; 440 441 gem0: ethernet@ff0b0000 { 442 compatible = "cdns,zynqmp-gem", "cdns,gem"; 443 status = "disabled"; 444 interrupt-parent = <&gic>; 445 interrupts = <0 57 4>, <0 57 4>; 446 reg = <0x0 0xff0b0000 0x0 0x1000>; 447 clock-names = "pclk", "hclk", "tx_clk"; 448 #address-cells = <1>; 449 #size-cells = <0>; 450 power-domains = <&zynqmp_firmware PD_ETH_0>; 451 }; 452 453 gem1: ethernet@ff0c0000 { 454 compatible = "cdns,zynqmp-gem", "cdns,gem"; 455 status = "disabled"; 456 interrupt-parent = <&gic>; 457 interrupts = <0 59 4>, <0 59 4>; 458 reg = <0x0 0xff0c0000 0x0 0x1000>; 459 clock-names = "pclk", "hclk", "tx_clk"; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 power-domains = <&zynqmp_firmware PD_ETH_1>; 463 }; 464 465 gem2: ethernet@ff0d0000 { 466 compatible = "cdns,zynqmp-gem", "cdns,gem"; 467 status = "disabled"; 468 interrupt-parent = <&gic>; 469 interrupts = <0 61 4>, <0 61 4>; 470 reg = <0x0 0xff0d0000 0x0 0x1000>; 471 clock-names = "pclk", "hclk", "tx_clk"; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 power-domains = <&zynqmp_firmware PD_ETH_2>; 475 }; 476 477 gem3: ethernet@ff0e0000 { 478 compatible = "cdns,zynqmp-gem", "cdns,gem"; 479 status = "disabled"; 480 interrupt-parent = <&gic>; 481 interrupts = <0 63 4>, <0 63 4>; 482 reg = <0x0 0xff0e0000 0x0 0x1000>; 483 clock-names = "pclk", "hclk", "tx_clk"; 484 #address-cells = <1>; 485 #size-cells = <0>; 486 power-domains = <&zynqmp_firmware PD_ETH_3>; 487 }; 488 489 gpio: gpio@ff0a0000 { 490 compatible = "xlnx,zynqmp-gpio-1.0"; 491 status = "disabled"; 492 #gpio-cells = <0x2>; 493 gpio-controller; 494 interrupt-parent = <&gic>; 495 interrupts = <0 16 4>; 496 interrupt-controller; 497 #interrupt-cells = <2>; 498 reg = <0x0 0xff0a0000 0x0 0x1000>; 499 power-domains = <&zynqmp_firmware PD_GPIO>; 500 }; 501 502 i2c0: i2c@ff020000 { 503 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 504 status = "disabled"; 505 interrupt-parent = <&gic>; 506 interrupts = <0 17 4>; 507 reg = <0x0 0xff020000 0x0 0x1000>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 power-domains = <&zynqmp_firmware PD_I2C_0>; 511 }; 512 513 i2c1: i2c@ff030000 { 514 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 515 status = "disabled"; 516 interrupt-parent = <&gic>; 517 interrupts = <0 18 4>; 518 reg = <0x0 0xff030000 0x0 0x1000>; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 power-domains = <&zynqmp_firmware PD_I2C_1>; 522 }; 523 524 pcie: pcie@fd0e0000 { 525 compatible = "xlnx,nwl-pcie-2.11"; 526 status = "disabled"; 527 #address-cells = <3>; 528 #size-cells = <2>; 529 #interrupt-cells = <1>; 530 msi-controller; 531 device_type = "pci"; 532 interrupt-parent = <&gic>; 533 interrupts = <0 118 4>, 534 <0 117 4>, 535 <0 116 4>, 536 <0 115 4>, /* MSI_1 [63...32] */ 537 <0 114 4>; /* MSI_0 [31...0] */ 538 interrupt-names = "misc", "dummy", "intx", 539 "msi1", "msi0"; 540 msi-parent = <&pcie>; 541 reg = <0x0 0xfd0e0000 0x0 0x1000>, 542 <0x0 0xfd480000 0x0 0x1000>, 543 <0x80 0x00000000 0x0 0x1000000>; 544 reg-names = "breg", "pcireg", "cfg"; 545 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 546 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 547 bus-range = <0x00 0xff>; 548 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 549 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 550 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 551 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 552 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 553 power-domains = <&zynqmp_firmware PD_PCIE>; 554 pcie_intc: legacy-interrupt-controller { 555 interrupt-controller; 556 #address-cells = <0>; 557 #interrupt-cells = <1>; 558 }; 559 }; 560 561 rtc: rtc@ffa60000 { 562 compatible = "xlnx,zynqmp-rtc"; 563 status = "disabled"; 564 reg = <0x0 0xffa60000 0x0 0x100>; 565 interrupt-parent = <&gic>; 566 interrupts = <0 26 4>, <0 27 4>; 567 interrupt-names = "alarm", "sec"; 568 calibration = <0x8000>; 569 }; 570 571 sata: ahci@fd0c0000 { 572 compatible = "ceva,ahci-1v84"; 573 status = "disabled"; 574 reg = <0x0 0xfd0c0000 0x0 0x2000>; 575 interrupt-parent = <&gic>; 576 interrupts = <0 133 4>; 577 power-domains = <&zynqmp_firmware PD_SATA>; 578 }; 579 580 sdhci0: mmc@ff160000 { 581 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 582 status = "disabled"; 583 interrupt-parent = <&gic>; 584 interrupts = <0 48 4>; 585 reg = <0x0 0xff160000 0x0 0x1000>; 586 clock-names = "clk_xin", "clk_ahb"; 587 #clock-cells = <1>; 588 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 589 power-domains = <&zynqmp_firmware PD_SD_0>; 590 }; 591 592 sdhci1: mmc@ff170000 { 593 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 594 status = "disabled"; 595 interrupt-parent = <&gic>; 596 interrupts = <0 49 4>; 597 reg = <0x0 0xff170000 0x0 0x1000>; 598 clock-names = "clk_xin", "clk_ahb"; 599 #clock-cells = <1>; 600 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 601 power-domains = <&zynqmp_firmware PD_SD_1>; 602 }; 603 604 smmu: smmu@fd800000 { 605 compatible = "arm,mmu-500"; 606 reg = <0x0 0xfd800000 0x0 0x20000>; 607 status = "disabled"; 608 #global-interrupts = <1>; 609 interrupt-parent = <&gic>; 610 interrupts = <0 155 4>, 611 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 612 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 613 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 614 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 615 }; 616 617 spi0: spi@ff040000 { 618 compatible = "cdns,spi-r1p6"; 619 status = "disabled"; 620 interrupt-parent = <&gic>; 621 interrupts = <0 19 4>; 622 reg = <0x0 0xff040000 0x0 0x1000>; 623 clock-names = "ref_clk", "pclk"; 624 #address-cells = <1>; 625 #size-cells = <0>; 626 power-domains = <&zynqmp_firmware PD_SPI_0>; 627 }; 628 629 spi1: spi@ff050000 { 630 compatible = "cdns,spi-r1p6"; 631 status = "disabled"; 632 interrupt-parent = <&gic>; 633 interrupts = <0 20 4>; 634 reg = <0x0 0xff050000 0x0 0x1000>; 635 clock-names = "ref_clk", "pclk"; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 power-domains = <&zynqmp_firmware PD_SPI_1>; 639 }; 640 641 ttc0: timer@ff110000 { 642 compatible = "cdns,ttc"; 643 status = "disabled"; 644 interrupt-parent = <&gic>; 645 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 646 reg = <0x0 0xff110000 0x0 0x1000>; 647 timer-width = <32>; 648 power-domains = <&zynqmp_firmware PD_TTC_0>; 649 }; 650 651 ttc1: timer@ff120000 { 652 compatible = "cdns,ttc"; 653 status = "disabled"; 654 interrupt-parent = <&gic>; 655 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 656 reg = <0x0 0xff120000 0x0 0x1000>; 657 timer-width = <32>; 658 power-domains = <&zynqmp_firmware PD_TTC_1>; 659 }; 660 661 ttc2: timer@ff130000 { 662 compatible = "cdns,ttc"; 663 status = "disabled"; 664 interrupt-parent = <&gic>; 665 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 666 reg = <0x0 0xff130000 0x0 0x1000>; 667 timer-width = <32>; 668 power-domains = <&zynqmp_firmware PD_TTC_2>; 669 }; 670 671 ttc3: timer@ff140000 { 672 compatible = "cdns,ttc"; 673 status = "disabled"; 674 interrupt-parent = <&gic>; 675 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 676 reg = <0x0 0xff140000 0x0 0x1000>; 677 timer-width = <32>; 678 power-domains = <&zynqmp_firmware PD_TTC_3>; 679 }; 680 681 uart0: serial@ff000000 { 682 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 683 status = "disabled"; 684 interrupt-parent = <&gic>; 685 interrupts = <0 21 4>; 686 reg = <0x0 0xff000000 0x0 0x1000>; 687 clock-names = "uart_clk", "pclk"; 688 power-domains = <&zynqmp_firmware PD_UART_0>; 689 }; 690 691 uart1: serial@ff010000 { 692 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 693 status = "disabled"; 694 interrupt-parent = <&gic>; 695 interrupts = <0 22 4>; 696 reg = <0x0 0xff010000 0x0 0x1000>; 697 clock-names = "uart_clk", "pclk"; 698 power-domains = <&zynqmp_firmware PD_UART_1>; 699 }; 700 701 usb0: usb@fe200000 { 702 compatible = "snps,dwc3"; 703 status = "disabled"; 704 interrupt-parent = <&gic>; 705 interrupts = <0 65 4>; 706 reg = <0x0 0xfe200000 0x0 0x40000>; 707 clock-names = "clk_xin", "clk_ahb"; 708 power-domains = <&zynqmp_firmware PD_USB_0>; 709 }; 710 711 usb1: usb@fe300000 { 712 compatible = "snps,dwc3"; 713 status = "disabled"; 714 interrupt-parent = <&gic>; 715 interrupts = <0 70 4>; 716 reg = <0x0 0xfe300000 0x0 0x40000>; 717 clock-names = "clk_xin", "clk_ahb"; 718 power-domains = <&zynqmp_firmware PD_USB_1>; 719 }; 720 721 watchdog0: watchdog@fd4d0000 { 722 compatible = "cdns,wdt-r1p2"; 723 status = "disabled"; 724 interrupt-parent = <&gic>; 725 interrupts = <0 113 1>; 726 reg = <0x0 0xfd4d0000 0x0 0x1000>; 727 timeout-sec = <10>; 728 }; 729 }; 730}; 731