1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __AMDGPU_DM_H__ 27 #define __AMDGPU_DM_H__ 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_connector.h> 31 #include <drm/drm_crtc.h> 32 #include <drm/drm_dp_mst_helper.h> 33 #include <drm/drm_plane.h> 34 35 /* 36 * This file contains the definition for amdgpu_display_manager 37 * and its API for amdgpu driver's use. 38 * This component provides all the display related functionality 39 * and this is the only component that calls DAL API. 40 * The API contained here intended for amdgpu driver use. 41 * The API that is called directly from KMS framework is located 42 * in amdgpu_dm_kms.h file 43 */ 44 45 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 46 /* 47 #include "include/amdgpu_dal_power_if.h" 48 #include "amdgpu_dm_irq.h" 49 */ 50 51 #include "irq_types.h" 52 #include "signal_types.h" 53 54 /* Forward declarations */ 55 struct amdgpu_device; 56 struct drm_device; 57 struct amdgpu_dm_irq_handler_data; 58 struct dc; 59 60 struct common_irq_params { 61 struct amdgpu_device *adev; 62 enum dc_irq_source irq_src; 63 }; 64 65 /** 66 * struct irq_list_head - Linked-list for low context IRQ handlers. 67 * 68 * @head: The list_head within &struct handler_data 69 * @work: A work_struct containing the deferred handler work 70 */ 71 struct irq_list_head { 72 struct list_head head; 73 /* In case this interrupt needs post-processing, 'work' will be queued*/ 74 struct work_struct work; 75 }; 76 77 /** 78 * struct dm_compressor_info - Buffer info used by frame buffer compression 79 * @cpu_addr: MMIO cpu addr 80 * @bo_ptr: Pointer to the buffer object 81 * @gpu_addr: MMIO gpu addr 82 */ 83 struct dm_comressor_info { 84 void *cpu_addr; 85 struct amdgpu_bo *bo_ptr; 86 uint64_t gpu_addr; 87 }; 88 89 /** 90 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI 91 * @min_input_signal: minimum possible input in range 0-255 92 * @max_input_signal: maximum possible input in range 0-255 93 * @caps_valid: true if these values are from the ACPI interface 94 */ 95 struct amdgpu_dm_backlight_caps { 96 int min_input_signal; 97 int max_input_signal; 98 bool caps_valid; 99 }; 100 101 /** 102 * struct amdgpu_display_manager - Central amdgpu display manager device 103 * 104 * @dc: Display Core control structure 105 * @adev: AMDGPU base driver structure 106 * @ddev: DRM base driver structure 107 * @display_indexes_num: Max number of display streams supported 108 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 109 * @backlight_dev: Backlight control device 110 * @cached_state: Caches device atomic state for suspend/resume 111 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info 112 */ 113 struct amdgpu_display_manager { 114 115 struct dc *dc; 116 117 /** 118 * @cgs_device: 119 * 120 * The Common Graphics Services device. It provides an interface for 121 * accessing registers. 122 */ 123 struct cgs_device *cgs_device; 124 125 struct amdgpu_device *adev; 126 struct drm_device *ddev; 127 u16 display_indexes_num; 128 129 /** 130 * @atomic_obj 131 * 132 * In combination with &dm_atomic_state it helps manage 133 * global atomic state that doesn't map cleanly into existing 134 * drm resources, like &dc_context. 135 */ 136 struct drm_private_obj atomic_obj; 137 138 /** 139 * @dc_lock: 140 * 141 * Guards access to DC functions that can issue register write 142 * sequences. 143 */ 144 struct mutex dc_lock; 145 146 /** 147 * @audio_lock: 148 * 149 * Guards access to audio instance changes. 150 */ 151 struct mutex audio_lock; 152 153 /** 154 * @audio_component: 155 * 156 * Used to notify ELD changes to sound driver. 157 */ 158 struct drm_audio_component *audio_component; 159 160 /** 161 * @audio_registered: 162 * 163 * True if the audio component has been registered 164 * successfully, false otherwise. 165 */ 166 bool audio_registered; 167 168 /** 169 * @irq_handler_list_low_tab: 170 * 171 * Low priority IRQ handler table. 172 * 173 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 174 * source. Low priority IRQ handlers are deferred to a workqueue to be 175 * processed. Hence, they can sleep. 176 * 177 * Note that handlers are called in the same order as they were 178 * registered (FIFO). 179 */ 180 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 181 182 /** 183 * @irq_handler_list_high_tab: 184 * 185 * High priority IRQ handler table. 186 * 187 * It is a n*m table, same as &irq_handler_list_low_tab. However, 188 * handlers in this table are not deferred and are called immediately. 189 */ 190 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 191 192 /** 193 * @pflip_params: 194 * 195 * Page flip IRQ parameters, passed to registered handlers when 196 * triggered. 197 */ 198 struct common_irq_params 199 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 200 201 /** 202 * @vblank_params: 203 * 204 * Vertical blanking IRQ parameters, passed to registered handlers when 205 * triggered. 206 */ 207 struct common_irq_params 208 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 209 210 /** 211 * @vupdate_params: 212 * 213 * Vertical update IRQ parameters, passed to registered handlers when 214 * triggered. 215 */ 216 struct common_irq_params 217 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 218 219 spinlock_t irq_handler_list_table_lock; 220 221 struct backlight_device *backlight_dev; 222 223 const struct dc_link *backlight_link; 224 struct amdgpu_dm_backlight_caps backlight_caps; 225 226 struct mod_freesync *freesync_module; 227 228 struct drm_atomic_state *cached_state; 229 230 struct dm_comressor_info compressor; 231 232 const struct firmware *fw_dmcu; 233 uint32_t dmcu_fw_version; 234 #ifdef CONFIG_DRM_AMD_DC_DCN2_0 235 /** 236 * gpu_info FW provided soc bounding box struct or 0 if not 237 * available in FW 238 */ 239 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 240 #endif 241 }; 242 243 struct amdgpu_dm_connector { 244 245 struct drm_connector base; 246 uint32_t connector_id; 247 248 /* we need to mind the EDID between detect 249 and get modes due to analog/digital/tvencoder */ 250 struct edid *edid; 251 252 /* shared with amdgpu */ 253 struct amdgpu_hpd hpd; 254 255 /* number of modes generated from EDID at 'dc_sink' */ 256 int num_modes; 257 258 /* The 'old' sink - before an HPD. 259 * The 'current' sink is in dc_link->sink. */ 260 struct dc_sink *dc_sink; 261 struct dc_link *dc_link; 262 struct dc_sink *dc_em_sink; 263 264 /* DM only */ 265 struct drm_dp_mst_topology_mgr mst_mgr; 266 struct amdgpu_dm_dp_aux dm_dp_aux; 267 struct drm_dp_mst_port *port; 268 struct amdgpu_dm_connector *mst_port; 269 struct amdgpu_encoder *mst_encoder; 270 271 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 272 struct amdgpu_i2c_adapter *i2c; 273 274 /* Monitor range limits */ 275 int min_vfreq ; 276 int max_vfreq ; 277 int pixel_clock_mhz; 278 279 /* Audio instance - protected by audio_lock. */ 280 int audio_inst; 281 282 struct mutex hpd_lock; 283 284 bool fake_enable; 285 #ifdef CONFIG_DEBUG_FS 286 uint32_t debugfs_dpcd_address; 287 uint32_t debugfs_dpcd_size; 288 #endif 289 }; 290 291 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 292 293 extern const struct amdgpu_ip_block_version dm_ip_block; 294 295 struct amdgpu_framebuffer; 296 struct amdgpu_display_manager; 297 struct dc_validation_set; 298 struct dc_plane_state; 299 300 struct dm_plane_state { 301 struct drm_plane_state base; 302 struct dc_plane_state *dc_state; 303 }; 304 305 struct dm_crtc_state { 306 struct drm_crtc_state base; 307 struct dc_stream_state *stream; 308 309 bool cm_has_degamma; 310 bool cm_is_degamma_srgb; 311 312 int active_planes; 313 bool interrupts_enabled; 314 315 int crc_skip_count; 316 bool crc_enabled; 317 318 bool freesync_timing_changed; 319 bool freesync_vrr_info_changed; 320 321 bool vrr_supported; 322 struct mod_freesync_config freesync_config; 323 struct mod_vrr_params vrr_params; 324 struct dc_info_packet vrr_infopacket; 325 326 int abm_level; 327 }; 328 329 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 330 331 struct dm_atomic_state { 332 struct drm_private_state base; 333 334 struct dc_state *context; 335 }; 336 337 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 338 339 struct dm_connector_state { 340 struct drm_connector_state base; 341 342 enum amdgpu_rmx_type scaling; 343 uint8_t underscan_vborder; 344 uint8_t underscan_hborder; 345 bool underscan_enable; 346 bool freesync_capable; 347 uint8_t abm_level; 348 }; 349 350 #define to_dm_connector_state(x)\ 351 container_of((x), struct dm_connector_state, base) 352 353 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 354 struct drm_connector_state * 355 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 356 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 357 struct drm_connector_state *state, 358 struct drm_property *property, 359 uint64_t val); 360 361 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 362 const struct drm_connector_state *state, 363 struct drm_property *property, 364 uint64_t *val); 365 366 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 367 368 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 369 struct amdgpu_dm_connector *aconnector, 370 int connector_type, 371 struct dc_link *link, 372 int link_index); 373 374 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 375 struct drm_display_mode *mode); 376 377 void dm_restore_drm_connector_state(struct drm_device *dev, 378 struct drm_connector *connector); 379 380 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 381 struct edid *edid); 382 383 /* amdgpu_dm_crc.c */ 384 #ifdef CONFIG_DEBUG_FS 385 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); 386 int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, 387 const char *src_name, 388 size_t *values_cnt); 389 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); 390 #else 391 #define amdgpu_dm_crtc_set_crc_source NULL 392 #define amdgpu_dm_crtc_verify_crc_source NULL 393 #define amdgpu_dm_crtc_handle_crc_irq(x) 394 #endif 395 396 #define MAX_COLOR_LUT_ENTRIES 4096 397 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 398 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 399 400 void amdgpu_dm_init_color_mod(void); 401 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 402 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 403 struct dc_plane_state *dc_plane_state); 404 405 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 406 407 #endif /* __AMDGPU_DM_H__ */ 408