1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Texas Instruments 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 /* LCDC DRM driver, based on da8xx-fb */ 8 9 #include <linux/component.h> 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_debugfs.h> 18 #include <drm/drm_drv.h> 19 #include <drm/drm_fb_helper.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_irq.h> 24 #include <drm/drm_mm.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_vblank.h> 27 28 29 #include "tilcdc_drv.h" 30 #include "tilcdc_external.h" 31 #include "tilcdc_panel.h" 32 #include "tilcdc_regs.h" 33 34 static LIST_HEAD(module_list); 35 36 static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 }; 37 38 static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565, 39 DRM_FORMAT_BGR888, 40 DRM_FORMAT_XBGR8888 }; 41 42 static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565, 43 DRM_FORMAT_RGB888, 44 DRM_FORMAT_XRGB8888 }; 45 46 static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565, 47 DRM_FORMAT_RGB888, 48 DRM_FORMAT_XRGB8888 }; 49 50 void tilcdc_module_init(struct tilcdc_module *mod, const char *name, 51 const struct tilcdc_module_ops *funcs) 52 { 53 mod->name = name; 54 mod->funcs = funcs; 55 INIT_LIST_HEAD(&mod->list); 56 list_add(&mod->list, &module_list); 57 } 58 59 void tilcdc_module_cleanup(struct tilcdc_module *mod) 60 { 61 list_del(&mod->list); 62 } 63 64 static struct of_device_id tilcdc_of_match[]; 65 66 static int tilcdc_atomic_check(struct drm_device *dev, 67 struct drm_atomic_state *state) 68 { 69 int ret; 70 71 ret = drm_atomic_helper_check_modeset(dev, state); 72 if (ret) 73 return ret; 74 75 ret = drm_atomic_helper_check_planes(dev, state); 76 if (ret) 77 return ret; 78 79 /* 80 * tilcdc ->atomic_check can update ->mode_changed if pixel format 81 * changes, hence will we check modeset changes again. 82 */ 83 ret = drm_atomic_helper_check_modeset(dev, state); 84 if (ret) 85 return ret; 86 87 return ret; 88 } 89 90 static int tilcdc_commit(struct drm_device *dev, 91 struct drm_atomic_state *state, 92 bool async) 93 { 94 int ret; 95 96 ret = drm_atomic_helper_prepare_planes(dev, state); 97 if (ret) 98 return ret; 99 100 ret = drm_atomic_helper_swap_state(state, true); 101 if (ret) { 102 drm_atomic_helper_cleanup_planes(dev, state); 103 return ret; 104 } 105 106 /* 107 * Everything below can be run asynchronously without the need to grab 108 * any modeset locks at all under one condition: It must be guaranteed 109 * that the asynchronous work has either been cancelled (if the driver 110 * supports it, which at least requires that the framebuffers get 111 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed 112 * before the new state gets committed on the software side with 113 * drm_atomic_helper_swap_state(). 114 * 115 * This scheme allows new atomic state updates to be prepared and 116 * checked in parallel to the asynchronous completion of the previous 117 * update. Which is important since compositors need to figure out the 118 * composition of the next frame right after having submitted the 119 * current layout. 120 */ 121 122 drm_atomic_helper_commit_modeset_disables(dev, state); 123 124 drm_atomic_helper_commit_planes(dev, state, 0); 125 126 drm_atomic_helper_commit_modeset_enables(dev, state); 127 128 drm_atomic_helper_wait_for_vblanks(dev, state); 129 130 drm_atomic_helper_cleanup_planes(dev, state); 131 132 return 0; 133 } 134 135 static const struct drm_mode_config_funcs mode_config_funcs = { 136 .fb_create = drm_gem_fb_create, 137 .atomic_check = tilcdc_atomic_check, 138 .atomic_commit = tilcdc_commit, 139 }; 140 141 static void modeset_init(struct drm_device *dev) 142 { 143 struct tilcdc_drm_private *priv = dev->dev_private; 144 struct tilcdc_module *mod; 145 146 list_for_each_entry(mod, &module_list, list) { 147 DBG("loading module: %s", mod->name); 148 mod->funcs->modeset_init(mod, dev); 149 } 150 151 dev->mode_config.min_width = 0; 152 dev->mode_config.min_height = 0; 153 dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc); 154 dev->mode_config.max_height = 2048; 155 dev->mode_config.funcs = &mode_config_funcs; 156 } 157 158 #ifdef CONFIG_CPU_FREQ 159 static int cpufreq_transition(struct notifier_block *nb, 160 unsigned long val, void *data) 161 { 162 struct tilcdc_drm_private *priv = container_of(nb, 163 struct tilcdc_drm_private, freq_transition); 164 165 if (val == CPUFREQ_POSTCHANGE) 166 tilcdc_crtc_update_clk(priv->crtc); 167 168 return 0; 169 } 170 #endif 171 172 /* 173 * DRM operations: 174 */ 175 176 static void tilcdc_fini(struct drm_device *dev) 177 { 178 struct tilcdc_drm_private *priv = dev->dev_private; 179 180 #ifdef CONFIG_CPU_FREQ 181 if (priv->freq_transition.notifier_call) 182 cpufreq_unregister_notifier(&priv->freq_transition, 183 CPUFREQ_TRANSITION_NOTIFIER); 184 #endif 185 186 if (priv->crtc) 187 tilcdc_crtc_shutdown(priv->crtc); 188 189 if (priv->is_registered) 190 drm_dev_unregister(dev); 191 192 drm_kms_helper_poll_fini(dev); 193 drm_irq_uninstall(dev); 194 drm_mode_config_cleanup(dev); 195 196 if (priv->clk) 197 clk_put(priv->clk); 198 199 if (priv->mmio) 200 iounmap(priv->mmio); 201 202 if (priv->wq) { 203 flush_workqueue(priv->wq); 204 destroy_workqueue(priv->wq); 205 } 206 207 dev->dev_private = NULL; 208 209 pm_runtime_disable(dev->dev); 210 211 drm_dev_put(dev); 212 } 213 214 static int tilcdc_init(struct drm_driver *ddrv, struct device *dev) 215 { 216 struct drm_device *ddev; 217 struct platform_device *pdev = to_platform_device(dev); 218 struct device_node *node = dev->of_node; 219 struct tilcdc_drm_private *priv; 220 struct resource *res; 221 u32 bpp = 0; 222 int ret; 223 224 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 225 if (!priv) 226 return -ENOMEM; 227 228 ddev = drm_dev_alloc(ddrv, dev); 229 if (IS_ERR(ddev)) 230 return PTR_ERR(ddev); 231 232 ddev->dev_private = priv; 233 platform_set_drvdata(pdev, ddev); 234 drm_mode_config_init(ddev); 235 236 priv->is_componentized = 237 tilcdc_get_external_components(dev, NULL) > 0; 238 239 priv->wq = alloc_ordered_workqueue("tilcdc", 0); 240 if (!priv->wq) { 241 ret = -ENOMEM; 242 goto init_failed; 243 } 244 245 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 246 if (!res) { 247 dev_err(dev, "failed to get memory resource\n"); 248 ret = -EINVAL; 249 goto init_failed; 250 } 251 252 priv->mmio = ioremap(res->start, resource_size(res)); 253 if (!priv->mmio) { 254 dev_err(dev, "failed to ioremap\n"); 255 ret = -ENOMEM; 256 goto init_failed; 257 } 258 259 priv->clk = clk_get(dev, "fck"); 260 if (IS_ERR(priv->clk)) { 261 dev_err(dev, "failed to get functional clock\n"); 262 ret = -ENODEV; 263 goto init_failed; 264 } 265 266 if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth)) 267 priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH; 268 269 DBG("Maximum Bandwidth Value %d", priv->max_bandwidth); 270 271 if (of_property_read_u32(node, "max-width", &priv->max_width)) 272 priv->max_width = TILCDC_DEFAULT_MAX_WIDTH; 273 274 DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width); 275 276 if (of_property_read_u32(node, "max-pixelclock", 277 &priv->max_pixelclock)) 278 priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK; 279 280 DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock); 281 282 pm_runtime_enable(dev); 283 284 /* Determine LCD IP Version */ 285 pm_runtime_get_sync(dev); 286 switch (tilcdc_read(ddev, LCDC_PID_REG)) { 287 case 0x4c100102: 288 priv->rev = 1; 289 break; 290 case 0x4f200800: 291 case 0x4f201000: 292 priv->rev = 2; 293 break; 294 default: 295 dev_warn(dev, "Unknown PID Reg value 0x%08x, " 296 "defaulting to LCD revision 1\n", 297 tilcdc_read(ddev, LCDC_PID_REG)); 298 priv->rev = 1; 299 break; 300 } 301 302 pm_runtime_put_sync(dev); 303 304 if (priv->rev == 1) { 305 DBG("Revision 1 LCDC supports only RGB565 format"); 306 priv->pixelformats = tilcdc_rev1_formats; 307 priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats); 308 bpp = 16; 309 } else { 310 const char *str = "\0"; 311 312 of_property_read_string(node, "blue-and-red-wiring", &str); 313 if (0 == strcmp(str, "crossed")) { 314 DBG("Configured for crossed blue and red wires"); 315 priv->pixelformats = tilcdc_crossed_formats; 316 priv->num_pixelformats = 317 ARRAY_SIZE(tilcdc_crossed_formats); 318 bpp = 32; /* Choose bpp with RGB support for fbdef */ 319 } else if (0 == strcmp(str, "straight")) { 320 DBG("Configured for straight blue and red wires"); 321 priv->pixelformats = tilcdc_straight_formats; 322 priv->num_pixelformats = 323 ARRAY_SIZE(tilcdc_straight_formats); 324 bpp = 16; /* Choose bpp with RGB support for fbdef */ 325 } else { 326 DBG("Blue and red wiring '%s' unknown, use legacy mode", 327 str); 328 priv->pixelformats = tilcdc_legacy_formats; 329 priv->num_pixelformats = 330 ARRAY_SIZE(tilcdc_legacy_formats); 331 bpp = 16; /* This is just a guess */ 332 } 333 } 334 335 ret = tilcdc_crtc_create(ddev); 336 if (ret < 0) { 337 dev_err(dev, "failed to create crtc\n"); 338 goto init_failed; 339 } 340 modeset_init(ddev); 341 342 #ifdef CONFIG_CPU_FREQ 343 priv->freq_transition.notifier_call = cpufreq_transition; 344 ret = cpufreq_register_notifier(&priv->freq_transition, 345 CPUFREQ_TRANSITION_NOTIFIER); 346 if (ret) { 347 dev_err(dev, "failed to register cpufreq notifier\n"); 348 priv->freq_transition.notifier_call = NULL; 349 goto init_failed; 350 } 351 #endif 352 353 if (priv->is_componentized) { 354 ret = component_bind_all(dev, ddev); 355 if (ret < 0) 356 goto init_failed; 357 358 ret = tilcdc_add_component_encoder(ddev); 359 if (ret < 0) 360 goto init_failed; 361 } else { 362 ret = tilcdc_attach_external_device(ddev); 363 if (ret) 364 goto init_failed; 365 } 366 367 if (!priv->external_connector && 368 ((priv->num_encoders == 0) || (priv->num_connectors == 0))) { 369 dev_err(dev, "no encoders/connectors found\n"); 370 ret = -EPROBE_DEFER; 371 goto init_failed; 372 } 373 374 ret = drm_vblank_init(ddev, 1); 375 if (ret < 0) { 376 dev_err(dev, "failed to initialize vblank\n"); 377 goto init_failed; 378 } 379 380 ret = drm_irq_install(ddev, platform_get_irq(pdev, 0)); 381 if (ret < 0) { 382 dev_err(dev, "failed to install IRQ handler\n"); 383 goto init_failed; 384 } 385 386 drm_mode_config_reset(ddev); 387 388 drm_kms_helper_poll_init(ddev); 389 390 ret = drm_dev_register(ddev, 0); 391 if (ret) 392 goto init_failed; 393 394 drm_fbdev_generic_setup(ddev, bpp); 395 396 priv->is_registered = true; 397 return 0; 398 399 init_failed: 400 tilcdc_fini(ddev); 401 402 return ret; 403 } 404 405 static irqreturn_t tilcdc_irq(int irq, void *arg) 406 { 407 struct drm_device *dev = arg; 408 struct tilcdc_drm_private *priv = dev->dev_private; 409 return tilcdc_crtc_irq(priv->crtc); 410 } 411 412 #if defined(CONFIG_DEBUG_FS) 413 static const struct { 414 const char *name; 415 uint8_t rev; 416 uint8_t save; 417 uint32_t reg; 418 } registers[] = { 419 #define REG(rev, save, reg) { #reg, rev, save, reg } 420 /* exists in revision 1: */ 421 REG(1, false, LCDC_PID_REG), 422 REG(1, true, LCDC_CTRL_REG), 423 REG(1, false, LCDC_STAT_REG), 424 REG(1, true, LCDC_RASTER_CTRL_REG), 425 REG(1, true, LCDC_RASTER_TIMING_0_REG), 426 REG(1, true, LCDC_RASTER_TIMING_1_REG), 427 REG(1, true, LCDC_RASTER_TIMING_2_REG), 428 REG(1, true, LCDC_DMA_CTRL_REG), 429 REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG), 430 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG), 431 REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG), 432 REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG), 433 /* new in revision 2: */ 434 REG(2, false, LCDC_RAW_STAT_REG), 435 REG(2, false, LCDC_MASKED_STAT_REG), 436 REG(2, true, LCDC_INT_ENABLE_SET_REG), 437 REG(2, false, LCDC_INT_ENABLE_CLR_REG), 438 REG(2, false, LCDC_END_OF_INT_IND_REG), 439 REG(2, true, LCDC_CLK_ENABLE_REG), 440 #undef REG 441 }; 442 443 #endif 444 445 #ifdef CONFIG_DEBUG_FS 446 static int tilcdc_regs_show(struct seq_file *m, void *arg) 447 { 448 struct drm_info_node *node = (struct drm_info_node *) m->private; 449 struct drm_device *dev = node->minor->dev; 450 struct tilcdc_drm_private *priv = dev->dev_private; 451 unsigned i; 452 453 pm_runtime_get_sync(dev->dev); 454 455 seq_printf(m, "revision: %d\n", priv->rev); 456 457 for (i = 0; i < ARRAY_SIZE(registers); i++) 458 if (priv->rev >= registers[i].rev) 459 seq_printf(m, "%s:\t %08x\n", registers[i].name, 460 tilcdc_read(dev, registers[i].reg)); 461 462 pm_runtime_put_sync(dev->dev); 463 464 return 0; 465 } 466 467 static int tilcdc_mm_show(struct seq_file *m, void *arg) 468 { 469 struct drm_info_node *node = (struct drm_info_node *) m->private; 470 struct drm_device *dev = node->minor->dev; 471 struct drm_printer p = drm_seq_file_printer(m); 472 drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p); 473 return 0; 474 } 475 476 static struct drm_info_list tilcdc_debugfs_list[] = { 477 { "regs", tilcdc_regs_show, 0 }, 478 { "mm", tilcdc_mm_show, 0 }, 479 }; 480 481 static int tilcdc_debugfs_init(struct drm_minor *minor) 482 { 483 struct drm_device *dev = minor->dev; 484 struct tilcdc_module *mod; 485 int ret; 486 487 ret = drm_debugfs_create_files(tilcdc_debugfs_list, 488 ARRAY_SIZE(tilcdc_debugfs_list), 489 minor->debugfs_root, minor); 490 491 list_for_each_entry(mod, &module_list, list) 492 if (mod->funcs->debugfs_init) 493 mod->funcs->debugfs_init(mod, minor); 494 495 if (ret) { 496 dev_err(dev->dev, "could not install tilcdc_debugfs_list\n"); 497 return ret; 498 } 499 500 return ret; 501 } 502 #endif 503 504 DEFINE_DRM_GEM_CMA_FOPS(fops); 505 506 static struct drm_driver tilcdc_driver = { 507 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 508 .irq_handler = tilcdc_irq, 509 .gem_free_object_unlocked = drm_gem_cma_free_object, 510 .gem_print_info = drm_gem_cma_print_info, 511 .gem_vm_ops = &drm_gem_cma_vm_ops, 512 .dumb_create = drm_gem_cma_dumb_create, 513 514 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 515 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 516 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, 517 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, 518 .gem_prime_vmap = drm_gem_cma_prime_vmap, 519 .gem_prime_vunmap = drm_gem_cma_prime_vunmap, 520 .gem_prime_mmap = drm_gem_cma_prime_mmap, 521 #ifdef CONFIG_DEBUG_FS 522 .debugfs_init = tilcdc_debugfs_init, 523 #endif 524 .fops = &fops, 525 .name = "tilcdc", 526 .desc = "TI LCD Controller DRM", 527 .date = "20121205", 528 .major = 1, 529 .minor = 0, 530 }; 531 532 /* 533 * Power management: 534 */ 535 536 #ifdef CONFIG_PM_SLEEP 537 static int tilcdc_pm_suspend(struct device *dev) 538 { 539 struct drm_device *ddev = dev_get_drvdata(dev); 540 int ret = 0; 541 542 ret = drm_mode_config_helper_suspend(ddev); 543 544 /* Select sleep pin state */ 545 pinctrl_pm_select_sleep_state(dev); 546 547 return ret; 548 } 549 550 static int tilcdc_pm_resume(struct device *dev) 551 { 552 struct drm_device *ddev = dev_get_drvdata(dev); 553 554 /* Select default pin state */ 555 pinctrl_pm_select_default_state(dev); 556 return drm_mode_config_helper_resume(ddev); 557 } 558 #endif 559 560 static const struct dev_pm_ops tilcdc_pm_ops = { 561 SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume) 562 }; 563 564 /* 565 * Platform driver: 566 */ 567 static int tilcdc_bind(struct device *dev) 568 { 569 return tilcdc_init(&tilcdc_driver, dev); 570 } 571 572 static void tilcdc_unbind(struct device *dev) 573 { 574 struct drm_device *ddev = dev_get_drvdata(dev); 575 576 /* Check if a subcomponent has already triggered the unloading. */ 577 if (!ddev->dev_private) 578 return; 579 580 tilcdc_fini(dev_get_drvdata(dev)); 581 } 582 583 static const struct component_master_ops tilcdc_comp_ops = { 584 .bind = tilcdc_bind, 585 .unbind = tilcdc_unbind, 586 }; 587 588 static int tilcdc_pdev_probe(struct platform_device *pdev) 589 { 590 struct component_match *match = NULL; 591 int ret; 592 593 /* bail out early if no DT data: */ 594 if (!pdev->dev.of_node) { 595 dev_err(&pdev->dev, "device-tree data is missing\n"); 596 return -ENXIO; 597 } 598 599 ret = tilcdc_get_external_components(&pdev->dev, &match); 600 if (ret < 0) 601 return ret; 602 else if (ret == 0) 603 return tilcdc_init(&tilcdc_driver, &pdev->dev); 604 else 605 return component_master_add_with_match(&pdev->dev, 606 &tilcdc_comp_ops, 607 match); 608 } 609 610 static int tilcdc_pdev_remove(struct platform_device *pdev) 611 { 612 int ret; 613 614 ret = tilcdc_get_external_components(&pdev->dev, NULL); 615 if (ret < 0) 616 return ret; 617 else if (ret == 0) 618 tilcdc_fini(platform_get_drvdata(pdev)); 619 else 620 component_master_del(&pdev->dev, &tilcdc_comp_ops); 621 622 return 0; 623 } 624 625 static struct of_device_id tilcdc_of_match[] = { 626 { .compatible = "ti,am33xx-tilcdc", }, 627 { .compatible = "ti,da850-tilcdc", }, 628 { }, 629 }; 630 MODULE_DEVICE_TABLE(of, tilcdc_of_match); 631 632 static struct platform_driver tilcdc_platform_driver = { 633 .probe = tilcdc_pdev_probe, 634 .remove = tilcdc_pdev_remove, 635 .driver = { 636 .name = "tilcdc", 637 .pm = &tilcdc_pm_ops, 638 .of_match_table = tilcdc_of_match, 639 }, 640 }; 641 642 static int __init tilcdc_drm_init(void) 643 { 644 DBG("init"); 645 tilcdc_panel_init(); 646 return platform_driver_register(&tilcdc_platform_driver); 647 } 648 649 static void __exit tilcdc_drm_fini(void) 650 { 651 DBG("fini"); 652 platform_driver_unregister(&tilcdc_platform_driver); 653 tilcdc_panel_fini(); 654 } 655 656 module_init(tilcdc_drm_init); 657 module_exit(tilcdc_drm_fini); 658 659 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 660 MODULE_DESCRIPTION("TI LCD Controller DRM Driver"); 661 MODULE_LICENSE("GPL"); 662