1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/gpio/meson-a1-gpio.h>
9
10/ {
11	compatible = "amlogic,a1";
12
13	interrupt-parent = <&gic>;
14	#address-cells = <2>;
15	#size-cells = <2>;
16
17	cpus {
18		#address-cells = <2>;
19		#size-cells = <0>;
20
21		cpu0: cpu@0 {
22			device_type = "cpu";
23			compatible = "arm,cortex-a35";
24			reg = <0x0 0x0>;
25			enable-method = "psci";
26			next-level-cache = <&l2>;
27		};
28
29		cpu1: cpu@1 {
30			device_type = "cpu";
31			compatible = "arm,cortex-a35";
32			reg = <0x0 0x1>;
33			enable-method = "psci";
34			next-level-cache = <&l2>;
35		};
36
37		l2: l2-cache0 {
38			compatible = "cache";
39		};
40	};
41
42	psci {
43		compatible = "arm,psci-1.0";
44		method = "smc";
45	};
46
47	reserved-memory {
48		#address-cells = <2>;
49		#size-cells = <2>;
50		ranges;
51
52		linux,cma {
53			compatible = "shared-dma-pool";
54			reusable;
55			size = <0x0 0x800000>;
56			alignment = <0x0 0x400000>;
57			linux,cma-default;
58		};
59	};
60
61	sm: secure-monitor {
62		compatible = "amlogic,meson-gxbb-sm";
63	};
64
65	soc {
66		compatible = "simple-bus";
67		#address-cells = <2>;
68		#size-cells = <2>;
69		ranges;
70
71		apb: bus@fe000000 {
72			compatible = "simple-bus";
73			reg = <0x0 0xfe000000 0x0 0x1000000>;
74			#address-cells = <2>;
75			#size-cells = <2>;
76			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
77
78
79			reset: reset-controller@0 {
80				compatible = "amlogic,meson-a1-reset";
81				reg = <0x0 0x0 0x0 0x8c>;
82				#reset-cells = <1>;
83			};
84
85			periphs_pinctrl: pinctrl@0400 {
86				compatible = "amlogic,meson-a1-periphs-pinctrl";
87				#address-cells = <2>;
88				#size-cells = <2>;
89				ranges;
90
91				gpio: bank@0400 {
92					reg = <0x0 0x0400 0x0 0x003c>,
93					      <0x0 0x0480 0x0 0x0118>;
94					reg-names = "mux", "gpio";
95					gpio-controller;
96					#gpio-cells = <2>;
97					gpio-ranges = <&periphs_pinctrl 0 0 62>;
98				};
99
100			};
101
102			uart_AO: serial@1c00 {
103				compatible = "amlogic,meson-gx-uart",
104					     "amlogic,meson-ao-uart";
105				reg = <0x0 0x1c00 0x0 0x18>;
106				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
107				clocks = <&xtal>, <&xtal>, <&xtal>;
108				clock-names = "xtal", "pclk", "baud";
109				status = "disabled";
110			};
111
112			uart_AO_B: serial@2000 {
113				compatible = "amlogic,meson-gx-uart",
114					     "amlogic,meson-ao-uart";
115				reg = <0x0 0x2000 0x0 0x18>;
116				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
117				clocks = <&xtal>, <&xtal>, <&xtal>;
118				clock-names = "xtal", "pclk", "baud";
119				status = "disabled";
120			};
121		};
122
123		gic: interrupt-controller@ff901000 {
124			compatible = "arm,gic-400";
125			reg = <0x0 0xff901000 0x0 0x1000>,
126			      <0x0 0xff902000 0x0 0x2000>,
127			      <0x0 0xff904000 0x0 0x2000>,
128			      <0x0 0xff906000 0x0 0x2000>;
129			interrupt-controller;
130			interrupts = <GIC_PPI 9
131				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
132			#interrupt-cells = <3>;
133			#address-cells = <0>;
134		};
135	};
136
137	timer {
138		compatible = "arm,armv8-timer";
139		interrupts = <GIC_PPI 13
140			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
141			     <GIC_PPI 14
142			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
143			     <GIC_PPI 11
144			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
145			     <GIC_PPI 10
146			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
147	};
148
149	xtal: xtal-clk {
150		compatible = "fixed-clock";
151		clock-frequency = <24000000>;
152		clock-output-names = "xtal";
153		#clock-cells = <0>;
154	};
155};
156