1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
4  *
5  * Based on msm_serial.c, which is:
6  * Copyright (C) 2007 Google, Inc.
7  * Author: Robert Love <rlove@google.com>
8  */
9 
10 #include <linux/hrtimer.h>
11 #include <linux/delay.h>
12 #include <linux/io.h>
13 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/init.h>
16 #include <linux/console.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/slab.h>
22 #include <linux/clk.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/err.h>
26 
27 /*
28  * UART Register offsets
29  */
30 
31 #define VT8500_URTDR		0x0000	/* Transmit data */
32 #define VT8500_URRDR		0x0004	/* Receive data */
33 #define VT8500_URDIV		0x0008	/* Clock/Baud rate divisor */
34 #define VT8500_URLCR		0x000C	/* Line control */
35 #define VT8500_URICR		0x0010	/* IrDA control */
36 #define VT8500_URIER		0x0014	/* Interrupt enable */
37 #define VT8500_URISR		0x0018	/* Interrupt status */
38 #define VT8500_URUSR		0x001c	/* UART status */
39 #define VT8500_URFCR		0x0020	/* FIFO control */
40 #define VT8500_URFIDX		0x0024	/* FIFO index */
41 #define VT8500_URBKR		0x0028	/* Break signal count */
42 #define VT8500_URTOD		0x002c	/* Time out divisor */
43 #define VT8500_TXFIFO		0x1000	/* Transmit FIFO (16x8) */
44 #define VT8500_RXFIFO		0x1020	/* Receive FIFO (16x10) */
45 
46 /*
47  * Interrupt enable and status bits
48  */
49 
50 #define TXDE	(1 << 0)	/* Tx Data empty */
51 #define RXDF	(1 << 1)	/* Rx Data full */
52 #define TXFAE	(1 << 2)	/* Tx FIFO almost empty */
53 #define TXFE	(1 << 3)	/* Tx FIFO empty */
54 #define RXFAF	(1 << 4)	/* Rx FIFO almost full */
55 #define RXFF	(1 << 5)	/* Rx FIFO full */
56 #define TXUDR	(1 << 6)	/* Tx underrun */
57 #define RXOVER	(1 << 7)	/* Rx overrun */
58 #define PER	(1 << 8)	/* Parity error */
59 #define FER	(1 << 9)	/* Frame error */
60 #define TCTS	(1 << 10)	/* Toggle of CTS */
61 #define RXTOUT	(1 << 11)	/* Rx timeout */
62 #define BKDONE	(1 << 12)	/* Break signal done */
63 #define ERR	(1 << 13)	/* AHB error response */
64 
65 #define RX_FIFO_INTS	(RXFAF | RXFF | RXOVER | PER | FER | RXTOUT)
66 #define TX_FIFO_INTS	(TXFAE | TXFE | TXUDR)
67 
68 /*
69  * Line control bits
70  */
71 
72 #define VT8500_TXEN	(1 << 0)	/* Enable transmit logic */
73 #define VT8500_RXEN	(1 << 1)	/* Enable receive logic */
74 #define VT8500_CS8	(1 << 2)	/* 8-bit data length (vs. 7-bit) */
75 #define VT8500_CSTOPB	(1 << 3)	/* 2 stop bits (vs. 1) */
76 #define VT8500_PARENB	(1 << 4)	/* Enable parity */
77 #define VT8500_PARODD	(1 << 5)	/* Odd parity (vs. even) */
78 #define VT8500_RTS	(1 << 6)	/* Ready to send */
79 #define VT8500_LOOPBK	(1 << 7)	/* Enable internal loopback */
80 #define VT8500_DMA	(1 << 8)	/* Enable DMA mode (needs FIFO) */
81 #define VT8500_BREAK	(1 << 9)	/* Initiate break signal */
82 #define VT8500_PSLVERR	(1 << 10)	/* APB error upon empty RX FIFO read */
83 #define VT8500_SWRTSCTS	(1 << 11)	/* Software-controlled RTS/CTS */
84 
85 /*
86  * Capability flags (driver-internal)
87  */
88 
89 #define VT8500_HAS_SWRTSCTS_SWITCH	(1 << 1)
90 
91 #define VT8500_RECOMMENDED_CLK		12000000
92 #define VT8500_OVERSAMPLING_DIVISOR	13
93 #define VT8500_MAX_PORTS	6
94 
95 struct vt8500_port {
96 	struct uart_port	uart;
97 	char			name[16];
98 	struct clk		*clk;
99 	unsigned int		clk_predivisor;
100 	unsigned int		ier;
101 	unsigned int		vt8500_uart_flags;
102 };
103 
104 /*
105  * we use this variable to keep track of which ports
106  * have been allocated as we can't use pdev->id in
107  * devicetree
108  */
109 static DECLARE_BITMAP(vt8500_ports_in_use, VT8500_MAX_PORTS);
110 
111 static inline void vt8500_write(struct uart_port *port, unsigned int val,
112 			     unsigned int off)
113 {
114 	writel(val, port->membase + off);
115 }
116 
117 static inline unsigned int vt8500_read(struct uart_port *port, unsigned int off)
118 {
119 	return readl(port->membase + off);
120 }
121 
122 static void vt8500_stop_tx(struct uart_port *port)
123 {
124 	struct vt8500_port *vt8500_port = container_of(port,
125 						       struct vt8500_port,
126 						       uart);
127 
128 	vt8500_port->ier &= ~TX_FIFO_INTS;
129 	vt8500_write(port, vt8500_port->ier, VT8500_URIER);
130 }
131 
132 static void vt8500_stop_rx(struct uart_port *port)
133 {
134 	struct vt8500_port *vt8500_port = container_of(port,
135 						       struct vt8500_port,
136 						       uart);
137 
138 	vt8500_port->ier &= ~RX_FIFO_INTS;
139 	vt8500_write(port, vt8500_port->ier, VT8500_URIER);
140 }
141 
142 static void vt8500_enable_ms(struct uart_port *port)
143 {
144 	struct vt8500_port *vt8500_port = container_of(port,
145 						       struct vt8500_port,
146 						       uart);
147 
148 	vt8500_port->ier |= TCTS;
149 	vt8500_write(port, vt8500_port->ier, VT8500_URIER);
150 }
151 
152 static void handle_rx(struct uart_port *port)
153 {
154 	struct tty_port *tport = &port->state->port;
155 
156 	/*
157 	 * Handle overrun
158 	 */
159 	if ((vt8500_read(port, VT8500_URISR) & RXOVER)) {
160 		port->icount.overrun++;
161 		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
162 	}
163 
164 	/* and now the main RX loop */
165 	while (vt8500_read(port, VT8500_URFIDX) & 0x1f00) {
166 		unsigned int c;
167 		char flag = TTY_NORMAL;
168 
169 		c = readw(port->membase + VT8500_RXFIFO) & 0x3ff;
170 
171 		/* Mask conditions we're ignorning. */
172 		c &= ~port->read_status_mask;
173 
174 		if (c & FER) {
175 			port->icount.frame++;
176 			flag = TTY_FRAME;
177 		} else if (c & PER) {
178 			port->icount.parity++;
179 			flag = TTY_PARITY;
180 		}
181 		port->icount.rx++;
182 
183 		if (!uart_handle_sysrq_char(port, c))
184 			tty_insert_flip_char(tport, c, flag);
185 	}
186 
187 	spin_unlock(&port->lock);
188 	tty_flip_buffer_push(tport);
189 	spin_lock(&port->lock);
190 }
191 
192 static void handle_tx(struct uart_port *port)
193 {
194 	struct circ_buf *xmit = &port->state->xmit;
195 
196 	if (port->x_char) {
197 		writeb(port->x_char, port->membase + VT8500_TXFIFO);
198 		port->icount.tx++;
199 		port->x_char = 0;
200 	}
201 	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
202 		vt8500_stop_tx(port);
203 		return;
204 	}
205 
206 	while ((vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16) {
207 		if (uart_circ_empty(xmit))
208 			break;
209 
210 		writeb(xmit->buf[xmit->tail], port->membase + VT8500_TXFIFO);
211 
212 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
213 		port->icount.tx++;
214 	}
215 
216 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
217 		uart_write_wakeup(port);
218 
219 	if (uart_circ_empty(xmit))
220 		vt8500_stop_tx(port);
221 }
222 
223 static void vt8500_start_tx(struct uart_port *port)
224 {
225 	struct vt8500_port *vt8500_port = container_of(port,
226 						       struct vt8500_port,
227 						       uart);
228 
229 	vt8500_port->ier &= ~TX_FIFO_INTS;
230 	vt8500_write(port, vt8500_port->ier, VT8500_URIER);
231 	handle_tx(port);
232 	vt8500_port->ier |= TX_FIFO_INTS;
233 	vt8500_write(port, vt8500_port->ier, VT8500_URIER);
234 }
235 
236 static void handle_delta_cts(struct uart_port *port)
237 {
238 	port->icount.cts++;
239 	wake_up_interruptible(&port->state->port.delta_msr_wait);
240 }
241 
242 static irqreturn_t vt8500_irq(int irq, void *dev_id)
243 {
244 	struct uart_port *port = dev_id;
245 	unsigned long isr;
246 
247 	spin_lock(&port->lock);
248 	isr = vt8500_read(port, VT8500_URISR);
249 
250 	/* Acknowledge active status bits */
251 	vt8500_write(port, isr, VT8500_URISR);
252 
253 	if (isr & RX_FIFO_INTS)
254 		handle_rx(port);
255 	if (isr & TX_FIFO_INTS)
256 		handle_tx(port);
257 	if (isr & TCTS)
258 		handle_delta_cts(port);
259 
260 	spin_unlock(&port->lock);
261 
262 	return IRQ_HANDLED;
263 }
264 
265 static unsigned int vt8500_tx_empty(struct uart_port *port)
266 {
267 	return (vt8500_read(port, VT8500_URFIDX) & 0x1f) < 16 ?
268 						TIOCSER_TEMT : 0;
269 }
270 
271 static unsigned int vt8500_get_mctrl(struct uart_port *port)
272 {
273 	unsigned int usr;
274 
275 	usr = vt8500_read(port, VT8500_URUSR);
276 	if (usr & (1 << 4))
277 		return TIOCM_CTS;
278 	else
279 		return 0;
280 }
281 
282 static void vt8500_set_mctrl(struct uart_port *port, unsigned int mctrl)
283 {
284 	unsigned int lcr = vt8500_read(port, VT8500_URLCR);
285 
286 	if (mctrl & TIOCM_RTS)
287 		lcr |= VT8500_RTS;
288 	else
289 		lcr &= ~VT8500_RTS;
290 
291 	vt8500_write(port, lcr, VT8500_URLCR);
292 }
293 
294 static void vt8500_break_ctl(struct uart_port *port, int break_ctl)
295 {
296 	if (break_ctl)
297 		vt8500_write(port,
298 			     vt8500_read(port, VT8500_URLCR) | VT8500_BREAK,
299 			     VT8500_URLCR);
300 }
301 
302 static int vt8500_set_baud_rate(struct uart_port *port, unsigned int baud)
303 {
304 	struct vt8500_port *vt8500_port =
305 			container_of(port, struct vt8500_port, uart);
306 	unsigned long div;
307 	unsigned int loops = 1000;
308 
309 	div = ((vt8500_port->clk_predivisor - 1) & 0xf) << 16;
310 	div |= (uart_get_divisor(port, baud) - 1) & 0x3ff;
311 
312 	/* Effective baud rate */
313 	baud = port->uartclk / 16 / ((div & 0x3ff) + 1);
314 
315 	while ((vt8500_read(port, VT8500_URUSR) & (1 << 5)) && --loops)
316 		cpu_relax();
317 
318 	vt8500_write(port, div, VT8500_URDIV);
319 
320 	/* Break signal timing depends on baud rate, update accordingly */
321 	vt8500_write(port, mult_frac(baud, 4096, 1000000), VT8500_URBKR);
322 
323 	return baud;
324 }
325 
326 static int vt8500_startup(struct uart_port *port)
327 {
328 	struct vt8500_port *vt8500_port =
329 			container_of(port, struct vt8500_port, uart);
330 	int ret;
331 
332 	snprintf(vt8500_port->name, sizeof(vt8500_port->name),
333 		 "vt8500_serial%d", port->line);
334 
335 	ret = request_irq(port->irq, vt8500_irq, IRQF_TRIGGER_HIGH,
336 			  vt8500_port->name, port);
337 	if (unlikely(ret))
338 		return ret;
339 
340 	vt8500_write(port, 0x03, VT8500_URLCR);	/* enable TX & RX */
341 
342 	return 0;
343 }
344 
345 static void vt8500_shutdown(struct uart_port *port)
346 {
347 	struct vt8500_port *vt8500_port =
348 			container_of(port, struct vt8500_port, uart);
349 
350 	vt8500_port->ier = 0;
351 
352 	/* disable interrupts and FIFOs */
353 	vt8500_write(&vt8500_port->uart, 0, VT8500_URIER);
354 	vt8500_write(&vt8500_port->uart, 0x880, VT8500_URFCR);
355 	free_irq(port->irq, port);
356 }
357 
358 static void vt8500_set_termios(struct uart_port *port,
359 			       struct ktermios *termios,
360 			       struct ktermios *old)
361 {
362 	struct vt8500_port *vt8500_port =
363 			container_of(port, struct vt8500_port, uart);
364 	unsigned long flags;
365 	unsigned int baud, lcr;
366 	unsigned int loops = 1000;
367 
368 	spin_lock_irqsave(&port->lock, flags);
369 
370 	/* calculate and set baud rate */
371 	baud = uart_get_baud_rate(port, termios, old, 900, 921600);
372 	baud = vt8500_set_baud_rate(port, baud);
373 	if (tty_termios_baud_rate(termios))
374 		tty_termios_encode_baud_rate(termios, baud, baud);
375 
376 	/* calculate parity */
377 	lcr = vt8500_read(&vt8500_port->uart, VT8500_URLCR);
378 	lcr &= ~(VT8500_PARENB | VT8500_PARODD);
379 	if (termios->c_cflag & PARENB) {
380 		lcr |= VT8500_PARENB;
381 		termios->c_cflag &= ~CMSPAR;
382 		if (termios->c_cflag & PARODD)
383 			lcr |= VT8500_PARODD;
384 	}
385 
386 	/* calculate bits per char */
387 	lcr &= ~VT8500_CS8;
388 	switch (termios->c_cflag & CSIZE) {
389 	case CS7:
390 		break;
391 	case CS8:
392 	default:
393 		lcr |= VT8500_CS8;
394 		termios->c_cflag &= ~CSIZE;
395 		termios->c_cflag |= CS8;
396 		break;
397 	}
398 
399 	/* calculate stop bits */
400 	lcr &= ~VT8500_CSTOPB;
401 	if (termios->c_cflag & CSTOPB)
402 		lcr |= VT8500_CSTOPB;
403 
404 	lcr &= ~VT8500_SWRTSCTS;
405 	if (vt8500_port->vt8500_uart_flags & VT8500_HAS_SWRTSCTS_SWITCH)
406 		lcr |= VT8500_SWRTSCTS;
407 
408 	/* set parity, bits per char, and stop bit */
409 	vt8500_write(&vt8500_port->uart, lcr, VT8500_URLCR);
410 
411 	/* Configure status bits to ignore based on termio flags. */
412 	port->read_status_mask = 0;
413 	if (termios->c_iflag & IGNPAR)
414 		port->read_status_mask = FER | PER;
415 
416 	uart_update_timeout(port, termios->c_cflag, baud);
417 
418 	/* Reset FIFOs */
419 	vt8500_write(&vt8500_port->uart, 0x88c, VT8500_URFCR);
420 	while ((vt8500_read(&vt8500_port->uart, VT8500_URFCR) & 0xc)
421 							&& --loops)
422 		cpu_relax();
423 
424 	/* Every possible FIFO-related interrupt */
425 	vt8500_port->ier = RX_FIFO_INTS | TX_FIFO_INTS;
426 
427 	/*
428 	 * CTS flow control
429 	 */
430 	if (UART_ENABLE_MS(&vt8500_port->uart, termios->c_cflag))
431 		vt8500_port->ier |= TCTS;
432 
433 	vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR);
434 	vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER);
435 
436 	spin_unlock_irqrestore(&port->lock, flags);
437 }
438 
439 static const char *vt8500_type(struct uart_port *port)
440 {
441 	struct vt8500_port *vt8500_port =
442 			container_of(port, struct vt8500_port, uart);
443 	return vt8500_port->name;
444 }
445 
446 static void vt8500_release_port(struct uart_port *port)
447 {
448 }
449 
450 static int vt8500_request_port(struct uart_port *port)
451 {
452 	return 0;
453 }
454 
455 static void vt8500_config_port(struct uart_port *port, int flags)
456 {
457 	port->type = PORT_VT8500;
458 }
459 
460 static int vt8500_verify_port(struct uart_port *port,
461 			      struct serial_struct *ser)
462 {
463 	if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_VT8500))
464 		return -EINVAL;
465 	if (unlikely(port->irq != ser->irq))
466 		return -EINVAL;
467 	return 0;
468 }
469 
470 static struct vt8500_port *vt8500_uart_ports[VT8500_MAX_PORTS];
471 static struct uart_driver vt8500_uart_driver;
472 
473 #ifdef CONFIG_SERIAL_VT8500_CONSOLE
474 
475 static void wait_for_xmitr(struct uart_port *port)
476 {
477 	unsigned int status, tmout = 10000;
478 
479 	/* Wait up to 10ms for the character(s) to be sent. */
480 	do {
481 		status = vt8500_read(port, VT8500_URFIDX);
482 
483 		if (--tmout == 0)
484 			break;
485 		udelay(1);
486 	} while (status & 0x10);
487 }
488 
489 static void vt8500_console_putchar(struct uart_port *port, int c)
490 {
491 	wait_for_xmitr(port);
492 	writeb(c, port->membase + VT8500_TXFIFO);
493 }
494 
495 static void vt8500_console_write(struct console *co, const char *s,
496 			      unsigned int count)
497 {
498 	struct vt8500_port *vt8500_port = vt8500_uart_ports[co->index];
499 	unsigned long ier;
500 
501 	BUG_ON(co->index < 0 || co->index >= vt8500_uart_driver.nr);
502 
503 	ier = vt8500_read(&vt8500_port->uart, VT8500_URIER);
504 	vt8500_write(&vt8500_port->uart, VT8500_URIER, 0);
505 
506 	uart_console_write(&vt8500_port->uart, s, count,
507 			   vt8500_console_putchar);
508 
509 	/*
510 	 *	Finally, wait for transmitter to become empty
511 	 *	and switch back to FIFO
512 	 */
513 	wait_for_xmitr(&vt8500_port->uart);
514 	vt8500_write(&vt8500_port->uart, VT8500_URIER, ier);
515 }
516 
517 static int __init vt8500_console_setup(struct console *co, char *options)
518 {
519 	struct vt8500_port *vt8500_port;
520 	int baud = 9600;
521 	int bits = 8;
522 	int parity = 'n';
523 	int flow = 'n';
524 
525 	if (unlikely(co->index >= vt8500_uart_driver.nr || co->index < 0))
526 		return -ENXIO;
527 
528 	vt8500_port = vt8500_uart_ports[co->index];
529 
530 	if (!vt8500_port)
531 		return -ENODEV;
532 
533 	if (options)
534 		uart_parse_options(options, &baud, &parity, &bits, &flow);
535 
536 	return uart_set_options(&vt8500_port->uart,
537 				 co, baud, parity, bits, flow);
538 }
539 
540 static struct console vt8500_console = {
541 	.name = "ttyWMT",
542 	.write = vt8500_console_write,
543 	.device = uart_console_device,
544 	.setup = vt8500_console_setup,
545 	.flags = CON_PRINTBUFFER,
546 	.index = -1,
547 	.data = &vt8500_uart_driver,
548 };
549 
550 #define VT8500_CONSOLE	(&vt8500_console)
551 
552 #else
553 #define VT8500_CONSOLE	NULL
554 #endif
555 
556 #ifdef CONFIG_CONSOLE_POLL
557 static int vt8500_get_poll_char(struct uart_port *port)
558 {
559 	unsigned int status = vt8500_read(port, VT8500_URFIDX);
560 
561 	if (!(status & 0x1f00))
562 		return NO_POLL_CHAR;
563 
564 	return vt8500_read(port, VT8500_RXFIFO) & 0xff;
565 }
566 
567 static void vt8500_put_poll_char(struct uart_port *port, unsigned char c)
568 {
569 	unsigned int status, tmout = 10000;
570 
571 	do {
572 		status = vt8500_read(port, VT8500_URFIDX);
573 
574 		if (--tmout == 0)
575 			break;
576 		udelay(1);
577 	} while (status & 0x10);
578 
579 	vt8500_write(port, c, VT8500_TXFIFO);
580 }
581 #endif
582 
583 static const struct uart_ops vt8500_uart_pops = {
584 	.tx_empty	= vt8500_tx_empty,
585 	.set_mctrl	= vt8500_set_mctrl,
586 	.get_mctrl	= vt8500_get_mctrl,
587 	.stop_tx	= vt8500_stop_tx,
588 	.start_tx	= vt8500_start_tx,
589 	.stop_rx	= vt8500_stop_rx,
590 	.enable_ms	= vt8500_enable_ms,
591 	.break_ctl	= vt8500_break_ctl,
592 	.startup	= vt8500_startup,
593 	.shutdown	= vt8500_shutdown,
594 	.set_termios	= vt8500_set_termios,
595 	.type		= vt8500_type,
596 	.release_port	= vt8500_release_port,
597 	.request_port	= vt8500_request_port,
598 	.config_port	= vt8500_config_port,
599 	.verify_port	= vt8500_verify_port,
600 #ifdef CONFIG_CONSOLE_POLL
601 	.poll_get_char	= vt8500_get_poll_char,
602 	.poll_put_char	= vt8500_put_poll_char,
603 #endif
604 };
605 
606 static struct uart_driver vt8500_uart_driver = {
607 	.owner		= THIS_MODULE,
608 	.driver_name	= "vt8500_serial",
609 	.dev_name	= "ttyWMT",
610 	.nr		= 6,
611 	.cons		= VT8500_CONSOLE,
612 };
613 
614 static unsigned int vt8500_flags; /* none required so far */
615 static unsigned int wm8880_flags = VT8500_HAS_SWRTSCTS_SWITCH;
616 
617 static const struct of_device_id wmt_dt_ids[] = {
618 	{ .compatible = "via,vt8500-uart", .data = &vt8500_flags},
619 	{ .compatible = "wm,wm8880-uart", .data = &wm8880_flags},
620 	{}
621 };
622 
623 static int vt8500_serial_probe(struct platform_device *pdev)
624 {
625 	struct vt8500_port *vt8500_port;
626 	struct resource *mmres, *irqres;
627 	struct device_node *np = pdev->dev.of_node;
628 	const struct of_device_id *match;
629 	const unsigned int *flags;
630 	int ret;
631 	int port;
632 
633 	match = of_match_device(wmt_dt_ids, &pdev->dev);
634 	if (!match)
635 		return -EINVAL;
636 
637 	flags = match->data;
638 
639 	mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
640 	irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
641 	if (!mmres || !irqres)
642 		return -ENODEV;
643 
644 	if (np) {
645 		port = of_alias_get_id(np, "serial");
646 		if (port >= VT8500_MAX_PORTS)
647 			port = -1;
648 	} else {
649 		port = -1;
650 	}
651 
652 	if (port < 0) {
653 		/* calculate the port id */
654 		port = find_first_zero_bit(vt8500_ports_in_use,
655 					   VT8500_MAX_PORTS);
656 	}
657 
658 	if (port >= VT8500_MAX_PORTS)
659 		return -ENODEV;
660 
661 	/* reserve the port id */
662 	if (test_and_set_bit(port, vt8500_ports_in_use)) {
663 		/* port already in use - shouldn't really happen */
664 		return -EBUSY;
665 	}
666 
667 	vt8500_port = devm_kzalloc(&pdev->dev, sizeof(struct vt8500_port),
668 				   GFP_KERNEL);
669 	if (!vt8500_port)
670 		return -ENOMEM;
671 
672 	vt8500_port->uart.membase = devm_ioremap_resource(&pdev->dev, mmres);
673 	if (IS_ERR(vt8500_port->uart.membase))
674 		return PTR_ERR(vt8500_port->uart.membase);
675 
676 	vt8500_port->clk = of_clk_get(pdev->dev.of_node, 0);
677 	if (IS_ERR(vt8500_port->clk)) {
678 		dev_err(&pdev->dev, "failed to get clock\n");
679 		return  -EINVAL;
680 	}
681 
682 	ret = clk_prepare_enable(vt8500_port->clk);
683 	if (ret) {
684 		dev_err(&pdev->dev, "failed to enable clock\n");
685 		return ret;
686 	}
687 
688 	vt8500_port->vt8500_uart_flags = *flags;
689 	vt8500_port->clk_predivisor = DIV_ROUND_CLOSEST(
690 					clk_get_rate(vt8500_port->clk),
691 					VT8500_RECOMMENDED_CLK
692 				      );
693 	vt8500_port->uart.type = PORT_VT8500;
694 	vt8500_port->uart.iotype = UPIO_MEM;
695 	vt8500_port->uart.mapbase = mmres->start;
696 	vt8500_port->uart.irq = irqres->start;
697 	vt8500_port->uart.fifosize = 16;
698 	vt8500_port->uart.ops = &vt8500_uart_pops;
699 	vt8500_port->uart.line = port;
700 	vt8500_port->uart.dev = &pdev->dev;
701 	vt8500_port->uart.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
702 	vt8500_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_VT8500_CONSOLE);
703 
704 	/* Serial core uses the magic "16" everywhere - adjust for it */
705 	vt8500_port->uart.uartclk = 16 * clk_get_rate(vt8500_port->clk) /
706 					vt8500_port->clk_predivisor /
707 					VT8500_OVERSAMPLING_DIVISOR;
708 
709 	snprintf(vt8500_port->name, sizeof(vt8500_port->name),
710 		 "VT8500 UART%d", pdev->id);
711 
712 	vt8500_uart_ports[port] = vt8500_port;
713 
714 	uart_add_one_port(&vt8500_uart_driver, &vt8500_port->uart);
715 
716 	platform_set_drvdata(pdev, vt8500_port);
717 
718 	return 0;
719 }
720 
721 static struct platform_driver vt8500_platform_driver = {
722 	.probe  = vt8500_serial_probe,
723 	.driver = {
724 		.name = "vt8500_serial",
725 		.of_match_table = wmt_dt_ids,
726 		.suppress_bind_attrs = true,
727 	},
728 };
729 
730 static int __init vt8500_serial_init(void)
731 {
732 	int ret;
733 
734 	ret = uart_register_driver(&vt8500_uart_driver);
735 	if (unlikely(ret))
736 		return ret;
737 
738 	ret = platform_driver_register(&vt8500_platform_driver);
739 
740 	if (unlikely(ret))
741 		uart_unregister_driver(&vt8500_uart_driver);
742 
743 	return ret;
744 }
745 device_initcall(vt8500_serial_init);
746