1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * r8169.c: RealTek 8169/8168/8101 ethernet driver. 4 * 5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> 6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> 7 * Copyright (c) a lot of people too. Please respect their work. 8 * 9 * See MAINTAINERS file for support contact information. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/pci.h> 14 #include <linux/netdevice.h> 15 #include <linux/etherdevice.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/ethtool.h> 19 #include <linux/phy.h> 20 #include <linux/if_vlan.h> 21 #include <linux/in.h> 22 #include <linux/io.h> 23 #include <linux/ip.h> 24 #include <linux/tcp.h> 25 #include <linux/interrupt.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/bitfield.h> 29 #include <linux/prefetch.h> 30 #include <linux/ipv6.h> 31 #include <net/ip6_checksum.h> 32 33 #include "r8169.h" 34 #include "r8169_firmware.h" 35 36 #define MODULENAME "r8169" 37 38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" 39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" 40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" 41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" 42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" 43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw" 44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw" 45 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" 46 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw" 47 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw" 48 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw" 49 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw" 50 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw" 51 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw" 52 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw" 53 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw" 54 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw" 55 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw" 56 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw" 57 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw" 58 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" 59 60 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 61 The RTL chips use a 64 element hash table based on the Ethernet CRC. */ 62 #define MC_FILTER_LIMIT 32 63 64 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ 65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ 66 67 #define R8169_REGS_SIZE 256 68 #define R8169_RX_BUF_SIZE (SZ_16K - 1) 69 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ 70 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */ 71 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) 72 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) 73 74 #define OCP_STD_PHY_BASE 0xa400 75 76 #define RTL_CFG_NO_GBIT 1 77 78 /* write/read MMIO register */ 79 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg)) 80 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg)) 81 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg)) 82 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) 83 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg)) 84 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg)) 85 86 #define JUMBO_4K (4 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 87 #define JUMBO_6K (6 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 88 #define JUMBO_7K (7 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 89 #define JUMBO_9K (9 * SZ_1K - VLAN_ETH_HLEN - ETH_FCS_LEN) 90 91 static const struct { 92 const char *name; 93 const char *fw_name; 94 } rtl_chip_infos[] = { 95 /* PCI devices. */ 96 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" }, 97 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" }, 98 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" }, 99 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" }, 100 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" }, 101 /* PCI-E devices. */ 102 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" }, 103 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" }, 104 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" }, 105 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" }, 106 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" }, 107 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" }, 108 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" }, 109 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" }, 110 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" }, 111 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" }, 112 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" }, 113 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" }, 114 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" }, 115 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" }, 116 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" }, 117 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" }, 118 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" }, 119 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" }, 120 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1}, 121 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2}, 122 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" }, 123 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" }, 124 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1}, 125 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1}, 126 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" }, 127 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1}, 128 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2}, 129 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3}, 130 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1}, 131 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2}, 132 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 }, 133 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 }, 134 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1}, 135 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2}, 136 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" }, 137 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3}, 138 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2}, 139 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 }, 140 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1}, 141 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2}, 142 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1}, 143 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2}, 144 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" }, 145 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" }, 146 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" }, 147 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3}, 148 [RTL_GIGA_MAC_VER_60] = {"RTL8125" }, 149 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3}, 150 }; 151 152 static const struct pci_device_id rtl8169_pci_tbl[] = { 153 { PCI_VDEVICE(REALTEK, 0x2502) }, 154 { PCI_VDEVICE(REALTEK, 0x2600) }, 155 { PCI_VDEVICE(REALTEK, 0x8129) }, 156 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT }, 157 { PCI_VDEVICE(REALTEK, 0x8161) }, 158 { PCI_VDEVICE(REALTEK, 0x8167) }, 159 { PCI_VDEVICE(REALTEK, 0x8168) }, 160 { PCI_VDEVICE(NCUBE, 0x8168) }, 161 { PCI_VDEVICE(REALTEK, 0x8169) }, 162 { PCI_VENDOR_ID_DLINK, 0x4300, 163 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 }, 164 { PCI_VDEVICE(DLINK, 0x4300) }, 165 { PCI_VDEVICE(DLINK, 0x4302) }, 166 { PCI_VDEVICE(AT, 0xc107) }, 167 { PCI_VDEVICE(USR, 0x0116) }, 168 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 }, 169 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 }, 170 { PCI_VDEVICE(REALTEK, 0x8125) }, 171 { PCI_VDEVICE(REALTEK, 0x3000) }, 172 {} 173 }; 174 175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); 176 177 enum rtl_registers { 178 MAC0 = 0, /* Ethernet hardware address. */ 179 MAC4 = 4, 180 MAR0 = 8, /* Multicast filter. */ 181 CounterAddrLow = 0x10, 182 CounterAddrHigh = 0x14, 183 TxDescStartAddrLow = 0x20, 184 TxDescStartAddrHigh = 0x24, 185 TxHDescStartAddrLow = 0x28, 186 TxHDescStartAddrHigh = 0x2c, 187 FLASH = 0x30, 188 ERSR = 0x36, 189 ChipCmd = 0x37, 190 TxPoll = 0x38, 191 IntrMask = 0x3c, 192 IntrStatus = 0x3e, 193 194 TxConfig = 0x40, 195 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ 196 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ 197 198 RxConfig = 0x44, 199 #define RX128_INT_EN (1 << 15) /* 8111c and later */ 200 #define RX_MULTI_EN (1 << 14) /* 8111c only */ 201 #define RXCFG_FIFO_SHIFT 13 202 /* No threshold before first PCI xfer */ 203 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) 204 #define RX_EARLY_OFF (1 << 11) 205 #define RXCFG_DMA_SHIFT 8 206 /* Unlimited maximum PCI burst. */ 207 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) 208 209 Cfg9346 = 0x50, 210 Config0 = 0x51, 211 Config1 = 0x52, 212 Config2 = 0x53, 213 #define PME_SIGNAL (1 << 5) /* 8168c and later */ 214 215 Config3 = 0x54, 216 Config4 = 0x55, 217 Config5 = 0x56, 218 PHYAR = 0x60, 219 PHYstatus = 0x6c, 220 RxMaxSize = 0xda, 221 CPlusCmd = 0xe0, 222 IntrMitigate = 0xe2, 223 224 #define RTL_COALESCE_TX_USECS GENMASK(15, 12) 225 #define RTL_COALESCE_TX_FRAMES GENMASK(11, 8) 226 #define RTL_COALESCE_RX_USECS GENMASK(7, 4) 227 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0) 228 229 #define RTL_COALESCE_T_MAX 0x0fU 230 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_T_MAX * 4) 231 232 RxDescAddrLow = 0xe4, 233 RxDescAddrHigh = 0xe8, 234 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ 235 236 #define NoEarlyTx 0x3f /* Max value : no early transmit. */ 237 238 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ 239 240 #define TxPacketMax (8064 >> 7) 241 #define EarlySize 0x27 242 243 FuncEvent = 0xf0, 244 FuncEventMask = 0xf4, 245 FuncPresetState = 0xf8, 246 IBCR0 = 0xf8, 247 IBCR2 = 0xf9, 248 IBIMR0 = 0xfa, 249 IBISR0 = 0xfb, 250 FuncForceEvent = 0xfc, 251 }; 252 253 enum rtl8168_8101_registers { 254 CSIDR = 0x64, 255 CSIAR = 0x68, 256 #define CSIAR_FLAG 0x80000000 257 #define CSIAR_WRITE_CMD 0x80000000 258 #define CSIAR_BYTE_ENABLE 0x0000f000 259 #define CSIAR_ADDR_MASK 0x00000fff 260 PMCH = 0x6f, 261 EPHYAR = 0x80, 262 #define EPHYAR_FLAG 0x80000000 263 #define EPHYAR_WRITE_CMD 0x80000000 264 #define EPHYAR_REG_MASK 0x1f 265 #define EPHYAR_REG_SHIFT 16 266 #define EPHYAR_DATA_MASK 0xffff 267 DLLPR = 0xd0, 268 #define PFM_EN (1 << 6) 269 #define TX_10M_PS_EN (1 << 7) 270 DBG_REG = 0xd1, 271 #define FIX_NAK_1 (1 << 4) 272 #define FIX_NAK_2 (1 << 3) 273 TWSI = 0xd2, 274 MCU = 0xd3, 275 #define NOW_IS_OOB (1 << 7) 276 #define TX_EMPTY (1 << 5) 277 #define RX_EMPTY (1 << 4) 278 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY) 279 #define EN_NDP (1 << 3) 280 #define EN_OOB_RESET (1 << 2) 281 #define LINK_LIST_RDY (1 << 1) 282 EFUSEAR = 0xdc, 283 #define EFUSEAR_FLAG 0x80000000 284 #define EFUSEAR_WRITE_CMD 0x80000000 285 #define EFUSEAR_READ_CMD 0x00000000 286 #define EFUSEAR_REG_MASK 0x03ff 287 #define EFUSEAR_REG_SHIFT 8 288 #define EFUSEAR_DATA_MASK 0xff 289 MISC_1 = 0xf2, 290 #define PFM_D3COLD_EN (1 << 6) 291 }; 292 293 enum rtl8168_registers { 294 LED_FREQ = 0x1a, 295 EEE_LED = 0x1b, 296 ERIDR = 0x70, 297 ERIAR = 0x74, 298 #define ERIAR_FLAG 0x80000000 299 #define ERIAR_WRITE_CMD 0x80000000 300 #define ERIAR_READ_CMD 0x00000000 301 #define ERIAR_ADDR_BYTE_ALIGN 4 302 #define ERIAR_TYPE_SHIFT 16 303 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) 304 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) 305 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) 306 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT) 307 #define ERIAR_MASK_SHIFT 12 308 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) 309 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) 310 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT) 311 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT) 312 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) 313 EPHY_RXER_NUM = 0x7c, 314 OCPDR = 0xb0, /* OCP GPHY access */ 315 #define OCPDR_WRITE_CMD 0x80000000 316 #define OCPDR_READ_CMD 0x00000000 317 #define OCPDR_REG_MASK 0x7f 318 #define OCPDR_GPHY_REG_SHIFT 16 319 #define OCPDR_DATA_MASK 0xffff 320 OCPAR = 0xb4, 321 #define OCPAR_FLAG 0x80000000 322 #define OCPAR_GPHY_WRITE_CMD 0x8000f060 323 #define OCPAR_GPHY_READ_CMD 0x0000f060 324 GPHY_OCP = 0xb8, 325 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ 326 MISC = 0xf0, /* 8168e only. */ 327 #define TXPLA_RST (1 << 29) 328 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */ 329 #define PWM_EN (1 << 22) 330 #define RXDV_GATED_EN (1 << 19) 331 #define EARLY_TALLY_EN (1 << 16) 332 }; 333 334 enum rtl8125_registers { 335 IntrMask_8125 = 0x38, 336 IntrStatus_8125 = 0x3c, 337 TxPoll_8125 = 0x90, 338 MAC0_BKP = 0x19e0, 339 }; 340 341 #define RX_VLAN_INNER_8125 BIT(22) 342 #define RX_VLAN_OUTER_8125 BIT(23) 343 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125) 344 345 #define RX_FETCH_DFLT_8125 (8 << 27) 346 347 enum rtl_register_content { 348 /* InterruptStatusBits */ 349 SYSErr = 0x8000, 350 PCSTimeout = 0x4000, 351 SWInt = 0x0100, 352 TxDescUnavail = 0x0080, 353 RxFIFOOver = 0x0040, 354 LinkChg = 0x0020, 355 RxOverflow = 0x0010, 356 TxErr = 0x0008, 357 TxOK = 0x0004, 358 RxErr = 0x0002, 359 RxOK = 0x0001, 360 361 /* RxStatusDesc */ 362 RxRWT = (1 << 22), 363 RxRES = (1 << 21), 364 RxRUNT = (1 << 20), 365 RxCRC = (1 << 19), 366 367 /* ChipCmdBits */ 368 StopReq = 0x80, 369 CmdReset = 0x10, 370 CmdRxEnb = 0x08, 371 CmdTxEnb = 0x04, 372 RxBufEmpty = 0x01, 373 374 /* TXPoll register p.5 */ 375 HPQ = 0x80, /* Poll cmd on the high prio queue */ 376 NPQ = 0x40, /* Poll cmd on the low prio queue */ 377 FSWInt = 0x01, /* Forced software interrupt */ 378 379 /* Cfg9346Bits */ 380 Cfg9346_Lock = 0x00, 381 Cfg9346_Unlock = 0xc0, 382 383 /* rx_mode_bits */ 384 AcceptErr = 0x20, 385 AcceptRunt = 0x10, 386 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30 387 AcceptBroadcast = 0x08, 388 AcceptMulticast = 0x04, 389 AcceptMyPhys = 0x02, 390 AcceptAllPhys = 0x01, 391 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f 392 #define RX_CONFIG_ACCEPT_MASK 0x3f 393 394 /* TxConfigBits */ 395 TxInterFrameGapShift = 24, 396 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ 397 398 /* Config1 register p.24 */ 399 LEDS1 = (1 << 7), 400 LEDS0 = (1 << 6), 401 Speed_down = (1 << 4), 402 MEMMAP = (1 << 3), 403 IOMAP = (1 << 2), 404 VPD = (1 << 1), 405 PMEnable = (1 << 0), /* Power Management Enable */ 406 407 /* Config2 register p. 25 */ 408 ClkReqEn = (1 << 7), /* Clock Request Enable */ 409 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */ 410 PCI_Clock_66MHz = 0x01, 411 PCI_Clock_33MHz = 0x00, 412 413 /* Config3 register p.25 */ 414 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ 415 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ 416 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */ 417 Rdy_to_L23 = (1 << 1), /* L23 Enable */ 418 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ 419 420 /* Config4 register */ 421 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */ 422 423 /* Config5 register p.27 */ 424 BWF = (1 << 6), /* Accept Broadcast wakeup frame */ 425 MWF = (1 << 5), /* Accept Multicast wakeup frame */ 426 UWF = (1 << 4), /* Accept Unicast wakeup frame */ 427 Spi_en = (1 << 3), 428 LanWake = (1 << 1), /* LanWake enable/disable */ 429 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ 430 ASPM_en = (1 << 0), /* ASPM enable */ 431 432 /* CPlusCmd p.31 */ 433 EnableBist = (1 << 15), // 8168 8101 434 Mac_dbgo_oe = (1 << 14), // 8168 8101 435 EnAnaPLL = (1 << 14), // 8169 436 Normal_mode = (1 << 13), // unused 437 Force_half_dup = (1 << 12), // 8168 8101 438 Force_rxflow_en = (1 << 11), // 8168 8101 439 Force_txflow_en = (1 << 10), // 8168 8101 440 Cxpl_dbg_sel = (1 << 9), // 8168 8101 441 ASF = (1 << 8), // 8168 8101 442 PktCntrDisable = (1 << 7), // 8168 8101 443 Mac_dbgo_sel = 0x001c, // 8168 444 RxVlan = (1 << 6), 445 RxChkSum = (1 << 5), 446 PCIDAC = (1 << 4), 447 PCIMulRW = (1 << 3), 448 #define INTT_MASK GENMASK(1, 0) 449 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK) 450 451 /* rtl8169_PHYstatus */ 452 TBI_Enable = 0x80, 453 TxFlowCtrl = 0x40, 454 RxFlowCtrl = 0x20, 455 _1000bpsF = 0x10, 456 _100bps = 0x08, 457 _10bps = 0x04, 458 LinkStatus = 0x02, 459 FullDup = 0x01, 460 461 /* ResetCounterCommand */ 462 CounterReset = 0x1, 463 464 /* DumpCounterCommand */ 465 CounterDump = 0x8, 466 467 /* magic enable v2 */ 468 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */ 469 }; 470 471 enum rtl_desc_bit { 472 /* First doubleword. */ 473 DescOwn = (1 << 31), /* Descriptor is owned by NIC */ 474 RingEnd = (1 << 30), /* End of descriptor ring */ 475 FirstFrag = (1 << 29), /* First segment of a packet */ 476 LastFrag = (1 << 28), /* Final segment of a packet */ 477 }; 478 479 /* Generic case. */ 480 enum rtl_tx_desc_bit { 481 /* First doubleword. */ 482 TD_LSO = (1 << 27), /* Large Send Offload */ 483 #define TD_MSS_MAX 0x07ffu /* MSS value */ 484 485 /* Second doubleword. */ 486 TxVlanTag = (1 << 17), /* Add VLAN tag */ 487 }; 488 489 /* 8169, 8168b and 810x except 8102e. */ 490 enum rtl_tx_desc_bit_0 { 491 /* First doubleword. */ 492 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ 493 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ 494 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ 495 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ 496 }; 497 498 /* 8102e, 8168c and beyond. */ 499 enum rtl_tx_desc_bit_1 { 500 /* First doubleword. */ 501 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */ 502 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */ 503 #define GTTCPHO_SHIFT 18 504 #define GTTCPHO_MAX 0x7f 505 506 /* Second doubleword. */ 507 #define TCPHO_SHIFT 18 508 #define TCPHO_MAX 0x3ff 509 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ 510 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */ 511 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */ 512 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ 513 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ 514 }; 515 516 enum rtl_rx_desc_bit { 517 /* Rx private */ 518 PID1 = (1 << 18), /* Protocol ID bit 1/2 */ 519 PID0 = (1 << 17), /* Protocol ID bit 0/2 */ 520 521 #define RxProtoUDP (PID1) 522 #define RxProtoTCP (PID0) 523 #define RxProtoIP (PID1 | PID0) 524 #define RxProtoMask RxProtoIP 525 526 IPFail = (1 << 16), /* IP checksum failed */ 527 UDPFail = (1 << 15), /* UDP/IP checksum failed */ 528 TCPFail = (1 << 14), /* TCP/IP checksum failed */ 529 RxVlanTag = (1 << 16), /* VLAN tag available */ 530 }; 531 532 #define RsvdMask 0x3fffc000 533 534 #define RTL_GSO_MAX_SIZE_V1 32000 535 #define RTL_GSO_MAX_SEGS_V1 24 536 #define RTL_GSO_MAX_SIZE_V2 64000 537 #define RTL_GSO_MAX_SEGS_V2 64 538 539 struct TxDesc { 540 __le32 opts1; 541 __le32 opts2; 542 __le64 addr; 543 }; 544 545 struct RxDesc { 546 __le32 opts1; 547 __le32 opts2; 548 __le64 addr; 549 }; 550 551 struct ring_info { 552 struct sk_buff *skb; 553 u32 len; 554 }; 555 556 struct rtl8169_counters { 557 __le64 tx_packets; 558 __le64 rx_packets; 559 __le64 tx_errors; 560 __le32 rx_errors; 561 __le16 rx_missed; 562 __le16 align_errors; 563 __le32 tx_one_collision; 564 __le32 tx_multi_collision; 565 __le64 rx_unicast; 566 __le64 rx_broadcast; 567 __le32 rx_multicast; 568 __le16 tx_aborted; 569 __le16 tx_underun; 570 }; 571 572 struct rtl8169_tc_offsets { 573 bool inited; 574 __le64 tx_errors; 575 __le32 tx_multi_collision; 576 __le16 tx_aborted; 577 __le16 rx_missed; 578 }; 579 580 enum rtl_flag { 581 RTL_FLAG_TASK_ENABLED = 0, 582 RTL_FLAG_TASK_RESET_PENDING, 583 RTL_FLAG_MAX 584 }; 585 586 struct rtl8169_stats { 587 u64 packets; 588 u64 bytes; 589 struct u64_stats_sync syncp; 590 }; 591 592 struct rtl8169_private { 593 void __iomem *mmio_addr; /* memory map physical address */ 594 struct pci_dev *pci_dev; 595 struct net_device *dev; 596 struct phy_device *phydev; 597 struct napi_struct napi; 598 enum mac_version mac_version; 599 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ 600 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ 601 u32 dirty_tx; 602 struct rtl8169_stats rx_stats; 603 struct rtl8169_stats tx_stats; 604 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ 605 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ 606 dma_addr_t TxPhyAddr; 607 dma_addr_t RxPhyAddr; 608 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ 609 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ 610 u16 cp_cmd; 611 u32 irq_mask; 612 struct clk *clk; 613 614 struct { 615 DECLARE_BITMAP(flags, RTL_FLAG_MAX); 616 struct mutex mutex; 617 struct work_struct work; 618 } wk; 619 620 unsigned irq_enabled:1; 621 unsigned supports_gmii:1; 622 unsigned aspm_manageable:1; 623 dma_addr_t counters_phys_addr; 624 struct rtl8169_counters *counters; 625 struct rtl8169_tc_offsets tc_offset; 626 u32 saved_wolopts; 627 int eee_adv; 628 629 const char *fw_name; 630 struct rtl_fw *rtl_fw; 631 632 u32 ocp_base; 633 }; 634 635 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp); 636 637 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); 638 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); 639 MODULE_SOFTDEP("pre: realtek"); 640 MODULE_LICENSE("GPL"); 641 MODULE_FIRMWARE(FIRMWARE_8168D_1); 642 MODULE_FIRMWARE(FIRMWARE_8168D_2); 643 MODULE_FIRMWARE(FIRMWARE_8168E_1); 644 MODULE_FIRMWARE(FIRMWARE_8168E_2); 645 MODULE_FIRMWARE(FIRMWARE_8168E_3); 646 MODULE_FIRMWARE(FIRMWARE_8105E_1); 647 MODULE_FIRMWARE(FIRMWARE_8168F_1); 648 MODULE_FIRMWARE(FIRMWARE_8168F_2); 649 MODULE_FIRMWARE(FIRMWARE_8402_1); 650 MODULE_FIRMWARE(FIRMWARE_8411_1); 651 MODULE_FIRMWARE(FIRMWARE_8411_2); 652 MODULE_FIRMWARE(FIRMWARE_8106E_1); 653 MODULE_FIRMWARE(FIRMWARE_8106E_2); 654 MODULE_FIRMWARE(FIRMWARE_8168G_2); 655 MODULE_FIRMWARE(FIRMWARE_8168G_3); 656 MODULE_FIRMWARE(FIRMWARE_8168H_1); 657 MODULE_FIRMWARE(FIRMWARE_8168H_2); 658 MODULE_FIRMWARE(FIRMWARE_8168FP_3); 659 MODULE_FIRMWARE(FIRMWARE_8107E_1); 660 MODULE_FIRMWARE(FIRMWARE_8107E_2); 661 MODULE_FIRMWARE(FIRMWARE_8125A_3); 662 663 static inline struct device *tp_to_dev(struct rtl8169_private *tp) 664 { 665 return &tp->pci_dev->dev; 666 } 667 668 static void rtl_lock_work(struct rtl8169_private *tp) 669 { 670 mutex_lock(&tp->wk.mutex); 671 } 672 673 static void rtl_unlock_work(struct rtl8169_private *tp) 674 { 675 mutex_unlock(&tp->wk.mutex); 676 } 677 678 static void rtl_lock_config_regs(struct rtl8169_private *tp) 679 { 680 RTL_W8(tp, Cfg9346, Cfg9346_Lock); 681 } 682 683 static void rtl_unlock_config_regs(struct rtl8169_private *tp) 684 { 685 RTL_W8(tp, Cfg9346, Cfg9346_Unlock); 686 } 687 688 static void rtl_pci_commit(struct rtl8169_private *tp) 689 { 690 /* Read an arbitrary register to commit a preceding PCI write */ 691 RTL_R8(tp, ChipCmd); 692 } 693 694 static bool rtl_is_8125(struct rtl8169_private *tp) 695 { 696 return tp->mac_version >= RTL_GIGA_MAC_VER_60; 697 } 698 699 static bool rtl_is_8168evl_up(struct rtl8169_private *tp) 700 { 701 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 702 tp->mac_version != RTL_GIGA_MAC_VER_39 && 703 tp->mac_version <= RTL_GIGA_MAC_VER_52; 704 } 705 706 static bool rtl_supports_eee(struct rtl8169_private *tp) 707 { 708 return tp->mac_version >= RTL_GIGA_MAC_VER_34 && 709 tp->mac_version != RTL_GIGA_MAC_VER_37 && 710 tp->mac_version != RTL_GIGA_MAC_VER_39; 711 } 712 713 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg) 714 { 715 int i; 716 717 for (i = 0; i < ETH_ALEN; i++) 718 mac[i] = RTL_R8(tp, reg + i); 719 } 720 721 struct rtl_cond { 722 bool (*check)(struct rtl8169_private *); 723 const char *msg; 724 }; 725 726 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c, 727 unsigned long usecs, int n, bool high) 728 { 729 int i; 730 731 for (i = 0; i < n; i++) { 732 if (c->check(tp) == high) 733 return true; 734 fsleep(usecs); 735 } 736 737 if (net_ratelimit()) 738 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n", 739 c->msg, !high, n, usecs); 740 return false; 741 } 742 743 static bool rtl_loop_wait_high(struct rtl8169_private *tp, 744 const struct rtl_cond *c, 745 unsigned long d, int n) 746 { 747 return rtl_loop_wait(tp, c, d, n, true); 748 } 749 750 static bool rtl_loop_wait_low(struct rtl8169_private *tp, 751 const struct rtl_cond *c, 752 unsigned long d, int n) 753 { 754 return rtl_loop_wait(tp, c, d, n, false); 755 } 756 757 #define DECLARE_RTL_COND(name) \ 758 static bool name ## _check(struct rtl8169_private *); \ 759 \ 760 static const struct rtl_cond name = { \ 761 .check = name ## _check, \ 762 .msg = #name \ 763 }; \ 764 \ 765 static bool name ## _check(struct rtl8169_private *tp) 766 767 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg) 768 { 769 if (reg & 0xffff0001) { 770 if (net_ratelimit()) 771 netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg); 772 return true; 773 } 774 return false; 775 } 776 777 DECLARE_RTL_COND(rtl_ocp_gphy_cond) 778 { 779 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG; 780 } 781 782 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 783 { 784 if (rtl_ocp_reg_failure(tp, reg)) 785 return; 786 787 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data); 788 789 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10); 790 } 791 792 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg) 793 { 794 if (rtl_ocp_reg_failure(tp, reg)) 795 return 0; 796 797 RTL_W32(tp, GPHY_OCP, reg << 15); 798 799 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ? 800 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; 801 } 802 803 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data) 804 { 805 if (rtl_ocp_reg_failure(tp, reg)) 806 return; 807 808 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data); 809 } 810 811 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg) 812 { 813 if (rtl_ocp_reg_failure(tp, reg)) 814 return 0; 815 816 RTL_W32(tp, OCPDR, reg << 15); 817 818 return RTL_R32(tp, OCPDR); 819 } 820 821 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask, 822 u16 set) 823 { 824 u16 data = r8168_mac_ocp_read(tp, reg); 825 826 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set); 827 } 828 829 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value) 830 { 831 if (reg == 0x1f) { 832 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE; 833 return; 834 } 835 836 if (tp->ocp_base != OCP_STD_PHY_BASE) 837 reg -= 0x10; 838 839 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value); 840 } 841 842 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg) 843 { 844 if (reg == 0x1f) 845 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; 846 847 if (tp->ocp_base != OCP_STD_PHY_BASE) 848 reg -= 0x10; 849 850 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2); 851 } 852 853 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value) 854 { 855 if (reg == 0x1f) { 856 tp->ocp_base = value << 4; 857 return; 858 } 859 860 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value); 861 } 862 863 static int mac_mcu_read(struct rtl8169_private *tp, int reg) 864 { 865 return r8168_mac_ocp_read(tp, tp->ocp_base + reg); 866 } 867 868 DECLARE_RTL_COND(rtl_phyar_cond) 869 { 870 return RTL_R32(tp, PHYAR) & 0x80000000; 871 } 872 873 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value) 874 { 875 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); 876 877 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20); 878 /* 879 * According to hardware specs a 20us delay is required after write 880 * complete indication, but before sending next command. 881 */ 882 udelay(20); 883 } 884 885 static int r8169_mdio_read(struct rtl8169_private *tp, int reg) 886 { 887 int value; 888 889 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); 890 891 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ? 892 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; 893 894 /* 895 * According to hardware specs a 20us delay is required after read 896 * complete indication, but before sending next command. 897 */ 898 udelay(20); 899 900 return value; 901 } 902 903 DECLARE_RTL_COND(rtl_ocpar_cond) 904 { 905 return RTL_R32(tp, OCPAR) & OCPAR_FLAG; 906 } 907 908 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data) 909 { 910 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); 911 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD); 912 RTL_W32(tp, EPHY_RXER_NUM, 0); 913 914 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100); 915 } 916 917 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value) 918 { 919 r8168dp_1_mdio_access(tp, reg, 920 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK)); 921 } 922 923 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg) 924 { 925 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD); 926 927 mdelay(1); 928 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD); 929 RTL_W32(tp, EPHY_RXER_NUM, 0); 930 931 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ? 932 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT; 933 } 934 935 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 936 937 static void r8168dp_2_mdio_start(struct rtl8169_private *tp) 938 { 939 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); 940 } 941 942 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp) 943 { 944 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); 945 } 946 947 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value) 948 { 949 r8168dp_2_mdio_start(tp); 950 951 r8169_mdio_write(tp, reg, value); 952 953 r8168dp_2_mdio_stop(tp); 954 } 955 956 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg) 957 { 958 int value; 959 960 /* Work around issue with chip reporting wrong PHY ID */ 961 if (reg == MII_PHYSID2) 962 return 0xc912; 963 964 r8168dp_2_mdio_start(tp); 965 966 value = r8169_mdio_read(tp, reg); 967 968 r8168dp_2_mdio_stop(tp); 969 970 return value; 971 } 972 973 static void rtl_writephy(struct rtl8169_private *tp, int location, int val) 974 { 975 switch (tp->mac_version) { 976 case RTL_GIGA_MAC_VER_27: 977 r8168dp_1_mdio_write(tp, location, val); 978 break; 979 case RTL_GIGA_MAC_VER_28: 980 case RTL_GIGA_MAC_VER_31: 981 r8168dp_2_mdio_write(tp, location, val); 982 break; 983 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 984 r8168g_mdio_write(tp, location, val); 985 break; 986 default: 987 r8169_mdio_write(tp, location, val); 988 break; 989 } 990 } 991 992 static int rtl_readphy(struct rtl8169_private *tp, int location) 993 { 994 switch (tp->mac_version) { 995 case RTL_GIGA_MAC_VER_27: 996 return r8168dp_1_mdio_read(tp, location); 997 case RTL_GIGA_MAC_VER_28: 998 case RTL_GIGA_MAC_VER_31: 999 return r8168dp_2_mdio_read(tp, location); 1000 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 1001 return r8168g_mdio_read(tp, location); 1002 default: 1003 return r8169_mdio_read(tp, location); 1004 } 1005 } 1006 1007 DECLARE_RTL_COND(rtl_ephyar_cond) 1008 { 1009 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG; 1010 } 1011 1012 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value) 1013 { 1014 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | 1015 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1016 1017 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100); 1018 1019 udelay(10); 1020 } 1021 1022 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr) 1023 { 1024 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); 1025 1026 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ? 1027 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; 1028 } 1029 1030 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type) 1031 { 1032 /* based on RTL8168FP_OOBMAC_BASE in vendor driver */ 1033 if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB) 1034 *cmd |= 0x7f0 << 18; 1035 } 1036 1037 DECLARE_RTL_COND(rtl_eriar_cond) 1038 { 1039 return RTL_R32(tp, ERIAR) & ERIAR_FLAG; 1040 } 1041 1042 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1043 u32 val, int type) 1044 { 1045 u32 cmd = ERIAR_WRITE_CMD | type | mask | addr; 1046 1047 BUG_ON((addr & 3) || (mask == 0)); 1048 RTL_W32(tp, ERIDR, val); 1049 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1050 RTL_W32(tp, ERIAR, cmd); 1051 1052 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100); 1053 } 1054 1055 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 1056 u32 val) 1057 { 1058 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC); 1059 } 1060 1061 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 1062 { 1063 u32 cmd = ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr; 1064 1065 r8168fp_adjust_ocp_cmd(tp, &cmd, type); 1066 RTL_W32(tp, ERIAR, cmd); 1067 1068 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ? 1069 RTL_R32(tp, ERIDR) : ~0; 1070 } 1071 1072 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr) 1073 { 1074 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC); 1075 } 1076 1077 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m) 1078 { 1079 u32 val = rtl_eri_read(tp, addr); 1080 1081 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p); 1082 } 1083 1084 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p) 1085 { 1086 rtl_w0w1_eri(tp, addr, p, 0); 1087 } 1088 1089 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m) 1090 { 1091 rtl_w0w1_eri(tp, addr, 0, m); 1092 } 1093 1094 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg) 1095 { 1096 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); 1097 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ? 1098 RTL_R32(tp, OCPDR) : ~0; 1099 } 1100 1101 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg) 1102 { 1103 return _rtl_eri_read(tp, reg, ERIAR_OOB); 1104 } 1105 1106 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1107 u32 data) 1108 { 1109 RTL_W32(tp, OCPDR, data); 1110 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); 1111 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20); 1112 } 1113 1114 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 1115 u32 data) 1116 { 1117 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, 1118 data, ERIAR_OOB); 1119 } 1120 1121 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd) 1122 { 1123 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); 1124 1125 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); 1126 } 1127 1128 #define OOB_CMD_RESET 0x00 1129 #define OOB_CMD_DRIVER_START 0x05 1130 #define OOB_CMD_DRIVER_STOP 0x06 1131 1132 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) 1133 { 1134 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; 1135 } 1136 1137 DECLARE_RTL_COND(rtl_dp_ocp_read_cond) 1138 { 1139 u16 reg; 1140 1141 reg = rtl8168_get_ocp_reg(tp); 1142 1143 return r8168dp_ocp_read(tp, reg) & 0x00000800; 1144 } 1145 1146 DECLARE_RTL_COND(rtl_ep_ocp_read_cond) 1147 { 1148 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; 1149 } 1150 1151 DECLARE_RTL_COND(rtl_ocp_tx_cond) 1152 { 1153 return RTL_R8(tp, IBISR0) & 0x20; 1154 } 1155 1156 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp) 1157 { 1158 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); 1159 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000); 1160 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); 1161 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); 1162 } 1163 1164 static void rtl8168dp_driver_start(struct rtl8169_private *tp) 1165 { 1166 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START); 1167 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1168 } 1169 1170 static void rtl8168ep_driver_start(struct rtl8169_private *tp) 1171 { 1172 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); 1173 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1174 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1175 } 1176 1177 static void rtl8168_driver_start(struct rtl8169_private *tp) 1178 { 1179 switch (tp->mac_version) { 1180 case RTL_GIGA_MAC_VER_27: 1181 case RTL_GIGA_MAC_VER_28: 1182 case RTL_GIGA_MAC_VER_31: 1183 rtl8168dp_driver_start(tp); 1184 break; 1185 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1186 rtl8168ep_driver_start(tp); 1187 break; 1188 default: 1189 BUG(); 1190 break; 1191 } 1192 } 1193 1194 static void rtl8168dp_driver_stop(struct rtl8169_private *tp) 1195 { 1196 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP); 1197 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10); 1198 } 1199 1200 static void rtl8168ep_driver_stop(struct rtl8169_private *tp) 1201 { 1202 rtl8168ep_stop_cmac(tp); 1203 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); 1204 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); 1205 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10); 1206 } 1207 1208 static void rtl8168_driver_stop(struct rtl8169_private *tp) 1209 { 1210 switch (tp->mac_version) { 1211 case RTL_GIGA_MAC_VER_27: 1212 case RTL_GIGA_MAC_VER_28: 1213 case RTL_GIGA_MAC_VER_31: 1214 rtl8168dp_driver_stop(tp); 1215 break; 1216 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1217 rtl8168ep_driver_stop(tp); 1218 break; 1219 default: 1220 BUG(); 1221 break; 1222 } 1223 } 1224 1225 static bool r8168dp_check_dash(struct rtl8169_private *tp) 1226 { 1227 u16 reg = rtl8168_get_ocp_reg(tp); 1228 1229 return !!(r8168dp_ocp_read(tp, reg) & 0x00008000); 1230 } 1231 1232 static bool r8168ep_check_dash(struct rtl8169_private *tp) 1233 { 1234 return r8168ep_ocp_read(tp, 0x128) & 0x00000001; 1235 } 1236 1237 static bool r8168_check_dash(struct rtl8169_private *tp) 1238 { 1239 switch (tp->mac_version) { 1240 case RTL_GIGA_MAC_VER_27: 1241 case RTL_GIGA_MAC_VER_28: 1242 case RTL_GIGA_MAC_VER_31: 1243 return r8168dp_check_dash(tp); 1244 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 1245 return r8168ep_check_dash(tp); 1246 default: 1247 return false; 1248 } 1249 } 1250 1251 static void rtl_reset_packet_filter(struct rtl8169_private *tp) 1252 { 1253 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); 1254 rtl_eri_set_bits(tp, 0xdc, BIT(0)); 1255 } 1256 1257 DECLARE_RTL_COND(rtl_efusear_cond) 1258 { 1259 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG; 1260 } 1261 1262 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr) 1263 { 1264 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); 1265 1266 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ? 1267 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; 1268 } 1269 1270 static u32 rtl_get_events(struct rtl8169_private *tp) 1271 { 1272 if (rtl_is_8125(tp)) 1273 return RTL_R32(tp, IntrStatus_8125); 1274 else 1275 return RTL_R16(tp, IntrStatus); 1276 } 1277 1278 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits) 1279 { 1280 if (rtl_is_8125(tp)) 1281 RTL_W32(tp, IntrStatus_8125, bits); 1282 else 1283 RTL_W16(tp, IntrStatus, bits); 1284 } 1285 1286 static void rtl_irq_disable(struct rtl8169_private *tp) 1287 { 1288 if (rtl_is_8125(tp)) 1289 RTL_W32(tp, IntrMask_8125, 0); 1290 else 1291 RTL_W16(tp, IntrMask, 0); 1292 tp->irq_enabled = 0; 1293 } 1294 1295 static void rtl_irq_enable(struct rtl8169_private *tp) 1296 { 1297 tp->irq_enabled = 1; 1298 if (rtl_is_8125(tp)) 1299 RTL_W32(tp, IntrMask_8125, tp->irq_mask); 1300 else 1301 RTL_W16(tp, IntrMask, tp->irq_mask); 1302 } 1303 1304 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp) 1305 { 1306 rtl_irq_disable(tp); 1307 rtl_ack_events(tp, 0xffffffff); 1308 rtl_pci_commit(tp); 1309 } 1310 1311 static void rtl_link_chg_patch(struct rtl8169_private *tp) 1312 { 1313 struct phy_device *phydev = tp->phydev; 1314 1315 if (tp->mac_version == RTL_GIGA_MAC_VER_34 || 1316 tp->mac_version == RTL_GIGA_MAC_VER_38) { 1317 if (phydev->speed == SPEED_1000) { 1318 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1319 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1320 } else if (phydev->speed == SPEED_100) { 1321 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1322 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1323 } else { 1324 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1325 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1326 } 1327 rtl_reset_packet_filter(tp); 1328 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 || 1329 tp->mac_version == RTL_GIGA_MAC_VER_36) { 1330 if (phydev->speed == SPEED_1000) { 1331 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); 1332 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); 1333 } else { 1334 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); 1335 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); 1336 } 1337 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) { 1338 if (phydev->speed == SPEED_10) { 1339 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); 1340 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); 1341 } else { 1342 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 1343 } 1344 } 1345 } 1346 1347 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 1348 1349 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1350 { 1351 struct rtl8169_private *tp = netdev_priv(dev); 1352 1353 rtl_lock_work(tp); 1354 wol->supported = WAKE_ANY; 1355 wol->wolopts = tp->saved_wolopts; 1356 rtl_unlock_work(tp); 1357 } 1358 1359 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 1360 { 1361 static const struct { 1362 u32 opt; 1363 u16 reg; 1364 u8 mask; 1365 } cfg[] = { 1366 { WAKE_PHY, Config3, LinkUp }, 1367 { WAKE_UCAST, Config5, UWF }, 1368 { WAKE_BCAST, Config5, BWF }, 1369 { WAKE_MCAST, Config5, MWF }, 1370 { WAKE_ANY, Config5, LanWake }, 1371 { WAKE_MAGIC, Config3, MagicPacket } 1372 }; 1373 unsigned int i, tmp = ARRAY_SIZE(cfg); 1374 u8 options; 1375 1376 rtl_unlock_config_regs(tp); 1377 1378 if (rtl_is_8168evl_up(tp)) { 1379 tmp--; 1380 if (wolopts & WAKE_MAGIC) 1381 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); 1382 else 1383 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); 1384 } else if (rtl_is_8125(tp)) { 1385 tmp--; 1386 if (wolopts & WAKE_MAGIC) 1387 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); 1388 else 1389 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); 1390 } 1391 1392 for (i = 0; i < tmp; i++) { 1393 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; 1394 if (wolopts & cfg[i].opt) 1395 options |= cfg[i].mask; 1396 RTL_W8(tp, cfg[i].reg, options); 1397 } 1398 1399 switch (tp->mac_version) { 1400 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 1401 options = RTL_R8(tp, Config1) & ~PMEnable; 1402 if (wolopts) 1403 options |= PMEnable; 1404 RTL_W8(tp, Config1, options); 1405 break; 1406 case RTL_GIGA_MAC_VER_34: 1407 case RTL_GIGA_MAC_VER_37: 1408 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_61: 1409 options = RTL_R8(tp, Config2) & ~PME_SIGNAL; 1410 if (wolopts) 1411 options |= PME_SIGNAL; 1412 RTL_W8(tp, Config2, options); 1413 break; 1414 default: 1415 break; 1416 } 1417 1418 rtl_lock_config_regs(tp); 1419 1420 device_set_wakeup_enable(tp_to_dev(tp), wolopts); 1421 tp->dev->wol_enabled = wolopts ? 1 : 0; 1422 } 1423 1424 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 1425 { 1426 struct rtl8169_private *tp = netdev_priv(dev); 1427 struct device *d = tp_to_dev(tp); 1428 1429 if (wol->wolopts & ~WAKE_ANY) 1430 return -EINVAL; 1431 1432 pm_runtime_get_noresume(d); 1433 1434 rtl_lock_work(tp); 1435 1436 tp->saved_wolopts = wol->wolopts; 1437 1438 if (pm_runtime_active(d)) 1439 __rtl8169_set_wol(tp, tp->saved_wolopts); 1440 1441 rtl_unlock_work(tp); 1442 1443 pm_runtime_put_noidle(d); 1444 1445 return 0; 1446 } 1447 1448 static void rtl8169_get_drvinfo(struct net_device *dev, 1449 struct ethtool_drvinfo *info) 1450 { 1451 struct rtl8169_private *tp = netdev_priv(dev); 1452 struct rtl_fw *rtl_fw = tp->rtl_fw; 1453 1454 strlcpy(info->driver, MODULENAME, sizeof(info->driver)); 1455 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); 1456 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); 1457 if (rtl_fw) 1458 strlcpy(info->fw_version, rtl_fw->version, 1459 sizeof(info->fw_version)); 1460 } 1461 1462 static int rtl8169_get_regs_len(struct net_device *dev) 1463 { 1464 return R8169_REGS_SIZE; 1465 } 1466 1467 static netdev_features_t rtl8169_fix_features(struct net_device *dev, 1468 netdev_features_t features) 1469 { 1470 struct rtl8169_private *tp = netdev_priv(dev); 1471 1472 if (dev->mtu > TD_MSS_MAX) 1473 features &= ~NETIF_F_ALL_TSO; 1474 1475 if (dev->mtu > ETH_DATA_LEN && 1476 tp->mac_version > RTL_GIGA_MAC_VER_06) 1477 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO); 1478 1479 return features; 1480 } 1481 1482 static void rtl_set_rx_config_features(struct rtl8169_private *tp, 1483 netdev_features_t features) 1484 { 1485 u32 rx_config = RTL_R32(tp, RxConfig); 1486 1487 if (features & NETIF_F_RXALL) 1488 rx_config |= RX_CONFIG_ACCEPT_ERR_MASK; 1489 else 1490 rx_config &= ~RX_CONFIG_ACCEPT_ERR_MASK; 1491 1492 if (rtl_is_8125(tp)) { 1493 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1494 rx_config |= RX_VLAN_8125; 1495 else 1496 rx_config &= ~RX_VLAN_8125; 1497 } 1498 1499 RTL_W32(tp, RxConfig, rx_config); 1500 } 1501 1502 static int rtl8169_set_features(struct net_device *dev, 1503 netdev_features_t features) 1504 { 1505 struct rtl8169_private *tp = netdev_priv(dev); 1506 1507 rtl_lock_work(tp); 1508 1509 rtl_set_rx_config_features(tp, features); 1510 1511 if (features & NETIF_F_RXCSUM) 1512 tp->cp_cmd |= RxChkSum; 1513 else 1514 tp->cp_cmd &= ~RxChkSum; 1515 1516 if (!rtl_is_8125(tp)) { 1517 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1518 tp->cp_cmd |= RxVlan; 1519 else 1520 tp->cp_cmd &= ~RxVlan; 1521 } 1522 1523 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1524 rtl_pci_commit(tp); 1525 1526 rtl_unlock_work(tp); 1527 1528 return 0; 1529 } 1530 1531 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb) 1532 { 1533 return (skb_vlan_tag_present(skb)) ? 1534 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; 1535 } 1536 1537 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) 1538 { 1539 u32 opts2 = le32_to_cpu(desc->opts2); 1540 1541 if (opts2 & RxVlanTag) 1542 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); 1543 } 1544 1545 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, 1546 void *p) 1547 { 1548 struct rtl8169_private *tp = netdev_priv(dev); 1549 u32 __iomem *data = tp->mmio_addr; 1550 u32 *dw = p; 1551 int i; 1552 1553 rtl_lock_work(tp); 1554 for (i = 0; i < R8169_REGS_SIZE; i += 4) 1555 memcpy_fromio(dw++, data++, 4); 1556 rtl_unlock_work(tp); 1557 } 1558 1559 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { 1560 "tx_packets", 1561 "rx_packets", 1562 "tx_errors", 1563 "rx_errors", 1564 "rx_missed", 1565 "align_errors", 1566 "tx_single_collisions", 1567 "tx_multi_collisions", 1568 "unicast", 1569 "broadcast", 1570 "multicast", 1571 "tx_aborted", 1572 "tx_underrun", 1573 }; 1574 1575 static int rtl8169_get_sset_count(struct net_device *dev, int sset) 1576 { 1577 switch (sset) { 1578 case ETH_SS_STATS: 1579 return ARRAY_SIZE(rtl8169_gstrings); 1580 default: 1581 return -EOPNOTSUPP; 1582 } 1583 } 1584 1585 DECLARE_RTL_COND(rtl_counters_cond) 1586 { 1587 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump); 1588 } 1589 1590 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd) 1591 { 1592 dma_addr_t paddr = tp->counters_phys_addr; 1593 u32 cmd; 1594 1595 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32); 1596 rtl_pci_commit(tp); 1597 cmd = (u64)paddr & DMA_BIT_MASK(32); 1598 RTL_W32(tp, CounterAddrLow, cmd); 1599 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd); 1600 1601 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000); 1602 } 1603 1604 static void rtl8169_reset_counters(struct rtl8169_private *tp) 1605 { 1606 /* 1607 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the 1608 * tally counters. 1609 */ 1610 if (tp->mac_version >= RTL_GIGA_MAC_VER_19) 1611 rtl8169_do_counters(tp, CounterReset); 1612 } 1613 1614 static void rtl8169_update_counters(struct rtl8169_private *tp) 1615 { 1616 u8 val = RTL_R8(tp, ChipCmd); 1617 1618 /* 1619 * Some chips are unable to dump tally counters when the receiver 1620 * is disabled. If 0xff chip may be in a PCI power-save state. 1621 */ 1622 if (val & CmdRxEnb && val != 0xff) 1623 rtl8169_do_counters(tp, CounterDump); 1624 } 1625 1626 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp) 1627 { 1628 struct rtl8169_counters *counters = tp->counters; 1629 1630 /* 1631 * rtl8169_init_counter_offsets is called from rtl_open. On chip 1632 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only 1633 * reset by a power cycle, while the counter values collected by the 1634 * driver are reset at every driver unload/load cycle. 1635 * 1636 * To make sure the HW values returned by @get_stats64 match the SW 1637 * values, we collect the initial values at first open(*) and use them 1638 * as offsets to normalize the values returned by @get_stats64. 1639 * 1640 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one 1641 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only 1642 * set at open time by rtl_hw_start. 1643 */ 1644 1645 if (tp->tc_offset.inited) 1646 return; 1647 1648 rtl8169_reset_counters(tp); 1649 rtl8169_update_counters(tp); 1650 1651 tp->tc_offset.tx_errors = counters->tx_errors; 1652 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision; 1653 tp->tc_offset.tx_aborted = counters->tx_aborted; 1654 tp->tc_offset.rx_missed = counters->rx_missed; 1655 tp->tc_offset.inited = true; 1656 } 1657 1658 static void rtl8169_get_ethtool_stats(struct net_device *dev, 1659 struct ethtool_stats *stats, u64 *data) 1660 { 1661 struct rtl8169_private *tp = netdev_priv(dev); 1662 struct device *d = tp_to_dev(tp); 1663 struct rtl8169_counters *counters = tp->counters; 1664 1665 ASSERT_RTNL(); 1666 1667 pm_runtime_get_noresume(d); 1668 1669 if (pm_runtime_active(d)) 1670 rtl8169_update_counters(tp); 1671 1672 pm_runtime_put_noidle(d); 1673 1674 data[0] = le64_to_cpu(counters->tx_packets); 1675 data[1] = le64_to_cpu(counters->rx_packets); 1676 data[2] = le64_to_cpu(counters->tx_errors); 1677 data[3] = le32_to_cpu(counters->rx_errors); 1678 data[4] = le16_to_cpu(counters->rx_missed); 1679 data[5] = le16_to_cpu(counters->align_errors); 1680 data[6] = le32_to_cpu(counters->tx_one_collision); 1681 data[7] = le32_to_cpu(counters->tx_multi_collision); 1682 data[8] = le64_to_cpu(counters->rx_unicast); 1683 data[9] = le64_to_cpu(counters->rx_broadcast); 1684 data[10] = le32_to_cpu(counters->rx_multicast); 1685 data[11] = le16_to_cpu(counters->tx_aborted); 1686 data[12] = le16_to_cpu(counters->tx_underun); 1687 } 1688 1689 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) 1690 { 1691 switch(stringset) { 1692 case ETH_SS_STATS: 1693 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); 1694 break; 1695 } 1696 } 1697 1698 /* 1699 * Interrupt coalescing 1700 * 1701 * > 1 - the availability of the IntrMitigate (0xe2) register through the 1702 * > 8169, 8168 and 810x line of chipsets 1703 * 1704 * 8169, 8168, and 8136(810x) serial chipsets support it. 1705 * 1706 * > 2 - the Tx timer unit at gigabit speed 1707 * 1708 * The unit of the timer depends on both the speed and the setting of CPlusCmd 1709 * (0xe0) bit 1 and bit 0. 1710 * 1711 * For 8169 1712 * bit[1:0] \ speed 1000M 100M 10M 1713 * 0 0 320ns 2.56us 40.96us 1714 * 0 1 2.56us 20.48us 327.7us 1715 * 1 0 5.12us 40.96us 655.4us 1716 * 1 1 10.24us 81.92us 1.31ms 1717 * 1718 * For the other 1719 * bit[1:0] \ speed 1000M 100M 10M 1720 * 0 0 5us 2.56us 40.96us 1721 * 0 1 40us 20.48us 327.7us 1722 * 1 0 80us 40.96us 655.4us 1723 * 1 1 160us 81.92us 1.31ms 1724 */ 1725 1726 /* rx/tx scale factors for all CPlusCmd[0:1] cases */ 1727 struct rtl_coalesce_info { 1728 u32 speed; 1729 u32 scale_nsecs[4]; 1730 }; 1731 1732 /* produce array with base delay *1, *8, *8*2, *8*2*2 */ 1733 #define COALESCE_DELAY(d) { (d), 8 * (d), 16 * (d), 32 * (d) } 1734 1735 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = { 1736 { SPEED_10, COALESCE_DELAY(40960) }, 1737 { SPEED_100, COALESCE_DELAY(2560) }, 1738 { SPEED_1000, COALESCE_DELAY(320) }, 1739 { 0 }, 1740 }; 1741 1742 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = { 1743 { SPEED_10, COALESCE_DELAY(40960) }, 1744 { SPEED_100, COALESCE_DELAY(2560) }, 1745 { SPEED_1000, COALESCE_DELAY(5000) }, 1746 { 0 }, 1747 }; 1748 #undef COALESCE_DELAY 1749 1750 /* get rx/tx scale vector corresponding to current speed */ 1751 static const struct rtl_coalesce_info * 1752 rtl_coalesce_info(struct rtl8169_private *tp) 1753 { 1754 const struct rtl_coalesce_info *ci; 1755 1756 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 1757 ci = rtl_coalesce_info_8169; 1758 else 1759 ci = rtl_coalesce_info_8168_8136; 1760 1761 for (; ci->speed; ci++) { 1762 if (tp->phydev->speed == ci->speed) 1763 return ci; 1764 } 1765 1766 return ERR_PTR(-ELNRNG); 1767 } 1768 1769 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1770 { 1771 struct rtl8169_private *tp = netdev_priv(dev); 1772 const struct rtl_coalesce_info *ci; 1773 u32 scale, c_us, c_fr; 1774 u16 intrmit; 1775 1776 if (rtl_is_8125(tp)) 1777 return -EOPNOTSUPP; 1778 1779 memset(ec, 0, sizeof(*ec)); 1780 1781 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ 1782 ci = rtl_coalesce_info(tp); 1783 if (IS_ERR(ci)) 1784 return PTR_ERR(ci); 1785 1786 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK]; 1787 1788 intrmit = RTL_R16(tp, IntrMitigate); 1789 1790 c_us = FIELD_GET(RTL_COALESCE_TX_USECS, intrmit); 1791 ec->tx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1792 1793 c_fr = FIELD_GET(RTL_COALESCE_TX_FRAMES, intrmit); 1794 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ 1795 ec->tx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1796 1797 c_us = FIELD_GET(RTL_COALESCE_RX_USECS, intrmit); 1798 ec->rx_coalesce_usecs = DIV_ROUND_UP(c_us * scale, 1000); 1799 1800 c_fr = FIELD_GET(RTL_COALESCE_RX_FRAMES, intrmit); 1801 ec->rx_max_coalesced_frames = (c_us || c_fr) ? c_fr * 4 : 1; 1802 1803 return 0; 1804 } 1805 1806 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */ 1807 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec, 1808 u16 *cp01) 1809 { 1810 const struct rtl_coalesce_info *ci; 1811 u16 i; 1812 1813 ci = rtl_coalesce_info(tp); 1814 if (IS_ERR(ci)) 1815 return PTR_ERR(ci); 1816 1817 for (i = 0; i < 4; i++) { 1818 if (usec <= ci->scale_nsecs[i] * RTL_COALESCE_T_MAX / 1000U) { 1819 *cp01 = i; 1820 return ci->scale_nsecs[i]; 1821 } 1822 } 1823 1824 return -ERANGE; 1825 } 1826 1827 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec) 1828 { 1829 struct rtl8169_private *tp = netdev_priv(dev); 1830 u32 tx_fr = ec->tx_max_coalesced_frames; 1831 u32 rx_fr = ec->rx_max_coalesced_frames; 1832 u32 coal_usec_max, units; 1833 u16 w = 0, cp01 = 0; 1834 int scale; 1835 1836 if (rtl_is_8125(tp)) 1837 return -EOPNOTSUPP; 1838 1839 if (rx_fr > RTL_COALESCE_FRAME_MAX || tx_fr > RTL_COALESCE_FRAME_MAX) 1840 return -ERANGE; 1841 1842 coal_usec_max = max(ec->rx_coalesce_usecs, ec->tx_coalesce_usecs); 1843 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01); 1844 if (scale < 0) 1845 return scale; 1846 1847 /* Accept max_frames=1 we returned in rtl_get_coalesce. Accept it 1848 * not only when usecs=0 because of e.g. the following scenario: 1849 * 1850 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) 1851 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 1852 * - then user does `ethtool -C eth0 rx-usecs 100` 1853 * 1854 * Since ethtool sends to kernel whole ethtool_coalesce settings, 1855 * if we want to ignore rx_frames then it has to be set to 0. 1856 */ 1857 if (rx_fr == 1) 1858 rx_fr = 0; 1859 if (tx_fr == 1) 1860 tx_fr = 0; 1861 1862 /* HW requires time limit to be set if frame limit is set */ 1863 if ((tx_fr && !ec->tx_coalesce_usecs) || 1864 (rx_fr && !ec->rx_coalesce_usecs)) 1865 return -EINVAL; 1866 1867 w |= FIELD_PREP(RTL_COALESCE_TX_FRAMES, DIV_ROUND_UP(tx_fr, 4)); 1868 w |= FIELD_PREP(RTL_COALESCE_RX_FRAMES, DIV_ROUND_UP(rx_fr, 4)); 1869 1870 units = DIV_ROUND_UP(ec->tx_coalesce_usecs * 1000U, scale); 1871 w |= FIELD_PREP(RTL_COALESCE_TX_USECS, units); 1872 units = DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000U, scale); 1873 w |= FIELD_PREP(RTL_COALESCE_RX_USECS, units); 1874 1875 rtl_lock_work(tp); 1876 1877 RTL_W16(tp, IntrMitigate, w); 1878 1879 /* Meaning of PktCntrDisable bit changed from RTL8168e-vl */ 1880 if (rtl_is_8168evl_up(tp)) { 1881 if (!rx_fr && !tx_fr) 1882 /* disable packet counter */ 1883 tp->cp_cmd |= PktCntrDisable; 1884 else 1885 tp->cp_cmd &= ~PktCntrDisable; 1886 } 1887 1888 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01; 1889 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 1890 rtl_pci_commit(tp); 1891 1892 rtl_unlock_work(tp); 1893 1894 return 0; 1895 } 1896 1897 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data) 1898 { 1899 struct rtl8169_private *tp = netdev_priv(dev); 1900 struct device *d = tp_to_dev(tp); 1901 int ret; 1902 1903 if (!rtl_supports_eee(tp)) 1904 return -EOPNOTSUPP; 1905 1906 pm_runtime_get_noresume(d); 1907 1908 if (!pm_runtime_active(d)) { 1909 ret = -EOPNOTSUPP; 1910 } else { 1911 ret = phy_ethtool_get_eee(tp->phydev, data); 1912 } 1913 1914 pm_runtime_put_noidle(d); 1915 1916 return ret; 1917 } 1918 1919 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data) 1920 { 1921 struct rtl8169_private *tp = netdev_priv(dev); 1922 struct device *d = tp_to_dev(tp); 1923 int ret; 1924 1925 if (!rtl_supports_eee(tp)) 1926 return -EOPNOTSUPP; 1927 1928 pm_runtime_get_noresume(d); 1929 1930 if (!pm_runtime_active(d)) { 1931 ret = -EOPNOTSUPP; 1932 goto out; 1933 } 1934 1935 ret = phy_ethtool_set_eee(tp->phydev, data); 1936 1937 if (!ret) 1938 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN, 1939 MDIO_AN_EEE_ADV); 1940 out: 1941 pm_runtime_put_noidle(d); 1942 return ret; 1943 } 1944 1945 static const struct ethtool_ops rtl8169_ethtool_ops = { 1946 .supported_coalesce_params = ETHTOOL_COALESCE_USECS | 1947 ETHTOOL_COALESCE_MAX_FRAMES, 1948 .get_drvinfo = rtl8169_get_drvinfo, 1949 .get_regs_len = rtl8169_get_regs_len, 1950 .get_link = ethtool_op_get_link, 1951 .get_coalesce = rtl_get_coalesce, 1952 .set_coalesce = rtl_set_coalesce, 1953 .get_regs = rtl8169_get_regs, 1954 .get_wol = rtl8169_get_wol, 1955 .set_wol = rtl8169_set_wol, 1956 .get_strings = rtl8169_get_strings, 1957 .get_sset_count = rtl8169_get_sset_count, 1958 .get_ethtool_stats = rtl8169_get_ethtool_stats, 1959 .get_ts_info = ethtool_op_get_ts_info, 1960 .nway_reset = phy_ethtool_nway_reset, 1961 .get_eee = rtl8169_get_eee, 1962 .set_eee = rtl8169_set_eee, 1963 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1964 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1965 }; 1966 1967 static void rtl_enable_eee(struct rtl8169_private *tp) 1968 { 1969 struct phy_device *phydev = tp->phydev; 1970 int adv; 1971 1972 /* respect EEE advertisement the user may have set */ 1973 if (tp->eee_adv >= 0) 1974 adv = tp->eee_adv; 1975 else 1976 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 1977 1978 if (adv >= 0) 1979 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv); 1980 } 1981 1982 static enum mac_version rtl8169_get_mac_version(u16 xid, bool gmii) 1983 { 1984 /* 1985 * The driver currently handles the 8168Bf and the 8168Be identically 1986 * but they can be identified more specifically through the test below 1987 * if needed: 1988 * 1989 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be 1990 * 1991 * Same thing for the 8101Eb and the 8101Ec: 1992 * 1993 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec 1994 */ 1995 static const struct rtl_mac_info { 1996 u16 mask; 1997 u16 val; 1998 enum mac_version ver; 1999 } mac_info[] = { 2000 /* 8125 family. */ 2001 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, 2002 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, 2003 2004 /* RTL8117 */ 2005 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, 2006 2007 /* 8168EP family. */ 2008 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, 2009 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, 2010 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, 2011 2012 /* 8168H family. */ 2013 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, 2014 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, 2015 2016 /* 8168G family. */ 2017 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, 2018 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, 2019 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, 2020 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, 2021 2022 /* 8168F family. */ 2023 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, 2024 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, 2025 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, 2026 2027 /* 8168E family. */ 2028 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, 2029 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, 2030 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, 2031 2032 /* 8168D family. */ 2033 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, 2034 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, 2035 2036 /* 8168DP family. */ 2037 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, 2038 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, 2039 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, 2040 2041 /* 8168C family. */ 2042 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, 2043 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, 2044 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, 2045 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, 2046 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, 2047 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, 2048 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, 2049 2050 /* 8168B family. */ 2051 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 }, 2052 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, 2053 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, 2054 2055 /* 8101 family. */ 2056 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, 2057 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, 2058 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, 2059 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, 2060 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, 2061 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, 2062 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, 2063 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, 2064 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 }, 2065 /* RTL8401, reportedly works if treated as RTL8101e */ 2066 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_13 }, 2067 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 }, 2068 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 }, 2069 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, 2070 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, 2071 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 }, 2072 /* FIXME: where did these entries come from ? -- FR */ 2073 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 }, 2074 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 }, 2075 2076 /* 8110 family. */ 2077 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, 2078 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, 2079 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, 2080 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, 2081 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, 2082 2083 /* Catch-all */ 2084 { 0x000, 0x000, RTL_GIGA_MAC_NONE } 2085 }; 2086 const struct rtl_mac_info *p = mac_info; 2087 enum mac_version ver; 2088 2089 while ((xid & p->mask) != p->val) 2090 p++; 2091 ver = p->ver; 2092 2093 if (ver != RTL_GIGA_MAC_NONE && !gmii) { 2094 if (ver == RTL_GIGA_MAC_VER_42) 2095 ver = RTL_GIGA_MAC_VER_43; 2096 else if (ver == RTL_GIGA_MAC_VER_45) 2097 ver = RTL_GIGA_MAC_VER_47; 2098 else if (ver == RTL_GIGA_MAC_VER_46) 2099 ver = RTL_GIGA_MAC_VER_48; 2100 } 2101 2102 return ver; 2103 } 2104 2105 static void rtl_release_firmware(struct rtl8169_private *tp) 2106 { 2107 if (tp->rtl_fw) { 2108 rtl_fw_release_firmware(tp->rtl_fw); 2109 kfree(tp->rtl_fw); 2110 tp->rtl_fw = NULL; 2111 } 2112 } 2113 2114 void r8169_apply_firmware(struct rtl8169_private *tp) 2115 { 2116 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ 2117 if (tp->rtl_fw) 2118 rtl_fw_write_firmware(tp, tp->rtl_fw); 2119 } 2120 2121 static void rtl8168_config_eee_mac(struct rtl8169_private *tp) 2122 { 2123 /* Adjust EEE LED frequency */ 2124 if (tp->mac_version != RTL_GIGA_MAC_VER_38) 2125 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); 2126 2127 rtl_eri_set_bits(tp, 0x1b0, 0x0003); 2128 } 2129 2130 static void rtl8125_config_eee_mac(struct rtl8169_private *tp) 2131 { 2132 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); 2133 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); 2134 } 2135 2136 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr) 2137 { 2138 const u16 w[] = { 2139 addr[0] | (addr[1] << 8), 2140 addr[2] | (addr[3] << 8), 2141 addr[4] | (addr[5] << 8) 2142 }; 2143 2144 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16)); 2145 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]); 2146 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16); 2147 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16)); 2148 } 2149 2150 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp) 2151 { 2152 u16 data1, data2, ioffset; 2153 2154 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); 2155 data1 = r8168_mac_ocp_read(tp, 0xdd02); 2156 data2 = r8168_mac_ocp_read(tp, 0xdd00); 2157 2158 ioffset = (data2 >> 1) & 0x7ff8; 2159 ioffset |= data2 & 0x0007; 2160 if (data1 & BIT(7)) 2161 ioffset |= BIT(15); 2162 2163 return ioffset; 2164 } 2165 2166 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag) 2167 { 2168 set_bit(flag, tp->wk.flags); 2169 schedule_work(&tp->wk.work); 2170 } 2171 2172 static void rtl8169_init_phy(struct rtl8169_private *tp) 2173 { 2174 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version); 2175 2176 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { 2177 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); 2178 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); 2179 /* set undocumented MAC Reg C+CR Offset 0x82h */ 2180 RTL_W8(tp, 0x82, 0x01); 2181 } 2182 2183 if (tp->mac_version == RTL_GIGA_MAC_VER_05 && 2184 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE && 2185 tp->pci_dev->subsystem_device == 0xe000) 2186 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); 2187 2188 /* We may have called phy_speed_down before */ 2189 phy_speed_up(tp->phydev); 2190 2191 if (rtl_supports_eee(tp)) 2192 rtl_enable_eee(tp); 2193 2194 genphy_soft_reset(tp->phydev); 2195 } 2196 2197 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) 2198 { 2199 rtl_lock_work(tp); 2200 2201 rtl_unlock_config_regs(tp); 2202 2203 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8); 2204 rtl_pci_commit(tp); 2205 2206 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24); 2207 rtl_pci_commit(tp); 2208 2209 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 2210 rtl_rar_exgmac_set(tp, addr); 2211 2212 rtl_lock_config_regs(tp); 2213 2214 rtl_unlock_work(tp); 2215 } 2216 2217 static int rtl_set_mac_address(struct net_device *dev, void *p) 2218 { 2219 struct rtl8169_private *tp = netdev_priv(dev); 2220 struct device *d = tp_to_dev(tp); 2221 int ret; 2222 2223 ret = eth_mac_addr(dev, p); 2224 if (ret) 2225 return ret; 2226 2227 pm_runtime_get_noresume(d); 2228 2229 if (pm_runtime_active(d)) 2230 rtl_rar_set(tp, dev->dev_addr); 2231 2232 pm_runtime_put_noidle(d); 2233 2234 return 0; 2235 } 2236 2237 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) 2238 { 2239 switch (tp->mac_version) { 2240 case RTL_GIGA_MAC_VER_25: 2241 case RTL_GIGA_MAC_VER_26: 2242 case RTL_GIGA_MAC_VER_29: 2243 case RTL_GIGA_MAC_VER_30: 2244 case RTL_GIGA_MAC_VER_32: 2245 case RTL_GIGA_MAC_VER_33: 2246 case RTL_GIGA_MAC_VER_34: 2247 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61: 2248 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | 2249 AcceptBroadcast | AcceptMulticast | AcceptMyPhys); 2250 break; 2251 default: 2252 break; 2253 } 2254 } 2255 2256 static void rtl_pll_power_down(struct rtl8169_private *tp) 2257 { 2258 if (r8168_check_dash(tp)) 2259 return; 2260 2261 if (tp->mac_version == RTL_GIGA_MAC_VER_32 || 2262 tp->mac_version == RTL_GIGA_MAC_VER_33) 2263 rtl_ephy_write(tp, 0x19, 0xff64); 2264 2265 if (device_may_wakeup(tp_to_dev(tp))) { 2266 phy_speed_down(tp->phydev, false); 2267 rtl_wol_suspend_quirk(tp); 2268 return; 2269 } 2270 2271 switch (tp->mac_version) { 2272 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2273 case RTL_GIGA_MAC_VER_37: 2274 case RTL_GIGA_MAC_VER_39: 2275 case RTL_GIGA_MAC_VER_43: 2276 case RTL_GIGA_MAC_VER_44: 2277 case RTL_GIGA_MAC_VER_45: 2278 case RTL_GIGA_MAC_VER_46: 2279 case RTL_GIGA_MAC_VER_47: 2280 case RTL_GIGA_MAC_VER_48: 2281 case RTL_GIGA_MAC_VER_50: 2282 case RTL_GIGA_MAC_VER_51: 2283 case RTL_GIGA_MAC_VER_52: 2284 case RTL_GIGA_MAC_VER_60: 2285 case RTL_GIGA_MAC_VER_61: 2286 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2287 break; 2288 case RTL_GIGA_MAC_VER_40: 2289 case RTL_GIGA_MAC_VER_41: 2290 case RTL_GIGA_MAC_VER_49: 2291 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); 2292 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80); 2293 break; 2294 default: 2295 break; 2296 } 2297 } 2298 2299 static void rtl_pll_power_up(struct rtl8169_private *tp) 2300 { 2301 switch (tp->mac_version) { 2302 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33: 2303 case RTL_GIGA_MAC_VER_37: 2304 case RTL_GIGA_MAC_VER_39: 2305 case RTL_GIGA_MAC_VER_43: 2306 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80); 2307 break; 2308 case RTL_GIGA_MAC_VER_44: 2309 case RTL_GIGA_MAC_VER_45: 2310 case RTL_GIGA_MAC_VER_46: 2311 case RTL_GIGA_MAC_VER_47: 2312 case RTL_GIGA_MAC_VER_48: 2313 case RTL_GIGA_MAC_VER_50: 2314 case RTL_GIGA_MAC_VER_51: 2315 case RTL_GIGA_MAC_VER_52: 2316 case RTL_GIGA_MAC_VER_60: 2317 case RTL_GIGA_MAC_VER_61: 2318 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2319 break; 2320 case RTL_GIGA_MAC_VER_40: 2321 case RTL_GIGA_MAC_VER_41: 2322 case RTL_GIGA_MAC_VER_49: 2323 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0); 2324 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); 2325 break; 2326 default: 2327 break; 2328 } 2329 2330 phy_resume(tp->phydev); 2331 } 2332 2333 static void rtl_init_rxcfg(struct rtl8169_private *tp) 2334 { 2335 switch (tp->mac_version) { 2336 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 2337 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 2338 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); 2339 break; 2340 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 2341 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36: 2342 case RTL_GIGA_MAC_VER_38: 2343 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); 2344 break; 2345 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2346 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF); 2347 break; 2348 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2349 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST); 2350 break; 2351 default: 2352 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST); 2353 break; 2354 } 2355 } 2356 2357 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) 2358 { 2359 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; 2360 } 2361 2362 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) 2363 { 2364 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2365 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); 2366 } 2367 2368 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) 2369 { 2370 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2371 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); 2372 } 2373 2374 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) 2375 { 2376 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2377 } 2378 2379 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp) 2380 { 2381 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2382 } 2383 2384 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) 2385 { 2386 RTL_W8(tp, MaxTxPacketSize, 0x3f); 2387 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); 2388 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); 2389 } 2390 2391 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) 2392 { 2393 RTL_W8(tp, MaxTxPacketSize, 0x0c); 2394 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); 2395 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); 2396 } 2397 2398 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) 2399 { 2400 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); 2401 } 2402 2403 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) 2404 { 2405 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); 2406 } 2407 2408 static void rtl_jumbo_config(struct rtl8169_private *tp) 2409 { 2410 bool jumbo = tp->dev->mtu > ETH_DATA_LEN; 2411 2412 rtl_unlock_config_regs(tp); 2413 switch (tp->mac_version) { 2414 case RTL_GIGA_MAC_VER_12: 2415 case RTL_GIGA_MAC_VER_17: 2416 if (jumbo) { 2417 pcie_set_readrq(tp->pci_dev, 512); 2418 r8168b_1_hw_jumbo_enable(tp); 2419 } else { 2420 r8168b_1_hw_jumbo_disable(tp); 2421 } 2422 break; 2423 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: 2424 if (jumbo) { 2425 pcie_set_readrq(tp->pci_dev, 512); 2426 r8168c_hw_jumbo_enable(tp); 2427 } else { 2428 r8168c_hw_jumbo_disable(tp); 2429 } 2430 break; 2431 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: 2432 if (jumbo) 2433 r8168dp_hw_jumbo_enable(tp); 2434 else 2435 r8168dp_hw_jumbo_disable(tp); 2436 break; 2437 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: 2438 if (jumbo) { 2439 pcie_set_readrq(tp->pci_dev, 512); 2440 r8168e_hw_jumbo_enable(tp); 2441 } else { 2442 r8168e_hw_jumbo_disable(tp); 2443 } 2444 break; 2445 default: 2446 break; 2447 } 2448 rtl_lock_config_regs(tp); 2449 2450 if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii) 2451 pcie_set_readrq(tp->pci_dev, 4096); 2452 } 2453 2454 DECLARE_RTL_COND(rtl_chipcmd_cond) 2455 { 2456 return RTL_R8(tp, ChipCmd) & CmdReset; 2457 } 2458 2459 static void rtl_hw_reset(struct rtl8169_private *tp) 2460 { 2461 RTL_W8(tp, ChipCmd, CmdReset); 2462 2463 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100); 2464 } 2465 2466 static void rtl_request_firmware(struct rtl8169_private *tp) 2467 { 2468 struct rtl_fw *rtl_fw; 2469 2470 /* firmware loaded already or no firmware available */ 2471 if (tp->rtl_fw || !tp->fw_name) 2472 return; 2473 2474 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); 2475 if (!rtl_fw) 2476 return; 2477 2478 rtl_fw->phy_write = rtl_writephy; 2479 rtl_fw->phy_read = rtl_readphy; 2480 rtl_fw->mac_mcu_write = mac_mcu_write; 2481 rtl_fw->mac_mcu_read = mac_mcu_read; 2482 rtl_fw->fw_name = tp->fw_name; 2483 rtl_fw->dev = tp_to_dev(tp); 2484 2485 if (rtl_fw_request_firmware(rtl_fw)) 2486 kfree(rtl_fw); 2487 else 2488 tp->rtl_fw = rtl_fw; 2489 } 2490 2491 static void rtl_rx_close(struct rtl8169_private *tp) 2492 { 2493 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK); 2494 } 2495 2496 DECLARE_RTL_COND(rtl_npq_cond) 2497 { 2498 return RTL_R8(tp, TxPoll) & NPQ; 2499 } 2500 2501 DECLARE_RTL_COND(rtl_txcfg_empty_cond) 2502 { 2503 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY; 2504 } 2505 2506 DECLARE_RTL_COND(rtl_rxtx_empty_cond) 2507 { 2508 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; 2509 } 2510 2511 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp) 2512 { 2513 switch (tp->mac_version) { 2514 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52: 2515 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42); 2516 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2517 break; 2518 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 2519 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42); 2520 break; 2521 default: 2522 break; 2523 } 2524 } 2525 2526 static void rtl_enable_rxdvgate(struct rtl8169_private *tp) 2527 { 2528 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN); 2529 fsleep(2000); 2530 rtl_wait_txrx_fifo_empty(tp); 2531 } 2532 2533 static void rtl_set_tx_config_registers(struct rtl8169_private *tp) 2534 { 2535 u32 val = TX_DMA_BURST << TxDMAShift | 2536 InterFrameGap << TxInterFrameGapShift; 2537 2538 if (rtl_is_8168evl_up(tp)) 2539 val |= TXCFG_AUTO_FIFO; 2540 2541 RTL_W32(tp, TxConfig, val); 2542 } 2543 2544 static void rtl_set_rx_max_size(struct rtl8169_private *tp) 2545 { 2546 /* Low hurts. Let's disable the filtering. */ 2547 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1); 2548 } 2549 2550 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp) 2551 { 2552 /* 2553 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh 2554 * register to be written before TxDescAddrLow to work. 2555 * Switching from MMIO to I/O access fixes the issue as well. 2556 */ 2557 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); 2558 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); 2559 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); 2560 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); 2561 } 2562 2563 static void rtl8169_set_magic_reg(struct rtl8169_private *tp) 2564 { 2565 u32 val; 2566 2567 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 2568 val = 0x000fff00; 2569 else if (tp->mac_version == RTL_GIGA_MAC_VER_06) 2570 val = 0x00ffff00; 2571 else 2572 return; 2573 2574 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) 2575 val |= 0xff; 2576 2577 RTL_W32(tp, 0x7c, val); 2578 } 2579 2580 static void rtl_set_rx_mode(struct net_device *dev) 2581 { 2582 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast; 2583 /* Multicast hash filter */ 2584 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; 2585 struct rtl8169_private *tp = netdev_priv(dev); 2586 u32 tmp; 2587 2588 if (dev->flags & IFF_PROMISC) { 2589 rx_mode |= AcceptAllPhys; 2590 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT || 2591 dev->flags & IFF_ALLMULTI || 2592 tp->mac_version == RTL_GIGA_MAC_VER_35) { 2593 /* accept all multicasts */ 2594 } else if (netdev_mc_empty(dev)) { 2595 rx_mode &= ~AcceptMulticast; 2596 } else { 2597 struct netdev_hw_addr *ha; 2598 2599 mc_filter[1] = mc_filter[0] = 0; 2600 netdev_for_each_mc_addr(ha, dev) { 2601 u32 bit_nr = eth_hw_addr_crc(ha) >> 26; 2602 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31); 2603 } 2604 2605 if (tp->mac_version > RTL_GIGA_MAC_VER_06) { 2606 tmp = mc_filter[0]; 2607 mc_filter[0] = swab32(mc_filter[1]); 2608 mc_filter[1] = swab32(tmp); 2609 } 2610 } 2611 2612 RTL_W32(tp, MAR0 + 4, mc_filter[1]); 2613 RTL_W32(tp, MAR0 + 0, mc_filter[0]); 2614 2615 tmp = RTL_R32(tp, RxConfig); 2616 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode); 2617 } 2618 2619 DECLARE_RTL_COND(rtl_csiar_cond) 2620 { 2621 return RTL_R32(tp, CSIAR) & CSIAR_FLAG; 2622 } 2623 2624 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value) 2625 { 2626 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2627 2628 RTL_W32(tp, CSIDR, value); 2629 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | 2630 CSIAR_BYTE_ENABLE | func << 16); 2631 2632 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100); 2633 } 2634 2635 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr) 2636 { 2637 u32 func = PCI_FUNC(tp->pci_dev->devfn); 2638 2639 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 | 2640 CSIAR_BYTE_ENABLE); 2641 2642 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ? 2643 RTL_R32(tp, CSIDR) : ~0; 2644 } 2645 2646 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val) 2647 { 2648 struct pci_dev *pdev = tp->pci_dev; 2649 u32 csi; 2650 2651 /* According to Realtek the value at config space address 0x070f 2652 * controls the L0s/L1 entrance latency. We try standard ECAM access 2653 * first and if it fails fall back to CSI. 2654 */ 2655 if (pdev->cfg_size > 0x070f && 2656 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) 2657 return; 2658 2659 netdev_notice_once(tp->dev, 2660 "No native access to PCI extended config space, falling back to CSI\n"); 2661 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; 2662 rtl_csi_write(tp, 0x070c, csi | val << 24); 2663 } 2664 2665 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp) 2666 { 2667 rtl_csi_access_enable(tp, 0x27); 2668 } 2669 2670 struct ephy_info { 2671 unsigned int offset; 2672 u16 mask; 2673 u16 bits; 2674 }; 2675 2676 static void __rtl_ephy_init(struct rtl8169_private *tp, 2677 const struct ephy_info *e, int len) 2678 { 2679 u16 w; 2680 2681 while (len-- > 0) { 2682 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits; 2683 rtl_ephy_write(tp, e->offset, w); 2684 e++; 2685 } 2686 } 2687 2688 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a)) 2689 2690 static void rtl_disable_clock_request(struct rtl8169_private *tp) 2691 { 2692 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL, 2693 PCI_EXP_LNKCTL_CLKREQ_EN); 2694 } 2695 2696 static void rtl_enable_clock_request(struct rtl8169_private *tp) 2697 { 2698 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL, 2699 PCI_EXP_LNKCTL_CLKREQ_EN); 2700 } 2701 2702 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp) 2703 { 2704 /* work around an issue when PCI reset occurs during L2/L3 state */ 2705 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); 2706 } 2707 2708 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) 2709 { 2710 /* Don't enable ASPM in the chip if OS can't control ASPM */ 2711 if (enable && tp->aspm_manageable) { 2712 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en); 2713 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn); 2714 } else { 2715 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn); 2716 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en); 2717 } 2718 2719 udelay(10); 2720 } 2721 2722 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat, 2723 u16 tx_stat, u16 rx_dyn, u16 tx_dyn) 2724 { 2725 /* Usage of dynamic vs. static FIFO is controlled by bit 2726 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known. 2727 */ 2728 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); 2729 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); 2730 } 2731 2732 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp, 2733 u8 low, u8 high) 2734 { 2735 /* FIFO thresholds for pause flow control */ 2736 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); 2737 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); 2738 } 2739 2740 static void rtl_hw_start_8168b(struct rtl8169_private *tp) 2741 { 2742 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2743 } 2744 2745 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp) 2746 { 2747 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); 2748 2749 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2750 2751 rtl_disable_clock_request(tp); 2752 } 2753 2754 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp) 2755 { 2756 static const struct ephy_info e_info_8168cp[] = { 2757 { 0x01, 0, 0x0001 }, 2758 { 0x02, 0x0800, 0x1000 }, 2759 { 0x03, 0, 0x0042 }, 2760 { 0x06, 0x0080, 0x0000 }, 2761 { 0x07, 0, 0x2000 } 2762 }; 2763 2764 rtl_set_def_aspm_entry_latency(tp); 2765 2766 rtl_ephy_init(tp, e_info_8168cp); 2767 2768 __rtl_hw_start_8168cp(tp); 2769 } 2770 2771 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp) 2772 { 2773 rtl_set_def_aspm_entry_latency(tp); 2774 2775 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2776 } 2777 2778 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp) 2779 { 2780 rtl_set_def_aspm_entry_latency(tp); 2781 2782 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 2783 2784 /* Magic. */ 2785 RTL_W8(tp, DBG_REG, 0x20); 2786 } 2787 2788 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp) 2789 { 2790 static const struct ephy_info e_info_8168c_1[] = { 2791 { 0x02, 0x0800, 0x1000 }, 2792 { 0x03, 0, 0x0002 }, 2793 { 0x06, 0x0080, 0x0000 } 2794 }; 2795 2796 rtl_set_def_aspm_entry_latency(tp); 2797 2798 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); 2799 2800 rtl_ephy_init(tp, e_info_8168c_1); 2801 2802 __rtl_hw_start_8168cp(tp); 2803 } 2804 2805 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp) 2806 { 2807 static const struct ephy_info e_info_8168c_2[] = { 2808 { 0x01, 0, 0x0001 }, 2809 { 0x03, 0x0400, 0x0020 } 2810 }; 2811 2812 rtl_set_def_aspm_entry_latency(tp); 2813 2814 rtl_ephy_init(tp, e_info_8168c_2); 2815 2816 __rtl_hw_start_8168cp(tp); 2817 } 2818 2819 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp) 2820 { 2821 rtl_hw_start_8168c_2(tp); 2822 } 2823 2824 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp) 2825 { 2826 rtl_set_def_aspm_entry_latency(tp); 2827 2828 __rtl_hw_start_8168cp(tp); 2829 } 2830 2831 static void rtl_hw_start_8168d(struct rtl8169_private *tp) 2832 { 2833 rtl_set_def_aspm_entry_latency(tp); 2834 2835 rtl_disable_clock_request(tp); 2836 } 2837 2838 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) 2839 { 2840 static const struct ephy_info e_info_8168d_4[] = { 2841 { 0x0b, 0x0000, 0x0048 }, 2842 { 0x19, 0x0020, 0x0050 }, 2843 { 0x0c, 0x0100, 0x0020 }, 2844 { 0x10, 0x0004, 0x0000 }, 2845 }; 2846 2847 rtl_set_def_aspm_entry_latency(tp); 2848 2849 rtl_ephy_init(tp, e_info_8168d_4); 2850 2851 rtl_enable_clock_request(tp); 2852 } 2853 2854 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp) 2855 { 2856 static const struct ephy_info e_info_8168e_1[] = { 2857 { 0x00, 0x0200, 0x0100 }, 2858 { 0x00, 0x0000, 0x0004 }, 2859 { 0x06, 0x0002, 0x0001 }, 2860 { 0x06, 0x0000, 0x0030 }, 2861 { 0x07, 0x0000, 0x2000 }, 2862 { 0x00, 0x0000, 0x0020 }, 2863 { 0x03, 0x5800, 0x2000 }, 2864 { 0x03, 0x0000, 0x0001 }, 2865 { 0x01, 0x0800, 0x1000 }, 2866 { 0x07, 0x0000, 0x4000 }, 2867 { 0x1e, 0x0000, 0x2000 }, 2868 { 0x19, 0xffff, 0xfe6c }, 2869 { 0x0a, 0x0000, 0x0040 } 2870 }; 2871 2872 rtl_set_def_aspm_entry_latency(tp); 2873 2874 rtl_ephy_init(tp, e_info_8168e_1); 2875 2876 rtl_disable_clock_request(tp); 2877 2878 /* Reset tx FIFO pointer */ 2879 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST); 2880 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST); 2881 2882 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2883 } 2884 2885 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 2886 { 2887 static const struct ephy_info e_info_8168e_2[] = { 2888 { 0x09, 0x0000, 0x0080 }, 2889 { 0x19, 0x0000, 0x0224 }, 2890 { 0x00, 0x0000, 0x0004 }, 2891 { 0x0c, 0x3df0, 0x0200 }, 2892 }; 2893 2894 rtl_set_def_aspm_entry_latency(tp); 2895 2896 rtl_ephy_init(tp, e_info_8168e_2); 2897 2898 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2899 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2900 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2901 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2902 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); 2903 rtl_reset_packet_filter(tp); 2904 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2905 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2906 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); 2907 2908 rtl_disable_clock_request(tp); 2909 2910 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2911 2912 rtl8168_config_eee_mac(tp); 2913 2914 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2915 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2916 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2917 2918 rtl_hw_aspm_clkreq_enable(tp, true); 2919 } 2920 2921 static void rtl_hw_start_8168f(struct rtl8169_private *tp) 2922 { 2923 rtl_set_def_aspm_entry_latency(tp); 2924 2925 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2926 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); 2927 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); 2928 rtl_reset_packet_filter(tp); 2929 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); 2930 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); 2931 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); 2932 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); 2933 2934 rtl_disable_clock_request(tp); 2935 2936 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 2937 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 2938 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN); 2939 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en); 2940 2941 rtl8168_config_eee_mac(tp); 2942 } 2943 2944 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 2945 { 2946 static const struct ephy_info e_info_8168f_1[] = { 2947 { 0x06, 0x00c0, 0x0020 }, 2948 { 0x08, 0x0001, 0x0002 }, 2949 { 0x09, 0x0000, 0x0080 }, 2950 { 0x19, 0x0000, 0x0224 }, 2951 { 0x00, 0x0000, 0x0004 }, 2952 { 0x0c, 0x3df0, 0x0200 }, 2953 }; 2954 2955 rtl_hw_start_8168f(tp); 2956 2957 rtl_ephy_init(tp, e_info_8168f_1); 2958 2959 rtl_eri_set_bits(tp, 0x0d4, 0x1f00); 2960 } 2961 2962 static void rtl_hw_start_8411(struct rtl8169_private *tp) 2963 { 2964 static const struct ephy_info e_info_8168f_1[] = { 2965 { 0x06, 0x00c0, 0x0020 }, 2966 { 0x0f, 0xffff, 0x5200 }, 2967 { 0x19, 0x0000, 0x0224 }, 2968 { 0x00, 0x0000, 0x0004 }, 2969 { 0x0c, 0x3df0, 0x0200 }, 2970 }; 2971 2972 rtl_hw_start_8168f(tp); 2973 rtl_pcie_state_l2l3_disable(tp); 2974 2975 rtl_ephy_init(tp, e_info_8168f_1); 2976 2977 rtl_eri_set_bits(tp, 0x0d4, 0x0c00); 2978 } 2979 2980 static void rtl_hw_start_8168g(struct rtl8169_private *tp) 2981 { 2982 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 2983 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 2984 2985 rtl_set_def_aspm_entry_latency(tp); 2986 2987 rtl_reset_packet_filter(tp); 2988 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); 2989 2990 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 2991 2992 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 2993 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 2994 rtl_eri_set_bits(tp, 0x0d4, 0x1f80); 2995 2996 rtl8168_config_eee_mac(tp); 2997 2998 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 2999 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3000 3001 rtl_pcie_state_l2l3_disable(tp); 3002 } 3003 3004 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp) 3005 { 3006 static const struct ephy_info e_info_8168g_1[] = { 3007 { 0x00, 0x0008, 0x0000 }, 3008 { 0x0c, 0x3ff0, 0x0820 }, 3009 { 0x1e, 0x0000, 0x0001 }, 3010 { 0x19, 0x8000, 0x0000 } 3011 }; 3012 3013 rtl_hw_start_8168g(tp); 3014 3015 /* disable aspm and clock request before access ephy */ 3016 rtl_hw_aspm_clkreq_enable(tp, false); 3017 rtl_ephy_init(tp, e_info_8168g_1); 3018 rtl_hw_aspm_clkreq_enable(tp, true); 3019 } 3020 3021 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp) 3022 { 3023 static const struct ephy_info e_info_8168g_2[] = { 3024 { 0x00, 0x0008, 0x0000 }, 3025 { 0x0c, 0x3ff0, 0x0820 }, 3026 { 0x19, 0xffff, 0x7c00 }, 3027 { 0x1e, 0xffff, 0x20eb }, 3028 { 0x0d, 0xffff, 0x1666 }, 3029 { 0x00, 0xffff, 0x10a3 }, 3030 { 0x06, 0xffff, 0xf050 }, 3031 { 0x04, 0x0000, 0x0010 }, 3032 { 0x1d, 0x4000, 0x0000 }, 3033 }; 3034 3035 rtl_hw_start_8168g(tp); 3036 3037 /* disable aspm and clock request before access ephy */ 3038 rtl_hw_aspm_clkreq_enable(tp, false); 3039 rtl_ephy_init(tp, e_info_8168g_2); 3040 } 3041 3042 static void rtl_hw_start_8411_2(struct rtl8169_private *tp) 3043 { 3044 static const struct ephy_info e_info_8411_2[] = { 3045 { 0x00, 0x0008, 0x0000 }, 3046 { 0x0c, 0x37d0, 0x0820 }, 3047 { 0x1e, 0x0000, 0x0001 }, 3048 { 0x19, 0x8021, 0x0000 }, 3049 { 0x1e, 0x0000, 0x2000 }, 3050 { 0x0d, 0x0100, 0x0200 }, 3051 { 0x00, 0x0000, 0x0080 }, 3052 { 0x06, 0x0000, 0x0010 }, 3053 { 0x04, 0x0000, 0x0010 }, 3054 { 0x1d, 0x0000, 0x4000 }, 3055 }; 3056 3057 rtl_hw_start_8168g(tp); 3058 3059 /* disable aspm and clock request before access ephy */ 3060 rtl_hw_aspm_clkreq_enable(tp, false); 3061 rtl_ephy_init(tp, e_info_8411_2); 3062 3063 /* The following Realtek-provided magic fixes an issue with the RX unit 3064 * getting confused after the PHY having been powered-down. 3065 */ 3066 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); 3067 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); 3068 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); 3069 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); 3070 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); 3071 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); 3072 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); 3073 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); 3074 mdelay(3); 3075 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); 3076 3077 r8168_mac_ocp_write(tp, 0xF800, 0xE008); 3078 r8168_mac_ocp_write(tp, 0xF802, 0xE00A); 3079 r8168_mac_ocp_write(tp, 0xF804, 0xE00C); 3080 r8168_mac_ocp_write(tp, 0xF806, 0xE00E); 3081 r8168_mac_ocp_write(tp, 0xF808, 0xE027); 3082 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F); 3083 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E); 3084 r8168_mac_ocp_write(tp, 0xF80E, 0xE065); 3085 r8168_mac_ocp_write(tp, 0xF810, 0xC602); 3086 r8168_mac_ocp_write(tp, 0xF812, 0xBE00); 3087 r8168_mac_ocp_write(tp, 0xF814, 0x0000); 3088 r8168_mac_ocp_write(tp, 0xF816, 0xC502); 3089 r8168_mac_ocp_write(tp, 0xF818, 0xBD00); 3090 r8168_mac_ocp_write(tp, 0xF81A, 0x074C); 3091 r8168_mac_ocp_write(tp, 0xF81C, 0xC302); 3092 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00); 3093 r8168_mac_ocp_write(tp, 0xF820, 0x080A); 3094 r8168_mac_ocp_write(tp, 0xF822, 0x6420); 3095 r8168_mac_ocp_write(tp, 0xF824, 0x48C2); 3096 r8168_mac_ocp_write(tp, 0xF826, 0x8C20); 3097 r8168_mac_ocp_write(tp, 0xF828, 0xC516); 3098 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4); 3099 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0); 3100 r8168_mac_ocp_write(tp, 0xF82E, 0xF009); 3101 r8168_mac_ocp_write(tp, 0xF830, 0x74A2); 3102 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5); 3103 r8168_mac_ocp_write(tp, 0xF834, 0x74A0); 3104 r8168_mac_ocp_write(tp, 0xF836, 0xC50E); 3105 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2); 3106 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11); 3107 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0); 3108 r8168_mac_ocp_write(tp, 0xF83E, 0xE006); 3109 r8168_mac_ocp_write(tp, 0xF840, 0x74F8); 3110 r8168_mac_ocp_write(tp, 0xF842, 0x48C4); 3111 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8); 3112 r8168_mac_ocp_write(tp, 0xF846, 0xC404); 3113 r8168_mac_ocp_write(tp, 0xF848, 0xBC00); 3114 r8168_mac_ocp_write(tp, 0xF84A, 0xC403); 3115 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00); 3116 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2); 3117 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A); 3118 r8168_mac_ocp_write(tp, 0xF852, 0xE434); 3119 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0); 3120 r8168_mac_ocp_write(tp, 0xF856, 0x49D9); 3121 r8168_mac_ocp_write(tp, 0xF858, 0xF01F); 3122 r8168_mac_ocp_write(tp, 0xF85A, 0xC526); 3123 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5); 3124 r8168_mac_ocp_write(tp, 0xF85E, 0x1400); 3125 r8168_mac_ocp_write(tp, 0xF860, 0xF007); 3126 r8168_mac_ocp_write(tp, 0xF862, 0x0C01); 3127 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5); 3128 r8168_mac_ocp_write(tp, 0xF866, 0x1C15); 3129 r8168_mac_ocp_write(tp, 0xF868, 0xC51B); 3130 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0); 3131 r8168_mac_ocp_write(tp, 0xF86C, 0xE013); 3132 r8168_mac_ocp_write(tp, 0xF86E, 0xC519); 3133 r8168_mac_ocp_write(tp, 0xF870, 0x74A0); 3134 r8168_mac_ocp_write(tp, 0xF872, 0x48C4); 3135 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0); 3136 r8168_mac_ocp_write(tp, 0xF876, 0xC516); 3137 r8168_mac_ocp_write(tp, 0xF878, 0x74A4); 3138 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8); 3139 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA); 3140 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4); 3141 r8168_mac_ocp_write(tp, 0xF880, 0xC512); 3142 r8168_mac_ocp_write(tp, 0xF882, 0x1B00); 3143 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0); 3144 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C); 3145 r8168_mac_ocp_write(tp, 0xF888, 0x483F); 3146 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2); 3147 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04); 3148 r8168_mac_ocp_write(tp, 0xF88E, 0xC508); 3149 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0); 3150 r8168_mac_ocp_write(tp, 0xF892, 0xC505); 3151 r8168_mac_ocp_write(tp, 0xF894, 0xBD00); 3152 r8168_mac_ocp_write(tp, 0xF896, 0xC502); 3153 r8168_mac_ocp_write(tp, 0xF898, 0xBD00); 3154 r8168_mac_ocp_write(tp, 0xF89A, 0x0300); 3155 r8168_mac_ocp_write(tp, 0xF89C, 0x051E); 3156 r8168_mac_ocp_write(tp, 0xF89E, 0xE434); 3157 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018); 3158 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092); 3159 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20); 3160 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0); 3161 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F); 3162 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4); 3163 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3); 3164 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007); 3165 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0); 3166 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103); 3167 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607); 3168 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00); 3169 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606); 3170 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00); 3171 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602); 3172 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00); 3173 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C); 3174 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28); 3175 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C); 3176 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00); 3177 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707); 3178 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00); 3179 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2); 3180 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1); 3181 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502); 3182 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00); 3183 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA); 3184 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0); 3185 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502); 3186 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00); 3187 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132); 3188 3189 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); 3190 3191 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); 3192 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); 3193 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); 3194 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); 3195 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); 3196 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); 3197 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); 3198 3199 rtl_hw_aspm_clkreq_enable(tp, true); 3200 } 3201 3202 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 3203 { 3204 static const struct ephy_info e_info_8168h_1[] = { 3205 { 0x1e, 0x0800, 0x0001 }, 3206 { 0x1d, 0x0000, 0x0800 }, 3207 { 0x05, 0xffff, 0x2089 }, 3208 { 0x06, 0xffff, 0x5881 }, 3209 { 0x04, 0xffff, 0x854a }, 3210 { 0x01, 0xffff, 0x068b } 3211 }; 3212 int rg_saw_cnt; 3213 3214 /* disable aspm and clock request before access ephy */ 3215 rtl_hw_aspm_clkreq_enable(tp, false); 3216 rtl_ephy_init(tp, e_info_8168h_1); 3217 3218 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3219 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); 3220 3221 rtl_set_def_aspm_entry_latency(tp); 3222 3223 rtl_reset_packet_filter(tp); 3224 3225 rtl_eri_set_bits(tp, 0xd4, 0x1f00); 3226 rtl_eri_set_bits(tp, 0xdc, 0x001c); 3227 3228 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3229 3230 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3231 3232 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3233 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3234 3235 rtl8168_config_eee_mac(tp); 3236 3237 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3238 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3239 3240 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3241 3242 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3243 3244 rtl_pcie_state_l2l3_disable(tp); 3245 3246 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3247 if (rg_saw_cnt > 0) { 3248 u16 sw_cnt_1ms_ini; 3249 3250 sw_cnt_1ms_ini = 16000000/rg_saw_cnt; 3251 sw_cnt_1ms_ini &= 0x0fff; 3252 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3253 } 3254 3255 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3256 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); 3257 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); 3258 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3259 3260 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3261 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3262 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3263 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3264 3265 rtl_hw_aspm_clkreq_enable(tp, true); 3266 } 3267 3268 static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 3269 { 3270 rtl8168ep_stop_cmac(tp); 3271 3272 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3273 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3274 3275 rtl_set_def_aspm_entry_latency(tp); 3276 3277 rtl_reset_packet_filter(tp); 3278 3279 rtl_eri_set_bits(tp, 0xd4, 0x1f80); 3280 3281 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3282 3283 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3284 3285 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3286 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3287 3288 rtl8168_config_eee_mac(tp); 3289 3290 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); 3291 3292 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3293 3294 rtl_pcie_state_l2l3_disable(tp); 3295 } 3296 3297 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp) 3298 { 3299 static const struct ephy_info e_info_8168ep_1[] = { 3300 { 0x00, 0xffff, 0x10ab }, 3301 { 0x06, 0xffff, 0xf030 }, 3302 { 0x08, 0xffff, 0x2006 }, 3303 { 0x0d, 0xffff, 0x1666 }, 3304 { 0x0c, 0x3ff0, 0x0000 } 3305 }; 3306 3307 /* disable aspm and clock request before access ephy */ 3308 rtl_hw_aspm_clkreq_enable(tp, false); 3309 rtl_ephy_init(tp, e_info_8168ep_1); 3310 3311 rtl_hw_start_8168ep(tp); 3312 3313 rtl_hw_aspm_clkreq_enable(tp, true); 3314 } 3315 3316 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp) 3317 { 3318 static const struct ephy_info e_info_8168ep_2[] = { 3319 { 0x00, 0xffff, 0x10a3 }, 3320 { 0x19, 0xffff, 0xfc00 }, 3321 { 0x1e, 0xffff, 0x20ea } 3322 }; 3323 3324 /* disable aspm and clock request before access ephy */ 3325 rtl_hw_aspm_clkreq_enable(tp, false); 3326 rtl_ephy_init(tp, e_info_8168ep_2); 3327 3328 rtl_hw_start_8168ep(tp); 3329 3330 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3331 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3332 3333 rtl_hw_aspm_clkreq_enable(tp, true); 3334 } 3335 3336 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp) 3337 { 3338 static const struct ephy_info e_info_8168ep_3[] = { 3339 { 0x00, 0x0000, 0x0080 }, 3340 { 0x0d, 0x0100, 0x0200 }, 3341 { 0x19, 0x8021, 0x0000 }, 3342 { 0x1e, 0x0000, 0x2000 }, 3343 }; 3344 3345 /* disable aspm and clock request before access ephy */ 3346 rtl_hw_aspm_clkreq_enable(tp, false); 3347 rtl_ephy_init(tp, e_info_8168ep_3); 3348 3349 rtl_hw_start_8168ep(tp); 3350 3351 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3352 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3353 3354 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); 3355 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3356 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3357 3358 rtl_hw_aspm_clkreq_enable(tp, true); 3359 } 3360 3361 static void rtl_hw_start_8117(struct rtl8169_private *tp) 3362 { 3363 static const struct ephy_info e_info_8117[] = { 3364 { 0x19, 0x0040, 0x1100 }, 3365 { 0x59, 0x0040, 0x1100 }, 3366 }; 3367 int rg_saw_cnt; 3368 3369 rtl8168ep_stop_cmac(tp); 3370 3371 /* disable aspm and clock request before access ephy */ 3372 rtl_hw_aspm_clkreq_enable(tp, false); 3373 rtl_ephy_init(tp, e_info_8117); 3374 3375 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); 3376 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); 3377 3378 rtl_set_def_aspm_entry_latency(tp); 3379 3380 rtl_reset_packet_filter(tp); 3381 3382 rtl_eri_set_bits(tp, 0xd4, 0x1f90); 3383 3384 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); 3385 3386 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3387 3388 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3389 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3390 3391 rtl8168_config_eee_mac(tp); 3392 3393 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3394 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); 3395 3396 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); 3397 3398 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); 3399 3400 rtl_pcie_state_l2l3_disable(tp); 3401 3402 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; 3403 if (rg_saw_cnt > 0) { 3404 u16 sw_cnt_1ms_ini; 3405 3406 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; 3407 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); 3408 } 3409 3410 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); 3411 r8168_mac_ocp_write(tp, 0xea80, 0x0003); 3412 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); 3413 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); 3414 3415 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); 3416 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); 3417 r8168_mac_ocp_write(tp, 0xc094, 0x0000); 3418 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); 3419 3420 /* firmware is for MAC only */ 3421 r8169_apply_firmware(tp); 3422 3423 rtl_hw_aspm_clkreq_enable(tp, true); 3424 } 3425 3426 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) 3427 { 3428 static const struct ephy_info e_info_8102e_1[] = { 3429 { 0x01, 0, 0x6e65 }, 3430 { 0x02, 0, 0x091f }, 3431 { 0x03, 0, 0xc2f9 }, 3432 { 0x06, 0, 0xafb5 }, 3433 { 0x07, 0, 0x0e00 }, 3434 { 0x19, 0, 0xec80 }, 3435 { 0x01, 0, 0x2e65 }, 3436 { 0x01, 0, 0x6e65 } 3437 }; 3438 u8 cfg1; 3439 3440 rtl_set_def_aspm_entry_latency(tp); 3441 3442 RTL_W8(tp, DBG_REG, FIX_NAK_1); 3443 3444 RTL_W8(tp, Config1, 3445 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); 3446 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3447 3448 cfg1 = RTL_R8(tp, Config1); 3449 if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) 3450 RTL_W8(tp, Config1, cfg1 & ~LEDS0); 3451 3452 rtl_ephy_init(tp, e_info_8102e_1); 3453 } 3454 3455 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) 3456 { 3457 rtl_set_def_aspm_entry_latency(tp); 3458 3459 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); 3460 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); 3461 } 3462 3463 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp) 3464 { 3465 rtl_hw_start_8102e_2(tp); 3466 3467 rtl_ephy_write(tp, 0x03, 0xc2f9); 3468 } 3469 3470 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp) 3471 { 3472 static const struct ephy_info e_info_8105e_1[] = { 3473 { 0x07, 0, 0x4000 }, 3474 { 0x19, 0, 0x0200 }, 3475 { 0x19, 0, 0x0020 }, 3476 { 0x1e, 0, 0x2000 }, 3477 { 0x03, 0, 0x0001 }, 3478 { 0x19, 0, 0x0100 }, 3479 { 0x19, 0, 0x0004 }, 3480 { 0x0a, 0, 0x0020 } 3481 }; 3482 3483 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3484 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3485 3486 /* Disable Early Tally Counter */ 3487 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); 3488 3489 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3490 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); 3491 3492 rtl_ephy_init(tp, e_info_8105e_1); 3493 3494 rtl_pcie_state_l2l3_disable(tp); 3495 } 3496 3497 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp) 3498 { 3499 rtl_hw_start_8105e_1(tp); 3500 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); 3501 } 3502 3503 static void rtl_hw_start_8402(struct rtl8169_private *tp) 3504 { 3505 static const struct ephy_info e_info_8402[] = { 3506 { 0x19, 0xffff, 0xff64 }, 3507 { 0x1e, 0, 0x4000 } 3508 }; 3509 3510 rtl_set_def_aspm_entry_latency(tp); 3511 3512 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3513 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3514 3515 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 3516 3517 rtl_ephy_init(tp, e_info_8402); 3518 3519 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); 3520 rtl_reset_packet_filter(tp); 3521 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); 3522 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); 3523 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); 3524 3525 /* disable EEE */ 3526 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3527 3528 rtl_pcie_state_l2l3_disable(tp); 3529 } 3530 3531 static void rtl_hw_start_8106(struct rtl8169_private *tp) 3532 { 3533 rtl_hw_aspm_clkreq_enable(tp, false); 3534 3535 /* Force LAN exit from ASPM if Rx/Tx are not idle */ 3536 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); 3537 3538 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN); 3539 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); 3540 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); 3541 3542 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); 3543 3544 /* disable EEE */ 3545 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); 3546 3547 rtl_pcie_state_l2l3_disable(tp); 3548 rtl_hw_aspm_clkreq_enable(tp, true); 3549 } 3550 3551 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond) 3552 { 3553 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); 3554 } 3555 3556 static void rtl_hw_start_8125_common(struct rtl8169_private *tp) 3557 { 3558 rtl_pcie_state_l2l3_disable(tp); 3559 3560 RTL_W16(tp, 0x382, 0x221b); 3561 RTL_W8(tp, 0x4500, 0); 3562 RTL_W16(tp, 0x4800, 0); 3563 3564 /* disable UPS */ 3565 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); 3566 3567 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); 3568 3569 r8168_mac_ocp_write(tp, 0xc140, 0xffff); 3570 r8168_mac_ocp_write(tp, 0xc142, 0xffff); 3571 3572 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); 3573 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); 3574 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); 3575 3576 /* disable new tx descriptor format */ 3577 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); 3578 3579 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); 3580 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); 3581 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); 3582 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); 3583 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); 3584 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); 3585 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); 3586 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); 3587 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067); 3588 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00); 3589 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); 3590 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0); 3591 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); 3592 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); 3593 udelay(1); 3594 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); 3595 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); 3596 3597 r8168_mac_ocp_write(tp, 0xe098, 0xc302); 3598 3599 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10); 3600 3601 rtl8125_config_eee_mac(tp); 3602 3603 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN); 3604 udelay(10); 3605 } 3606 3607 static void rtl_hw_start_8125_1(struct rtl8169_private *tp) 3608 { 3609 static const struct ephy_info e_info_8125_1[] = { 3610 { 0x01, 0xffff, 0xa812 }, 3611 { 0x09, 0xffff, 0x520c }, 3612 { 0x04, 0xffff, 0xd000 }, 3613 { 0x0d, 0xffff, 0xf702 }, 3614 { 0x0a, 0xffff, 0x8653 }, 3615 { 0x06, 0xffff, 0x001e }, 3616 { 0x08, 0xffff, 0x3595 }, 3617 { 0x20, 0xffff, 0x9455 }, 3618 { 0x21, 0xffff, 0x99ff }, 3619 { 0x02, 0xffff, 0x6046 }, 3620 { 0x29, 0xffff, 0xfe00 }, 3621 { 0x23, 0xffff, 0xab62 }, 3622 3623 { 0x41, 0xffff, 0xa80c }, 3624 { 0x49, 0xffff, 0x520c }, 3625 { 0x44, 0xffff, 0xd000 }, 3626 { 0x4d, 0xffff, 0xf702 }, 3627 { 0x4a, 0xffff, 0x8653 }, 3628 { 0x46, 0xffff, 0x001e }, 3629 { 0x48, 0xffff, 0x3595 }, 3630 { 0x60, 0xffff, 0x9455 }, 3631 { 0x61, 0xffff, 0x99ff }, 3632 { 0x42, 0xffff, 0x6046 }, 3633 { 0x69, 0xffff, 0xfe00 }, 3634 { 0x63, 0xffff, 0xab62 }, 3635 }; 3636 3637 rtl_set_def_aspm_entry_latency(tp); 3638 3639 /* disable aspm and clock request before access ephy */ 3640 rtl_hw_aspm_clkreq_enable(tp, false); 3641 rtl_ephy_init(tp, e_info_8125_1); 3642 3643 rtl_hw_start_8125_common(tp); 3644 } 3645 3646 static void rtl_hw_start_8125_2(struct rtl8169_private *tp) 3647 { 3648 static const struct ephy_info e_info_8125_2[] = { 3649 { 0x04, 0xffff, 0xd000 }, 3650 { 0x0a, 0xffff, 0x8653 }, 3651 { 0x23, 0xffff, 0xab66 }, 3652 { 0x20, 0xffff, 0x9455 }, 3653 { 0x21, 0xffff, 0x99ff }, 3654 { 0x29, 0xffff, 0xfe04 }, 3655 3656 { 0x44, 0xffff, 0xd000 }, 3657 { 0x4a, 0xffff, 0x8653 }, 3658 { 0x63, 0xffff, 0xab66 }, 3659 { 0x60, 0xffff, 0x9455 }, 3660 { 0x61, 0xffff, 0x99ff }, 3661 { 0x69, 0xffff, 0xfe04 }, 3662 }; 3663 3664 rtl_set_def_aspm_entry_latency(tp); 3665 3666 /* disable aspm and clock request before access ephy */ 3667 rtl_hw_aspm_clkreq_enable(tp, false); 3668 rtl_ephy_init(tp, e_info_8125_2); 3669 3670 rtl_hw_start_8125_common(tp); 3671 } 3672 3673 static void rtl_hw_config(struct rtl8169_private *tp) 3674 { 3675 static const rtl_generic_fct hw_configs[] = { 3676 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1, 3677 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3, 3678 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2, 3679 [RTL_GIGA_MAC_VER_10] = NULL, 3680 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b, 3681 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b, 3682 [RTL_GIGA_MAC_VER_13] = NULL, 3683 [RTL_GIGA_MAC_VER_14] = NULL, 3684 [RTL_GIGA_MAC_VER_15] = NULL, 3685 [RTL_GIGA_MAC_VER_16] = NULL, 3686 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b, 3687 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1, 3688 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1, 3689 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2, 3690 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3, 3691 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4, 3692 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2, 3693 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3, 3694 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d, 3695 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d, 3696 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d, 3697 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4, 3698 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1, 3699 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2, 3700 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d, 3701 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1, 3702 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1, 3703 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2, 3704 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1, 3705 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1, 3706 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402, 3707 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411, 3708 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106, 3709 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1, 3710 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1, 3711 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2, 3712 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2, 3713 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2, 3714 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1, 3715 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1, 3716 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1, 3717 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1, 3718 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1, 3719 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2, 3720 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3, 3721 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117, 3722 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1, 3723 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2, 3724 }; 3725 3726 if (hw_configs[tp->mac_version]) 3727 hw_configs[tp->mac_version](tp); 3728 } 3729 3730 static void rtl_hw_start_8125(struct rtl8169_private *tp) 3731 { 3732 int i; 3733 3734 /* disable interrupt coalescing */ 3735 for (i = 0xa00; i < 0xb00; i += 4) 3736 RTL_W32(tp, i, 0); 3737 3738 rtl_hw_config(tp); 3739 } 3740 3741 static void rtl_hw_start_8168(struct rtl8169_private *tp) 3742 { 3743 if (rtl_is_8168evl_up(tp)) 3744 RTL_W8(tp, MaxTxPacketSize, EarlySize); 3745 else 3746 RTL_W8(tp, MaxTxPacketSize, TxPacketMax); 3747 3748 rtl_hw_config(tp); 3749 3750 /* disable interrupt coalescing */ 3751 RTL_W16(tp, IntrMitigate, 0x0000); 3752 } 3753 3754 static void rtl_hw_start_8169(struct rtl8169_private *tp) 3755 { 3756 RTL_W8(tp, EarlyTxThres, NoEarlyTx); 3757 3758 tp->cp_cmd |= PCIMulRW; 3759 3760 if (tp->mac_version == RTL_GIGA_MAC_VER_02 || 3761 tp->mac_version == RTL_GIGA_MAC_VER_03) 3762 tp->cp_cmd |= EnAnaPLL; 3763 3764 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3765 3766 rtl8169_set_magic_reg(tp); 3767 3768 /* disable interrupt coalescing */ 3769 RTL_W16(tp, IntrMitigate, 0x0000); 3770 } 3771 3772 static void rtl_hw_start(struct rtl8169_private *tp) 3773 { 3774 rtl_unlock_config_regs(tp); 3775 3776 RTL_W16(tp, CPlusCmd, tp->cp_cmd); 3777 3778 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 3779 rtl_hw_start_8169(tp); 3780 else if (rtl_is_8125(tp)) 3781 rtl_hw_start_8125(tp); 3782 else 3783 rtl_hw_start_8168(tp); 3784 3785 rtl_set_rx_max_size(tp); 3786 rtl_set_rx_tx_desc_registers(tp); 3787 rtl_lock_config_regs(tp); 3788 3789 rtl_jumbo_config(tp); 3790 3791 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ 3792 rtl_pci_commit(tp); 3793 3794 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb); 3795 rtl_init_rxcfg(tp); 3796 rtl_set_tx_config_registers(tp); 3797 rtl_set_rx_config_features(tp, tp->dev->features); 3798 rtl_set_rx_mode(tp->dev); 3799 rtl_irq_enable(tp); 3800 } 3801 3802 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) 3803 { 3804 struct rtl8169_private *tp = netdev_priv(dev); 3805 3806 dev->mtu = new_mtu; 3807 netdev_update_features(dev); 3808 rtl_jumbo_config(tp); 3809 3810 return 0; 3811 } 3812 3813 static void rtl8169_mark_to_asic(struct RxDesc *desc) 3814 { 3815 u32 eor = le32_to_cpu(desc->opts1) & RingEnd; 3816 3817 desc->opts2 = 0; 3818 /* Force memory writes to complete before releasing descriptor */ 3819 dma_wmb(); 3820 WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE)); 3821 } 3822 3823 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp, 3824 struct RxDesc *desc) 3825 { 3826 struct device *d = tp_to_dev(tp); 3827 int node = dev_to_node(d); 3828 dma_addr_t mapping; 3829 struct page *data; 3830 3831 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE)); 3832 if (!data) 3833 return NULL; 3834 3835 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3836 if (unlikely(dma_mapping_error(d, mapping))) { 3837 netdev_err(tp->dev, "Failed to map RX DMA!\n"); 3838 __free_pages(data, get_order(R8169_RX_BUF_SIZE)); 3839 return NULL; 3840 } 3841 3842 desc->addr = cpu_to_le64(mapping); 3843 rtl8169_mark_to_asic(desc); 3844 3845 return data; 3846 } 3847 3848 static void rtl8169_rx_clear(struct rtl8169_private *tp) 3849 { 3850 unsigned int i; 3851 3852 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { 3853 dma_unmap_page(tp_to_dev(tp), 3854 le64_to_cpu(tp->RxDescArray[i].addr), 3855 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); 3856 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE)); 3857 tp->Rx_databuff[i] = NULL; 3858 tp->RxDescArray[i].addr = 0; 3859 tp->RxDescArray[i].opts1 = 0; 3860 } 3861 } 3862 3863 static int rtl8169_rx_fill(struct rtl8169_private *tp) 3864 { 3865 unsigned int i; 3866 3867 for (i = 0; i < NUM_RX_DESC; i++) { 3868 struct page *data; 3869 3870 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); 3871 if (!data) { 3872 rtl8169_rx_clear(tp); 3873 return -ENOMEM; 3874 } 3875 tp->Rx_databuff[i] = data; 3876 } 3877 3878 /* mark as last descriptor in the ring */ 3879 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd); 3880 3881 return 0; 3882 } 3883 3884 static int rtl8169_init_ring(struct rtl8169_private *tp) 3885 { 3886 rtl8169_init_ring_indexes(tp); 3887 3888 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); 3889 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); 3890 3891 return rtl8169_rx_fill(tp); 3892 } 3893 3894 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry) 3895 { 3896 struct ring_info *tx_skb = tp->tx_skb + entry; 3897 struct TxDesc *desc = tp->TxDescArray + entry; 3898 3899 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len, 3900 DMA_TO_DEVICE); 3901 memset(desc, 0, sizeof(*desc)); 3902 memset(tx_skb, 0, sizeof(*tx_skb)); 3903 } 3904 3905 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, 3906 unsigned int n) 3907 { 3908 unsigned int i; 3909 3910 for (i = 0; i < n; i++) { 3911 unsigned int entry = (start + i) % NUM_TX_DESC; 3912 struct ring_info *tx_skb = tp->tx_skb + entry; 3913 unsigned int len = tx_skb->len; 3914 3915 if (len) { 3916 struct sk_buff *skb = tx_skb->skb; 3917 3918 rtl8169_unmap_tx_skb(tp, entry); 3919 if (skb) 3920 dev_consume_skb_any(skb); 3921 } 3922 } 3923 } 3924 3925 static void rtl8169_tx_clear(struct rtl8169_private *tp) 3926 { 3927 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); 3928 netdev_reset_queue(tp->dev); 3929 } 3930 3931 static void rtl8169_hw_reset(struct rtl8169_private *tp, bool going_down) 3932 { 3933 /* Give a racing hard_start_xmit a few cycles to complete. */ 3934 synchronize_rcu(); 3935 3936 /* Disable interrupts */ 3937 rtl8169_irq_mask_and_ack(tp); 3938 3939 rtl_rx_close(tp); 3940 3941 if (going_down && tp->dev->wol_enabled) 3942 goto no_reset; 3943 3944 switch (tp->mac_version) { 3945 case RTL_GIGA_MAC_VER_27: 3946 case RTL_GIGA_MAC_VER_28: 3947 case RTL_GIGA_MAC_VER_31: 3948 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000); 3949 break; 3950 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38: 3951 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3952 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666); 3953 break; 3954 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61: 3955 rtl_enable_rxdvgate(tp); 3956 fsleep(2000); 3957 break; 3958 default: 3959 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); 3960 fsleep(100); 3961 break; 3962 } 3963 3964 rtl_hw_reset(tp); 3965 no_reset: 3966 rtl8169_tx_clear(tp); 3967 rtl8169_init_ring_indexes(tp); 3968 } 3969 3970 static void rtl_reset_work(struct rtl8169_private *tp) 3971 { 3972 struct net_device *dev = tp->dev; 3973 int i; 3974 3975 napi_disable(&tp->napi); 3976 netif_stop_queue(dev); 3977 3978 rtl8169_hw_reset(tp, false); 3979 3980 for (i = 0; i < NUM_RX_DESC; i++) 3981 rtl8169_mark_to_asic(tp->RxDescArray + i); 3982 3983 napi_enable(&tp->napi); 3984 rtl_hw_start(tp); 3985 netif_wake_queue(dev); 3986 } 3987 3988 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue) 3989 { 3990 struct rtl8169_private *tp = netdev_priv(dev); 3991 3992 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 3993 } 3994 3995 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len, 3996 void *addr, unsigned int entry, bool desc_own) 3997 { 3998 struct TxDesc *txd = tp->TxDescArray + entry; 3999 struct device *d = tp_to_dev(tp); 4000 dma_addr_t mapping; 4001 u32 opts1; 4002 int ret; 4003 4004 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); 4005 ret = dma_mapping_error(d, mapping); 4006 if (unlikely(ret)) { 4007 if (net_ratelimit()) 4008 netdev_err(tp->dev, "Failed to map TX data!\n"); 4009 return ret; 4010 } 4011 4012 txd->addr = cpu_to_le64(mapping); 4013 txd->opts2 = cpu_to_le32(opts[1]); 4014 4015 opts1 = opts[0] | len; 4016 if (entry == NUM_TX_DESC - 1) 4017 opts1 |= RingEnd; 4018 if (desc_own) 4019 opts1 |= DescOwn; 4020 txd->opts1 = cpu_to_le32(opts1); 4021 4022 tp->tx_skb[entry].len = len; 4023 4024 return 0; 4025 } 4026 4027 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, 4028 const u32 *opts, unsigned int entry) 4029 { 4030 struct skb_shared_info *info = skb_shinfo(skb); 4031 unsigned int cur_frag; 4032 4033 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { 4034 const skb_frag_t *frag = info->frags + cur_frag; 4035 void *addr = skb_frag_address(frag); 4036 u32 len = skb_frag_size(frag); 4037 4038 entry = (entry + 1) % NUM_TX_DESC; 4039 4040 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true))) 4041 goto err_out; 4042 } 4043 4044 return 0; 4045 4046 err_out: 4047 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); 4048 return -EIO; 4049 } 4050 4051 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb) 4052 { 4053 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34; 4054 } 4055 4056 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts) 4057 { 4058 u32 mss = skb_shinfo(skb)->gso_size; 4059 4060 if (mss) { 4061 opts[0] |= TD_LSO; 4062 opts[0] |= mss << TD0_MSS_SHIFT; 4063 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4064 const struct iphdr *ip = ip_hdr(skb); 4065 4066 if (ip->protocol == IPPROTO_TCP) 4067 opts[0] |= TD0_IP_CS | TD0_TCP_CS; 4068 else if (ip->protocol == IPPROTO_UDP) 4069 opts[0] |= TD0_IP_CS | TD0_UDP_CS; 4070 else 4071 WARN_ON_ONCE(1); 4072 } 4073 } 4074 4075 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp, 4076 struct sk_buff *skb, u32 *opts) 4077 { 4078 u32 transport_offset = (u32)skb_transport_offset(skb); 4079 struct skb_shared_info *shinfo = skb_shinfo(skb); 4080 u32 mss = shinfo->gso_size; 4081 4082 if (mss) { 4083 if (shinfo->gso_type & SKB_GSO_TCPV4) { 4084 opts[0] |= TD1_GTSENV4; 4085 } else if (shinfo->gso_type & SKB_GSO_TCPV6) { 4086 if (skb_cow_head(skb, 0)) 4087 return false; 4088 4089 tcp_v6_gso_csum_prep(skb); 4090 opts[0] |= TD1_GTSENV6; 4091 } else { 4092 WARN_ON_ONCE(1); 4093 } 4094 4095 opts[0] |= transport_offset << GTTCPHO_SHIFT; 4096 opts[1] |= mss << TD1_MSS_SHIFT; 4097 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4098 u8 ip_protocol; 4099 4100 switch (vlan_get_protocol(skb)) { 4101 case htons(ETH_P_IP): 4102 opts[1] |= TD1_IPv4_CS; 4103 ip_protocol = ip_hdr(skb)->protocol; 4104 break; 4105 4106 case htons(ETH_P_IPV6): 4107 opts[1] |= TD1_IPv6_CS; 4108 ip_protocol = ipv6_hdr(skb)->nexthdr; 4109 break; 4110 4111 default: 4112 ip_protocol = IPPROTO_RAW; 4113 break; 4114 } 4115 4116 if (ip_protocol == IPPROTO_TCP) 4117 opts[1] |= TD1_TCP_CS; 4118 else if (ip_protocol == IPPROTO_UDP) 4119 opts[1] |= TD1_UDP_CS; 4120 else 4121 WARN_ON_ONCE(1); 4122 4123 opts[1] |= transport_offset << TCPHO_SHIFT; 4124 } else { 4125 if (unlikely(rtl_test_hw_pad_bug(tp, skb))) 4126 return !eth_skb_pad(skb); 4127 } 4128 4129 return true; 4130 } 4131 4132 static bool rtl_tx_slots_avail(struct rtl8169_private *tp, 4133 unsigned int nr_frags) 4134 { 4135 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx; 4136 4137 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */ 4138 return slots_avail > nr_frags; 4139 } 4140 4141 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */ 4142 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp) 4143 { 4144 switch (tp->mac_version) { 4145 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 4146 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17: 4147 return false; 4148 default: 4149 return true; 4150 } 4151 } 4152 4153 static void rtl8169_doorbell(struct rtl8169_private *tp) 4154 { 4155 if (rtl_is_8125(tp)) 4156 RTL_W16(tp, TxPoll_8125, BIT(0)); 4157 else 4158 RTL_W8(tp, TxPoll, NPQ); 4159 } 4160 4161 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, 4162 struct net_device *dev) 4163 { 4164 unsigned int frags = skb_shinfo(skb)->nr_frags; 4165 struct rtl8169_private *tp = netdev_priv(dev); 4166 unsigned int entry = tp->cur_tx % NUM_TX_DESC; 4167 struct TxDesc *txd_first, *txd_last; 4168 bool stop_queue, door_bell; 4169 u32 opts[2]; 4170 4171 txd_first = tp->TxDescArray + entry; 4172 4173 if (unlikely(!rtl_tx_slots_avail(tp, frags))) { 4174 if (net_ratelimit()) 4175 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 4176 goto err_stop_0; 4177 } 4178 4179 if (unlikely(le32_to_cpu(txd_first->opts1) & DescOwn)) 4180 goto err_stop_0; 4181 4182 opts[1] = rtl8169_tx_vlan_tag(skb); 4183 opts[0] = 0; 4184 4185 if (!rtl_chip_supports_csum_v2(tp)) 4186 rtl8169_tso_csum_v1(skb, opts); 4187 else if (!rtl8169_tso_csum_v2(tp, skb, opts)) 4188 goto err_dma_0; 4189 4190 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data, 4191 entry, false))) 4192 goto err_dma_0; 4193 4194 if (frags) { 4195 if (rtl8169_xmit_frags(tp, skb, opts, entry)) 4196 goto err_dma_1; 4197 entry = (entry + frags) % NUM_TX_DESC; 4198 } 4199 4200 txd_last = tp->TxDescArray + entry; 4201 txd_last->opts1 |= cpu_to_le32(LastFrag); 4202 tp->tx_skb[entry].skb = skb; 4203 4204 skb_tx_timestamp(skb); 4205 4206 /* Force memory writes to complete before releasing descriptor */ 4207 dma_wmb(); 4208 4209 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more()); 4210 4211 txd_first->opts1 |= cpu_to_le32(DescOwn | FirstFrag); 4212 4213 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */ 4214 smp_wmb(); 4215 4216 tp->cur_tx += frags + 1; 4217 4218 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS); 4219 if (unlikely(stop_queue)) { 4220 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must 4221 * not miss a ring update when it notices a stopped queue. 4222 */ 4223 smp_wmb(); 4224 netif_stop_queue(dev); 4225 door_bell = true; 4226 } 4227 4228 if (door_bell) 4229 rtl8169_doorbell(tp); 4230 4231 if (unlikely(stop_queue)) { 4232 /* Sync with rtl_tx: 4233 * - publish queue status and cur_tx ring index (write barrier) 4234 * - refresh dirty_tx ring index (read barrier). 4235 * May the current thread have a pessimistic view of the ring 4236 * status and forget to wake up queue, a racing rtl_tx thread 4237 * can't. 4238 */ 4239 smp_mb(); 4240 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) 4241 netif_start_queue(dev); 4242 } 4243 4244 return NETDEV_TX_OK; 4245 4246 err_dma_1: 4247 rtl8169_unmap_tx_skb(tp, entry); 4248 err_dma_0: 4249 dev_kfree_skb_any(skb); 4250 dev->stats.tx_dropped++; 4251 return NETDEV_TX_OK; 4252 4253 err_stop_0: 4254 netif_stop_queue(dev); 4255 dev->stats.tx_dropped++; 4256 return NETDEV_TX_BUSY; 4257 } 4258 4259 static unsigned int rtl_last_frag_len(struct sk_buff *skb) 4260 { 4261 struct skb_shared_info *info = skb_shinfo(skb); 4262 unsigned int nr_frags = info->nr_frags; 4263 4264 if (!nr_frags) 4265 return UINT_MAX; 4266 4267 return skb_frag_size(info->frags + nr_frags - 1); 4268 } 4269 4270 /* Workaround for hw issues with TSO on RTL8168evl */ 4271 static netdev_features_t rtl8168evl_fix_tso(struct sk_buff *skb, 4272 netdev_features_t features) 4273 { 4274 /* IPv4 header has options field */ 4275 if (vlan_get_protocol(skb) == htons(ETH_P_IP) && 4276 ip_hdrlen(skb) > sizeof(struct iphdr)) 4277 features &= ~NETIF_F_ALL_TSO; 4278 4279 /* IPv4 TCP header has options field */ 4280 else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4 && 4281 tcp_hdrlen(skb) > sizeof(struct tcphdr)) 4282 features &= ~NETIF_F_ALL_TSO; 4283 4284 else if (rtl_last_frag_len(skb) <= 6) 4285 features &= ~NETIF_F_ALL_TSO; 4286 4287 return features; 4288 } 4289 4290 static netdev_features_t rtl8169_features_check(struct sk_buff *skb, 4291 struct net_device *dev, 4292 netdev_features_t features) 4293 { 4294 int transport_offset = skb_transport_offset(skb); 4295 struct rtl8169_private *tp = netdev_priv(dev); 4296 4297 if (skb_is_gso(skb)) { 4298 if (tp->mac_version == RTL_GIGA_MAC_VER_34) 4299 features = rtl8168evl_fix_tso(skb, features); 4300 4301 if (transport_offset > GTTCPHO_MAX && 4302 rtl_chip_supports_csum_v2(tp)) 4303 features &= ~NETIF_F_ALL_TSO; 4304 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 4305 if (skb->len < ETH_ZLEN) { 4306 switch (tp->mac_version) { 4307 case RTL_GIGA_MAC_VER_11: 4308 case RTL_GIGA_MAC_VER_12: 4309 case RTL_GIGA_MAC_VER_17: 4310 case RTL_GIGA_MAC_VER_34: 4311 features &= ~NETIF_F_CSUM_MASK; 4312 break; 4313 default: 4314 break; 4315 } 4316 } 4317 4318 if (transport_offset > TCPHO_MAX && 4319 rtl_chip_supports_csum_v2(tp)) 4320 features &= ~NETIF_F_CSUM_MASK; 4321 } 4322 4323 return vlan_features_check(skb, features); 4324 } 4325 4326 static void rtl8169_pcierr_interrupt(struct net_device *dev) 4327 { 4328 struct rtl8169_private *tp = netdev_priv(dev); 4329 struct pci_dev *pdev = tp->pci_dev; 4330 int pci_status_errs; 4331 u16 pci_cmd; 4332 4333 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4334 4335 pci_status_errs = pci_status_get_and_clear_errors(pdev); 4336 4337 if (net_ratelimit()) 4338 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", 4339 pci_cmd, pci_status_errs); 4340 /* 4341 * The recovery sequence below admits a very elaborated explanation: 4342 * - it seems to work; 4343 * - I did not see what else could be done; 4344 * - it makes iop3xx happy. 4345 * 4346 * Feel free to adjust to your needs. 4347 */ 4348 if (pdev->broken_parity_status) 4349 pci_cmd &= ~PCI_COMMAND_PARITY; 4350 else 4351 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; 4352 4353 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4354 4355 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4356 } 4357 4358 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp, 4359 int budget) 4360 { 4361 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0; 4362 4363 dirty_tx = tp->dirty_tx; 4364 smp_rmb(); 4365 4366 for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) { 4367 unsigned int entry = dirty_tx % NUM_TX_DESC; 4368 struct sk_buff *skb = tp->tx_skb[entry].skb; 4369 u32 status; 4370 4371 status = le32_to_cpu(tp->TxDescArray[entry].opts1); 4372 if (status & DescOwn) 4373 break; 4374 4375 rtl8169_unmap_tx_skb(tp, entry); 4376 4377 if (skb) { 4378 pkts_compl++; 4379 bytes_compl += skb->len; 4380 napi_consume_skb(skb, budget); 4381 } 4382 dirty_tx++; 4383 } 4384 4385 if (tp->dirty_tx != dirty_tx) { 4386 netdev_completed_queue(dev, pkts_compl, bytes_compl); 4387 4388 u64_stats_update_begin(&tp->tx_stats.syncp); 4389 tp->tx_stats.packets += pkts_compl; 4390 tp->tx_stats.bytes += bytes_compl; 4391 u64_stats_update_end(&tp->tx_stats.syncp); 4392 4393 tp->dirty_tx = dirty_tx; 4394 /* Sync with rtl8169_start_xmit: 4395 * - publish dirty_tx ring index (write barrier) 4396 * - refresh cur_tx ring index and queue status (read barrier) 4397 * May the current thread miss the stopped queue condition, 4398 * a racing xmit thread can only have a right view of the 4399 * ring status. 4400 */ 4401 smp_mb(); 4402 if (netif_queue_stopped(dev) && 4403 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) { 4404 netif_wake_queue(dev); 4405 } 4406 /* 4407 * 8168 hack: TxPoll requests are lost when the Tx packets are 4408 * too close. Let's kick an extra TxPoll request when a burst 4409 * of start_xmit activity is detected (if it is not detected, 4410 * it is slow enough). -- FR 4411 */ 4412 if (tp->cur_tx != dirty_tx) 4413 rtl8169_doorbell(tp); 4414 } 4415 } 4416 4417 static inline int rtl8169_fragmented_frame(u32 status) 4418 { 4419 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); 4420 } 4421 4422 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) 4423 { 4424 u32 status = opts1 & RxProtoMask; 4425 4426 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || 4427 ((status == RxProtoUDP) && !(opts1 & UDPFail))) 4428 skb->ip_summed = CHECKSUM_UNNECESSARY; 4429 else 4430 skb_checksum_none_assert(skb); 4431 } 4432 4433 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget) 4434 { 4435 unsigned int cur_rx, rx_left, count; 4436 struct device *d = tp_to_dev(tp); 4437 4438 cur_rx = tp->cur_rx; 4439 4440 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) { 4441 unsigned int pkt_size, entry = cur_rx % NUM_RX_DESC; 4442 struct RxDesc *desc = tp->RxDescArray + entry; 4443 struct sk_buff *skb; 4444 const void *rx_buf; 4445 dma_addr_t addr; 4446 u32 status; 4447 4448 status = le32_to_cpu(desc->opts1); 4449 if (status & DescOwn) 4450 break; 4451 4452 /* This barrier is needed to keep us from reading 4453 * any other fields out of the Rx descriptor until 4454 * we know the status of DescOwn 4455 */ 4456 dma_rmb(); 4457 4458 if (unlikely(status & RxRES)) { 4459 if (net_ratelimit()) 4460 netdev_warn(dev, "Rx ERROR. status = %08x\n", 4461 status); 4462 dev->stats.rx_errors++; 4463 if (status & (RxRWT | RxRUNT)) 4464 dev->stats.rx_length_errors++; 4465 if (status & RxCRC) 4466 dev->stats.rx_crc_errors++; 4467 4468 if (!(dev->features & NETIF_F_RXALL)) 4469 goto release_descriptor; 4470 else if (status & RxRWT || !(status & (RxRUNT | RxCRC))) 4471 goto release_descriptor; 4472 } 4473 4474 pkt_size = status & GENMASK(13, 0); 4475 if (likely(!(dev->features & NETIF_F_RXFCS))) 4476 pkt_size -= ETH_FCS_LEN; 4477 4478 /* The driver does not support incoming fragmented frames. 4479 * They are seen as a symptom of over-mtu sized frames. 4480 */ 4481 if (unlikely(rtl8169_fragmented_frame(status))) { 4482 dev->stats.rx_dropped++; 4483 dev->stats.rx_length_errors++; 4484 goto release_descriptor; 4485 } 4486 4487 skb = napi_alloc_skb(&tp->napi, pkt_size); 4488 if (unlikely(!skb)) { 4489 dev->stats.rx_dropped++; 4490 goto release_descriptor; 4491 } 4492 4493 addr = le64_to_cpu(desc->addr); 4494 rx_buf = page_address(tp->Rx_databuff[entry]); 4495 4496 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); 4497 prefetch(rx_buf); 4498 skb_copy_to_linear_data(skb, rx_buf, pkt_size); 4499 skb->tail += pkt_size; 4500 skb->len = pkt_size; 4501 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); 4502 4503 rtl8169_rx_csum(skb, status); 4504 skb->protocol = eth_type_trans(skb, dev); 4505 4506 rtl8169_rx_vlan_tag(desc, skb); 4507 4508 if (skb->pkt_type == PACKET_MULTICAST) 4509 dev->stats.multicast++; 4510 4511 napi_gro_receive(&tp->napi, skb); 4512 4513 u64_stats_update_begin(&tp->rx_stats.syncp); 4514 tp->rx_stats.packets++; 4515 tp->rx_stats.bytes += pkt_size; 4516 u64_stats_update_end(&tp->rx_stats.syncp); 4517 4518 release_descriptor: 4519 rtl8169_mark_to_asic(desc); 4520 } 4521 4522 count = cur_rx - tp->cur_rx; 4523 tp->cur_rx = cur_rx; 4524 4525 return count; 4526 } 4527 4528 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) 4529 { 4530 struct rtl8169_private *tp = dev_instance; 4531 u32 status = rtl_get_events(tp); 4532 4533 if (!tp->irq_enabled || (status & 0xffff) == 0xffff || 4534 !(status & tp->irq_mask)) 4535 return IRQ_NONE; 4536 4537 if (unlikely(status & SYSErr)) { 4538 rtl8169_pcierr_interrupt(tp->dev); 4539 goto out; 4540 } 4541 4542 if (status & LinkChg) 4543 phy_mac_interrupt(tp->phydev); 4544 4545 if (unlikely(status & RxFIFOOver && 4546 tp->mac_version == RTL_GIGA_MAC_VER_11)) { 4547 netif_stop_queue(tp->dev); 4548 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING); 4549 } 4550 4551 rtl_irq_disable(tp); 4552 napi_schedule_irqoff(&tp->napi); 4553 out: 4554 rtl_ack_events(tp, status); 4555 4556 return IRQ_HANDLED; 4557 } 4558 4559 static void rtl_task(struct work_struct *work) 4560 { 4561 struct rtl8169_private *tp = 4562 container_of(work, struct rtl8169_private, wk.work); 4563 4564 rtl_lock_work(tp); 4565 4566 if (!netif_running(tp->dev) || 4567 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags)) 4568 goto out_unlock; 4569 4570 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) 4571 rtl_reset_work(tp); 4572 out_unlock: 4573 rtl_unlock_work(tp); 4574 } 4575 4576 static int rtl8169_poll(struct napi_struct *napi, int budget) 4577 { 4578 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); 4579 struct net_device *dev = tp->dev; 4580 int work_done; 4581 4582 work_done = rtl_rx(dev, tp, (u32) budget); 4583 4584 rtl_tx(dev, tp, budget); 4585 4586 if (work_done < budget) { 4587 napi_complete_done(napi, work_done); 4588 rtl_irq_enable(tp); 4589 } 4590 4591 return work_done; 4592 } 4593 4594 static void r8169_phylink_handler(struct net_device *ndev) 4595 { 4596 struct rtl8169_private *tp = netdev_priv(ndev); 4597 4598 if (netif_carrier_ok(ndev)) { 4599 rtl_link_chg_patch(tp); 4600 pm_request_resume(&tp->pci_dev->dev); 4601 } else { 4602 pm_runtime_idle(&tp->pci_dev->dev); 4603 } 4604 4605 if (net_ratelimit()) 4606 phy_print_status(tp->phydev); 4607 } 4608 4609 static int r8169_phy_connect(struct rtl8169_private *tp) 4610 { 4611 struct phy_device *phydev = tp->phydev; 4612 phy_interface_t phy_mode; 4613 int ret; 4614 4615 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII : 4616 PHY_INTERFACE_MODE_MII; 4617 4618 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler, 4619 phy_mode); 4620 if (ret) 4621 return ret; 4622 4623 if (!tp->supports_gmii) 4624 phy_set_max_speed(phydev, SPEED_100); 4625 4626 phy_support_asym_pause(phydev); 4627 4628 phy_attached_info(phydev); 4629 4630 return 0; 4631 } 4632 4633 static void rtl8169_down(struct rtl8169_private *tp) 4634 { 4635 rtl_lock_work(tp); 4636 4637 /* Clear all task flags */ 4638 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX); 4639 4640 phy_stop(tp->phydev); 4641 napi_disable(&tp->napi); 4642 4643 rtl8169_hw_reset(tp, true); 4644 4645 rtl_pll_power_down(tp); 4646 4647 rtl_unlock_work(tp); 4648 } 4649 4650 static int rtl8169_close(struct net_device *dev) 4651 { 4652 struct rtl8169_private *tp = netdev_priv(dev); 4653 struct pci_dev *pdev = tp->pci_dev; 4654 4655 pm_runtime_get_sync(&pdev->dev); 4656 4657 /* Update counters before going down */ 4658 rtl8169_update_counters(tp); 4659 4660 netif_stop_queue(dev); 4661 rtl8169_down(tp); 4662 rtl8169_rx_clear(tp); 4663 4664 cancel_work_sync(&tp->wk.work); 4665 4666 phy_disconnect(tp->phydev); 4667 4668 pci_free_irq(pdev, 0, tp); 4669 4670 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4671 tp->RxPhyAddr); 4672 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4673 tp->TxPhyAddr); 4674 tp->TxDescArray = NULL; 4675 tp->RxDescArray = NULL; 4676 4677 pm_runtime_put_sync(&pdev->dev); 4678 4679 return 0; 4680 } 4681 4682 #ifdef CONFIG_NET_POLL_CONTROLLER 4683 static void rtl8169_netpoll(struct net_device *dev) 4684 { 4685 struct rtl8169_private *tp = netdev_priv(dev); 4686 4687 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp); 4688 } 4689 #endif 4690 4691 static int rtl_open(struct net_device *dev) 4692 { 4693 struct rtl8169_private *tp = netdev_priv(dev); 4694 struct pci_dev *pdev = tp->pci_dev; 4695 int retval = -ENOMEM; 4696 4697 pm_runtime_get_sync(&pdev->dev); 4698 4699 /* 4700 * Rx and Tx descriptors needs 256 bytes alignment. 4701 * dma_alloc_coherent provides more. 4702 */ 4703 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, 4704 &tp->TxPhyAddr, GFP_KERNEL); 4705 if (!tp->TxDescArray) 4706 goto err_pm_runtime_put; 4707 4708 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, 4709 &tp->RxPhyAddr, GFP_KERNEL); 4710 if (!tp->RxDescArray) 4711 goto err_free_tx_0; 4712 4713 retval = rtl8169_init_ring(tp); 4714 if (retval < 0) 4715 goto err_free_rx_1; 4716 4717 rtl_request_firmware(tp); 4718 4719 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp, 4720 dev->name); 4721 if (retval < 0) 4722 goto err_release_fw_2; 4723 4724 retval = r8169_phy_connect(tp); 4725 if (retval) 4726 goto err_free_irq; 4727 4728 rtl_lock_work(tp); 4729 4730 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4731 4732 napi_enable(&tp->napi); 4733 4734 rtl8169_init_phy(tp); 4735 4736 rtl_pll_power_up(tp); 4737 4738 rtl_hw_start(tp); 4739 4740 rtl8169_init_counter_offsets(tp); 4741 4742 phy_start(tp->phydev); 4743 netif_start_queue(dev); 4744 4745 rtl_unlock_work(tp); 4746 4747 pm_runtime_put_sync(&pdev->dev); 4748 out: 4749 return retval; 4750 4751 err_free_irq: 4752 pci_free_irq(pdev, 0, tp); 4753 err_release_fw_2: 4754 rtl_release_firmware(tp); 4755 rtl8169_rx_clear(tp); 4756 err_free_rx_1: 4757 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, 4758 tp->RxPhyAddr); 4759 tp->RxDescArray = NULL; 4760 err_free_tx_0: 4761 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, 4762 tp->TxPhyAddr); 4763 tp->TxDescArray = NULL; 4764 err_pm_runtime_put: 4765 pm_runtime_put_noidle(&pdev->dev); 4766 goto out; 4767 } 4768 4769 static void 4770 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 4771 { 4772 struct rtl8169_private *tp = netdev_priv(dev); 4773 struct pci_dev *pdev = tp->pci_dev; 4774 struct rtl8169_counters *counters = tp->counters; 4775 unsigned int start; 4776 4777 pm_runtime_get_noresume(&pdev->dev); 4778 4779 netdev_stats_to_stats64(stats, &dev->stats); 4780 4781 do { 4782 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp); 4783 stats->rx_packets = tp->rx_stats.packets; 4784 stats->rx_bytes = tp->rx_stats.bytes; 4785 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start)); 4786 4787 do { 4788 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp); 4789 stats->tx_packets = tp->tx_stats.packets; 4790 stats->tx_bytes = tp->tx_stats.bytes; 4791 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start)); 4792 4793 /* 4794 * Fetch additional counter values missing in stats collected by driver 4795 * from tally counters. 4796 */ 4797 if (pm_runtime_active(&pdev->dev)) 4798 rtl8169_update_counters(tp); 4799 4800 /* 4801 * Subtract values fetched during initalization. 4802 * See rtl8169_init_counter_offsets for a description why we do that. 4803 */ 4804 stats->tx_errors = le64_to_cpu(counters->tx_errors) - 4805 le64_to_cpu(tp->tc_offset.tx_errors); 4806 stats->collisions = le32_to_cpu(counters->tx_multi_collision) - 4807 le32_to_cpu(tp->tc_offset.tx_multi_collision); 4808 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) - 4809 le16_to_cpu(tp->tc_offset.tx_aborted); 4810 stats->rx_missed_errors = le16_to_cpu(counters->rx_missed) - 4811 le16_to_cpu(tp->tc_offset.rx_missed); 4812 4813 pm_runtime_put_noidle(&pdev->dev); 4814 } 4815 4816 static void rtl8169_net_suspend(struct rtl8169_private *tp) 4817 { 4818 if (!netif_running(tp->dev)) 4819 return; 4820 4821 netif_device_detach(tp->dev); 4822 rtl8169_down(tp); 4823 } 4824 4825 #ifdef CONFIG_PM 4826 4827 static int __maybe_unused rtl8169_suspend(struct device *device) 4828 { 4829 struct rtl8169_private *tp = dev_get_drvdata(device); 4830 4831 rtl8169_net_suspend(tp); 4832 clk_disable_unprepare(tp->clk); 4833 4834 return 0; 4835 } 4836 4837 static void __rtl8169_resume(struct rtl8169_private *tp) 4838 { 4839 netif_device_attach(tp->dev); 4840 4841 rtl_pll_power_up(tp); 4842 rtl8169_init_phy(tp); 4843 4844 phy_start(tp->phydev); 4845 4846 rtl_lock_work(tp); 4847 napi_enable(&tp->napi); 4848 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags); 4849 rtl_reset_work(tp); 4850 rtl_unlock_work(tp); 4851 } 4852 4853 static int __maybe_unused rtl8169_resume(struct device *device) 4854 { 4855 struct rtl8169_private *tp = dev_get_drvdata(device); 4856 4857 rtl_rar_set(tp, tp->dev->dev_addr); 4858 4859 clk_prepare_enable(tp->clk); 4860 4861 if (netif_running(tp->dev)) 4862 __rtl8169_resume(tp); 4863 4864 return 0; 4865 } 4866 4867 static int rtl8169_runtime_suspend(struct device *device) 4868 { 4869 struct rtl8169_private *tp = dev_get_drvdata(device); 4870 4871 if (!tp->TxDescArray) 4872 return 0; 4873 4874 rtl_lock_work(tp); 4875 __rtl8169_set_wol(tp, WAKE_PHY); 4876 rtl_unlock_work(tp); 4877 4878 rtl8169_net_suspend(tp); 4879 4880 /* Update counters before going runtime suspend */ 4881 rtl8169_update_counters(tp); 4882 4883 return 0; 4884 } 4885 4886 static int rtl8169_runtime_resume(struct device *device) 4887 { 4888 struct rtl8169_private *tp = dev_get_drvdata(device); 4889 4890 rtl_rar_set(tp, tp->dev->dev_addr); 4891 4892 if (!tp->TxDescArray) 4893 return 0; 4894 4895 rtl_lock_work(tp); 4896 __rtl8169_set_wol(tp, tp->saved_wolopts); 4897 rtl_unlock_work(tp); 4898 4899 __rtl8169_resume(tp); 4900 4901 return 0; 4902 } 4903 4904 static int rtl8169_runtime_idle(struct device *device) 4905 { 4906 struct rtl8169_private *tp = dev_get_drvdata(device); 4907 4908 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev)) 4909 pm_schedule_suspend(device, 10000); 4910 4911 return -EBUSY; 4912 } 4913 4914 static const struct dev_pm_ops rtl8169_pm_ops = { 4915 SET_SYSTEM_SLEEP_PM_OPS(rtl8169_suspend, rtl8169_resume) 4916 SET_RUNTIME_PM_OPS(rtl8169_runtime_suspend, rtl8169_runtime_resume, 4917 rtl8169_runtime_idle) 4918 }; 4919 4920 #endif /* CONFIG_PM */ 4921 4922 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) 4923 { 4924 /* WoL fails with 8168b when the receiver is disabled. */ 4925 switch (tp->mac_version) { 4926 case RTL_GIGA_MAC_VER_11: 4927 case RTL_GIGA_MAC_VER_12: 4928 case RTL_GIGA_MAC_VER_17: 4929 pci_clear_master(tp->pci_dev); 4930 4931 RTL_W8(tp, ChipCmd, CmdRxEnb); 4932 rtl_pci_commit(tp); 4933 break; 4934 default: 4935 break; 4936 } 4937 } 4938 4939 static void rtl_shutdown(struct pci_dev *pdev) 4940 { 4941 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4942 4943 rtl8169_net_suspend(tp); 4944 4945 /* Restore original MAC address */ 4946 rtl_rar_set(tp, tp->dev->perm_addr); 4947 4948 if (system_state == SYSTEM_POWER_OFF) { 4949 if (tp->saved_wolopts) { 4950 rtl_wol_suspend_quirk(tp); 4951 rtl_wol_shutdown_quirk(tp); 4952 } 4953 4954 pci_wake_from_d3(pdev, true); 4955 pci_set_power_state(pdev, PCI_D3hot); 4956 } 4957 } 4958 4959 static void rtl_remove_one(struct pci_dev *pdev) 4960 { 4961 struct rtl8169_private *tp = pci_get_drvdata(pdev); 4962 4963 if (pci_dev_run_wake(pdev)) 4964 pm_runtime_get_noresume(&pdev->dev); 4965 4966 unregister_netdev(tp->dev); 4967 4968 if (r8168_check_dash(tp)) 4969 rtl8168_driver_stop(tp); 4970 4971 rtl_release_firmware(tp); 4972 4973 /* restore original MAC address */ 4974 rtl_rar_set(tp, tp->dev->perm_addr); 4975 } 4976 4977 static const struct net_device_ops rtl_netdev_ops = { 4978 .ndo_open = rtl_open, 4979 .ndo_stop = rtl8169_close, 4980 .ndo_get_stats64 = rtl8169_get_stats64, 4981 .ndo_start_xmit = rtl8169_start_xmit, 4982 .ndo_features_check = rtl8169_features_check, 4983 .ndo_tx_timeout = rtl8169_tx_timeout, 4984 .ndo_validate_addr = eth_validate_addr, 4985 .ndo_change_mtu = rtl8169_change_mtu, 4986 .ndo_fix_features = rtl8169_fix_features, 4987 .ndo_set_features = rtl8169_set_features, 4988 .ndo_set_mac_address = rtl_set_mac_address, 4989 .ndo_do_ioctl = phy_do_ioctl_running, 4990 .ndo_set_rx_mode = rtl_set_rx_mode, 4991 #ifdef CONFIG_NET_POLL_CONTROLLER 4992 .ndo_poll_controller = rtl8169_netpoll, 4993 #endif 4994 4995 }; 4996 4997 static void rtl_set_irq_mask(struct rtl8169_private *tp) 4998 { 4999 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg; 5000 5001 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) 5002 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver; 5003 else if (tp->mac_version == RTL_GIGA_MAC_VER_11) 5004 /* special workaround needed */ 5005 tp->irq_mask |= RxFIFOOver; 5006 else 5007 tp->irq_mask |= RxOverflow; 5008 } 5009 5010 static int rtl_alloc_irq(struct rtl8169_private *tp) 5011 { 5012 unsigned int flags; 5013 5014 switch (tp->mac_version) { 5015 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5016 rtl_unlock_config_regs(tp); 5017 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); 5018 rtl_lock_config_regs(tp); 5019 /* fall through */ 5020 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17: 5021 flags = PCI_IRQ_LEGACY; 5022 break; 5023 default: 5024 flags = PCI_IRQ_ALL_TYPES; 5025 break; 5026 } 5027 5028 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags); 5029 } 5030 5031 static void rtl_read_mac_address(struct rtl8169_private *tp, 5032 u8 mac_addr[ETH_ALEN]) 5033 { 5034 /* Get MAC address */ 5035 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) { 5036 u32 value = rtl_eri_read(tp, 0xe0); 5037 5038 mac_addr[0] = (value >> 0) & 0xff; 5039 mac_addr[1] = (value >> 8) & 0xff; 5040 mac_addr[2] = (value >> 16) & 0xff; 5041 mac_addr[3] = (value >> 24) & 0xff; 5042 5043 value = rtl_eri_read(tp, 0xe4); 5044 mac_addr[4] = (value >> 0) & 0xff; 5045 mac_addr[5] = (value >> 8) & 0xff; 5046 } else if (rtl_is_8125(tp)) { 5047 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP); 5048 } 5049 } 5050 5051 DECLARE_RTL_COND(rtl_link_list_ready_cond) 5052 { 5053 return RTL_R8(tp, MCU) & LINK_LIST_RDY; 5054 } 5055 5056 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp) 5057 { 5058 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42); 5059 } 5060 5061 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg) 5062 { 5063 struct rtl8169_private *tp = mii_bus->priv; 5064 5065 if (phyaddr > 0) 5066 return -ENODEV; 5067 5068 return rtl_readphy(tp, phyreg); 5069 } 5070 5071 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr, 5072 int phyreg, u16 val) 5073 { 5074 struct rtl8169_private *tp = mii_bus->priv; 5075 5076 if (phyaddr > 0) 5077 return -ENODEV; 5078 5079 rtl_writephy(tp, phyreg, val); 5080 5081 return 0; 5082 } 5083 5084 static int r8169_mdio_register(struct rtl8169_private *tp) 5085 { 5086 struct pci_dev *pdev = tp->pci_dev; 5087 struct mii_bus *new_bus; 5088 int ret; 5089 5090 new_bus = devm_mdiobus_alloc(&pdev->dev); 5091 if (!new_bus) 5092 return -ENOMEM; 5093 5094 new_bus->name = "r8169"; 5095 new_bus->priv = tp; 5096 new_bus->parent = &pdev->dev; 5097 new_bus->irq[0] = PHY_IGNORE_INTERRUPT; 5098 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev)); 5099 5100 new_bus->read = r8169_mdio_read_reg; 5101 new_bus->write = r8169_mdio_write_reg; 5102 5103 ret = devm_mdiobus_register(new_bus); 5104 if (ret) 5105 return ret; 5106 5107 tp->phydev = mdiobus_get_phy(new_bus, 0); 5108 if (!tp->phydev) { 5109 return -ENODEV; 5110 } else if (!tp->phydev->drv) { 5111 /* Most chip versions fail with the genphy driver. 5112 * Therefore ensure that the dedicated PHY driver is loaded. 5113 */ 5114 dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be added to initramfs?\n", 5115 tp->phydev->phy_id); 5116 return -EUNATCH; 5117 } 5118 5119 /* PHY will be woken up in rtl_open() */ 5120 phy_suspend(tp->phydev); 5121 5122 return 0; 5123 } 5124 5125 static void rtl_hw_init_8168g(struct rtl8169_private *tp) 5126 { 5127 rtl_enable_rxdvgate(tp); 5128 5129 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5130 msleep(1); 5131 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5132 5133 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5134 r8168g_wait_ll_share_fifo_ready(tp); 5135 5136 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); 5137 r8168g_wait_ll_share_fifo_ready(tp); 5138 } 5139 5140 static void rtl_hw_init_8125(struct rtl8169_private *tp) 5141 { 5142 rtl_enable_rxdvgate(tp); 5143 5144 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); 5145 msleep(1); 5146 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); 5147 5148 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); 5149 r8168g_wait_ll_share_fifo_ready(tp); 5150 5151 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); 5152 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); 5153 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); 5154 r8168g_wait_ll_share_fifo_ready(tp); 5155 } 5156 5157 static void rtl_hw_initialize(struct rtl8169_private *tp) 5158 { 5159 switch (tp->mac_version) { 5160 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52: 5161 rtl8168ep_stop_cmac(tp); 5162 /* fall through */ 5163 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48: 5164 rtl_hw_init_8168g(tp); 5165 break; 5166 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61: 5167 rtl_hw_init_8125(tp); 5168 break; 5169 default: 5170 break; 5171 } 5172 } 5173 5174 static int rtl_jumbo_max(struct rtl8169_private *tp) 5175 { 5176 /* Non-GBit versions don't support jumbo frames */ 5177 if (!tp->supports_gmii) 5178 return 0; 5179 5180 switch (tp->mac_version) { 5181 /* RTL8169 */ 5182 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06: 5183 return JUMBO_7K; 5184 /* RTL8168b */ 5185 case RTL_GIGA_MAC_VER_11: 5186 case RTL_GIGA_MAC_VER_12: 5187 case RTL_GIGA_MAC_VER_17: 5188 return JUMBO_4K; 5189 /* RTL8168c */ 5190 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24: 5191 return JUMBO_6K; 5192 default: 5193 return JUMBO_9K; 5194 } 5195 } 5196 5197 static void rtl_disable_clk(void *data) 5198 { 5199 clk_disable_unprepare(data); 5200 } 5201 5202 static int rtl_get_ether_clk(struct rtl8169_private *tp) 5203 { 5204 struct device *d = tp_to_dev(tp); 5205 struct clk *clk; 5206 int rc; 5207 5208 clk = devm_clk_get(d, "ether_clk"); 5209 if (IS_ERR(clk)) { 5210 rc = PTR_ERR(clk); 5211 if (rc == -ENOENT) 5212 /* clk-core allows NULL (for suspend / resume) */ 5213 rc = 0; 5214 else if (rc != -EPROBE_DEFER) 5215 dev_err(d, "failed to get clk: %d\n", rc); 5216 } else { 5217 tp->clk = clk; 5218 rc = clk_prepare_enable(clk); 5219 if (rc) 5220 dev_err(d, "failed to enable clk: %d\n", rc); 5221 else 5222 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk); 5223 } 5224 5225 return rc; 5226 } 5227 5228 static void rtl_init_mac_address(struct rtl8169_private *tp) 5229 { 5230 struct net_device *dev = tp->dev; 5231 u8 *mac_addr = dev->dev_addr; 5232 int rc; 5233 5234 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr); 5235 if (!rc) 5236 goto done; 5237 5238 rtl_read_mac_address(tp, mac_addr); 5239 if (is_valid_ether_addr(mac_addr)) 5240 goto done; 5241 5242 rtl_read_mac_from_reg(tp, mac_addr, MAC0); 5243 if (is_valid_ether_addr(mac_addr)) 5244 goto done; 5245 5246 eth_hw_addr_random(dev); 5247 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n"); 5248 done: 5249 rtl_rar_set(tp, mac_addr); 5250 } 5251 5252 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5253 { 5254 struct rtl8169_private *tp; 5255 int jumbo_max, region, rc; 5256 enum mac_version chipset; 5257 struct net_device *dev; 5258 u16 xid; 5259 5260 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp)); 5261 if (!dev) 5262 return -ENOMEM; 5263 5264 SET_NETDEV_DEV(dev, &pdev->dev); 5265 dev->netdev_ops = &rtl_netdev_ops; 5266 tp = netdev_priv(dev); 5267 tp->dev = dev; 5268 tp->pci_dev = pdev; 5269 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; 5270 tp->eee_adv = -1; 5271 tp->ocp_base = OCP_STD_PHY_BASE; 5272 5273 /* Get the *optional* external "ether_clk" used on some boards */ 5274 rc = rtl_get_ether_clk(tp); 5275 if (rc) 5276 return rc; 5277 5278 /* Disable ASPM completely as that cause random device stop working 5279 * problems as well as full system hangs for some PCIe devices users. 5280 */ 5281 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 5282 PCIE_LINK_STATE_L1); 5283 tp->aspm_manageable = !rc; 5284 5285 /* enable device (incl. PCI PM wakeup and hotplug setup) */ 5286 rc = pcim_enable_device(pdev); 5287 if (rc < 0) { 5288 dev_err(&pdev->dev, "enable failure\n"); 5289 return rc; 5290 } 5291 5292 if (pcim_set_mwi(pdev) < 0) 5293 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n"); 5294 5295 /* use first MMIO region */ 5296 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1; 5297 if (region < 0) { 5298 dev_err(&pdev->dev, "no MMIO resource found\n"); 5299 return -ENODEV; 5300 } 5301 5302 /* check for weird/broken PCI region reporting */ 5303 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { 5304 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n"); 5305 return -ENODEV; 5306 } 5307 5308 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME); 5309 if (rc < 0) { 5310 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); 5311 return rc; 5312 } 5313 5314 tp->mmio_addr = pcim_iomap_table(pdev)[region]; 5315 5316 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf; 5317 5318 /* Identify chip attached to board */ 5319 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii); 5320 if (chipset == RTL_GIGA_MAC_NONE) { 5321 dev_err(&pdev->dev, "unknown chip XID %03x\n", xid); 5322 return -ENODEV; 5323 } 5324 5325 tp->mac_version = chipset; 5326 5327 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK; 5328 5329 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 && 5330 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) 5331 dev->features |= NETIF_F_HIGHDMA; 5332 5333 rtl_init_rxcfg(tp); 5334 5335 rtl8169_irq_mask_and_ack(tp); 5336 5337 rtl_hw_initialize(tp); 5338 5339 rtl_hw_reset(tp); 5340 5341 pci_set_master(pdev); 5342 5343 rc = rtl_alloc_irq(tp); 5344 if (rc < 0) { 5345 dev_err(&pdev->dev, "Can't allocate interrupt\n"); 5346 return rc; 5347 } 5348 5349 mutex_init(&tp->wk.mutex); 5350 INIT_WORK(&tp->wk.work, rtl_task); 5351 u64_stats_init(&tp->rx_stats.syncp); 5352 u64_stats_init(&tp->tx_stats.syncp); 5353 5354 rtl_init_mac_address(tp); 5355 5356 dev->ethtool_ops = &rtl8169_ethtool_ops; 5357 5358 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT); 5359 5360 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM | 5361 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 5362 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; 5363 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 5364 5365 /* 5366 * Pretend we are using VLANs; This bypasses a nasty bug where 5367 * Interrupts stop flowing on high load on 8110SCd controllers. 5368 */ 5369 if (tp->mac_version == RTL_GIGA_MAC_VER_05) 5370 /* Disallow toggling */ 5371 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX; 5372 5373 if (rtl_chip_supports_csum_v2(tp)) 5374 dev->hw_features |= NETIF_F_IPV6_CSUM; 5375 5376 dev->features |= dev->hw_features; 5377 5378 /* There has been a number of reports that using SG/TSO results in 5379 * tx timeouts. However for a lot of people SG/TSO works fine. 5380 * Therefore disable both features by default, but allow users to 5381 * enable them. Use at own risk! 5382 */ 5383 if (rtl_chip_supports_csum_v2(tp)) { 5384 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6; 5385 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2; 5386 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2; 5387 } else { 5388 dev->hw_features |= NETIF_F_SG | NETIF_F_TSO; 5389 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1; 5390 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1; 5391 } 5392 5393 dev->hw_features |= NETIF_F_RXALL; 5394 dev->hw_features |= NETIF_F_RXFCS; 5395 5396 /* configure chip for default features */ 5397 rtl8169_set_features(dev, dev->features); 5398 5399 jumbo_max = rtl_jumbo_max(tp); 5400 if (jumbo_max) 5401 dev->max_mtu = jumbo_max; 5402 5403 rtl_set_irq_mask(tp); 5404 5405 tp->fw_name = rtl_chip_infos[chipset].fw_name; 5406 5407 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters), 5408 &tp->counters_phys_addr, 5409 GFP_KERNEL); 5410 if (!tp->counters) 5411 return -ENOMEM; 5412 5413 pci_set_drvdata(pdev, tp); 5414 5415 rc = r8169_mdio_register(tp); 5416 if (rc) 5417 return rc; 5418 5419 /* chip gets powered up in rtl_open() */ 5420 rtl_pll_power_down(tp); 5421 5422 rc = register_netdev(dev); 5423 if (rc) 5424 return rc; 5425 5426 netdev_info(dev, "%s, %pM, XID %03x, IRQ %d\n", 5427 rtl_chip_infos[chipset].name, dev->dev_addr, xid, 5428 pci_irq_vector(pdev, 0)); 5429 5430 if (jumbo_max) 5431 netdev_info(dev, "jumbo features [frames: %d bytes, tx checksumming: %s]\n", 5432 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ? 5433 "ok" : "ko"); 5434 5435 if (r8168_check_dash(tp)) 5436 rtl8168_driver_start(tp); 5437 5438 if (pci_dev_run_wake(pdev)) 5439 pm_runtime_put_sync(&pdev->dev); 5440 5441 return 0; 5442 } 5443 5444 static struct pci_driver rtl8169_pci_driver = { 5445 .name = MODULENAME, 5446 .id_table = rtl8169_pci_tbl, 5447 .probe = rtl_init_one, 5448 .remove = rtl_remove_one, 5449 .shutdown = rtl_shutdown, 5450 #ifdef CONFIG_PM 5451 .driver.pm = &rtl8169_pm_ops, 5452 #endif 5453 }; 5454 5455 module_pci_driver(rtl8169_pci_driver); 5456