1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/coproc.c: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Authors: Rusty Russell <rusty@rustcorp.com.au> 9 * Christoffer Dall <c.dall@virtualopensystems.com> 10 */ 11 12 #include <linux/bsearch.h> 13 #include <linux/kvm_host.h> 14 #include <linux/mm.h> 15 #include <linux/printk.h> 16 #include <linux/uaccess.h> 17 18 #include <asm/cacheflush.h> 19 #include <asm/cputype.h> 20 #include <asm/debug-monitors.h> 21 #include <asm/esr.h> 22 #include <asm/kvm_arm.h> 23 #include <asm/kvm_coproc.h> 24 #include <asm/kvm_emulate.h> 25 #include <asm/kvm_hyp.h> 26 #include <asm/kvm_mmu.h> 27 #include <asm/perf_event.h> 28 #include <asm/sysreg.h> 29 30 #include <trace/events/kvm.h> 31 32 #include "sys_regs.h" 33 34 #include "trace.h" 35 36 /* 37 * All of this file is extremely similar to the ARM coproc.c, but the 38 * types are different. My gut feeling is that it should be pretty 39 * easy to merge, but that would be an ABI breakage -- again. VFP 40 * would also need to be abstracted. 41 * 42 * For AArch32, we only take care of what is being trapped. Anything 43 * that has to do with init and userspace access has to go via the 44 * 64bit interface. 45 */ 46 47 static bool read_from_write_only(struct kvm_vcpu *vcpu, 48 struct sys_reg_params *params, 49 const struct sys_reg_desc *r) 50 { 51 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n"); 52 print_sys_reg_instr(params); 53 kvm_inject_undefined(vcpu); 54 return false; 55 } 56 57 static bool write_to_read_only(struct kvm_vcpu *vcpu, 58 struct sys_reg_params *params, 59 const struct sys_reg_desc *r) 60 { 61 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n"); 62 print_sys_reg_instr(params); 63 kvm_inject_undefined(vcpu); 64 return false; 65 } 66 67 static bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 68 { 69 /* 70 * System registers listed in the switch are not saved on every 71 * exit from the guest but are only saved on vcpu_put. 72 * 73 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 74 * should never be listed below, because the guest cannot modify its 75 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's 76 * thread when emulating cross-VCPU communication. 77 */ 78 switch (reg) { 79 case CSSELR_EL1: *val = read_sysreg_s(SYS_CSSELR_EL1); break; 80 case SCTLR_EL1: *val = read_sysreg_s(SYS_SCTLR_EL12); break; 81 case CPACR_EL1: *val = read_sysreg_s(SYS_CPACR_EL12); break; 82 case TTBR0_EL1: *val = read_sysreg_s(SYS_TTBR0_EL12); break; 83 case TTBR1_EL1: *val = read_sysreg_s(SYS_TTBR1_EL12); break; 84 case TCR_EL1: *val = read_sysreg_s(SYS_TCR_EL12); break; 85 case ESR_EL1: *val = read_sysreg_s(SYS_ESR_EL12); break; 86 case AFSR0_EL1: *val = read_sysreg_s(SYS_AFSR0_EL12); break; 87 case AFSR1_EL1: *val = read_sysreg_s(SYS_AFSR1_EL12); break; 88 case FAR_EL1: *val = read_sysreg_s(SYS_FAR_EL12); break; 89 case MAIR_EL1: *val = read_sysreg_s(SYS_MAIR_EL12); break; 90 case VBAR_EL1: *val = read_sysreg_s(SYS_VBAR_EL12); break; 91 case CONTEXTIDR_EL1: *val = read_sysreg_s(SYS_CONTEXTIDR_EL12);break; 92 case TPIDR_EL0: *val = read_sysreg_s(SYS_TPIDR_EL0); break; 93 case TPIDRRO_EL0: *val = read_sysreg_s(SYS_TPIDRRO_EL0); break; 94 case TPIDR_EL1: *val = read_sysreg_s(SYS_TPIDR_EL1); break; 95 case AMAIR_EL1: *val = read_sysreg_s(SYS_AMAIR_EL12); break; 96 case CNTKCTL_EL1: *val = read_sysreg_s(SYS_CNTKCTL_EL12); break; 97 case ELR_EL1: *val = read_sysreg_s(SYS_ELR_EL12); break; 98 case PAR_EL1: *val = read_sysreg_s(SYS_PAR_EL1); break; 99 case DACR32_EL2: *val = read_sysreg_s(SYS_DACR32_EL2); break; 100 case IFSR32_EL2: *val = read_sysreg_s(SYS_IFSR32_EL2); break; 101 case DBGVCR32_EL2: *val = read_sysreg_s(SYS_DBGVCR32_EL2); break; 102 default: return false; 103 } 104 105 return true; 106 } 107 108 static bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 109 { 110 /* 111 * System registers listed in the switch are not restored on every 112 * entry to the guest but are only restored on vcpu_load. 113 * 114 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but 115 * should never be listed below, because the MPIDR should only be set 116 * once, before running the VCPU, and never changed later. 117 */ 118 switch (reg) { 119 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); break; 120 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); break; 121 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); break; 122 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); break; 123 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); break; 124 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); break; 125 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); break; 126 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); break; 127 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); break; 128 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); break; 129 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); break; 130 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); break; 131 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12);break; 132 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); break; 133 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); break; 134 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); break; 135 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); break; 136 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); break; 137 case ELR_EL1: write_sysreg_s(val, SYS_ELR_EL12); break; 138 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); break; 139 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); break; 140 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); break; 141 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); break; 142 default: return false; 143 } 144 145 return true; 146 } 147 148 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg) 149 { 150 u64 val = 0x8badf00d8badf00d; 151 152 if (vcpu->arch.sysregs_loaded_on_cpu && 153 __vcpu_read_sys_reg_from_cpu(reg, &val)) 154 return val; 155 156 return __vcpu_sys_reg(vcpu, reg); 157 } 158 159 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg) 160 { 161 if (vcpu->arch.sysregs_loaded_on_cpu && 162 __vcpu_write_sys_reg_to_cpu(val, reg)) 163 return; 164 165 __vcpu_sys_reg(vcpu, reg) = val; 166 } 167 168 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */ 169 static u32 cache_levels; 170 171 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ 172 #define CSSELR_MAX 12 173 174 /* Which cache CCSIDR represents depends on CSSELR value. */ 175 static u32 get_ccsidr(u32 csselr) 176 { 177 u32 ccsidr; 178 179 /* Make sure noone else changes CSSELR during this! */ 180 local_irq_disable(); 181 write_sysreg(csselr, csselr_el1); 182 isb(); 183 ccsidr = read_sysreg(ccsidr_el1); 184 local_irq_enable(); 185 186 return ccsidr; 187 } 188 189 /* 190 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized). 191 */ 192 static bool access_dcsw(struct kvm_vcpu *vcpu, 193 struct sys_reg_params *p, 194 const struct sys_reg_desc *r) 195 { 196 if (!p->is_write) 197 return read_from_write_only(vcpu, p, r); 198 199 /* 200 * Only track S/W ops if we don't have FWB. It still indicates 201 * that the guest is a bit broken (S/W operations should only 202 * be done by firmware, knowing that there is only a single 203 * CPU left in the system, and certainly not from non-secure 204 * software). 205 */ 206 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) 207 kvm_set_way_flush(vcpu); 208 209 return true; 210 } 211 212 /* 213 * Generic accessor for VM registers. Only called as long as HCR_TVM 214 * is set. If the guest enables the MMU, we stop trapping the VM 215 * sys_regs and leave it in complete control of the caches. 216 */ 217 static bool access_vm_reg(struct kvm_vcpu *vcpu, 218 struct sys_reg_params *p, 219 const struct sys_reg_desc *r) 220 { 221 bool was_enabled = vcpu_has_cache_enabled(vcpu); 222 u64 val; 223 int reg = r->reg; 224 225 BUG_ON(!p->is_write); 226 227 /* See the 32bit mapping in kvm_host.h */ 228 if (p->is_aarch32) 229 reg = r->reg / 2; 230 231 if (!p->is_aarch32 || !p->is_32bit) { 232 val = p->regval; 233 } else { 234 val = vcpu_read_sys_reg(vcpu, reg); 235 if (r->reg % 2) 236 val = (p->regval << 32) | (u64)lower_32_bits(val); 237 else 238 val = ((u64)upper_32_bits(val) << 32) | 239 lower_32_bits(p->regval); 240 } 241 vcpu_write_sys_reg(vcpu, val, reg); 242 243 kvm_toggle_cache(vcpu, was_enabled); 244 return true; 245 } 246 247 static bool access_actlr(struct kvm_vcpu *vcpu, 248 struct sys_reg_params *p, 249 const struct sys_reg_desc *r) 250 { 251 if (p->is_write) 252 return ignore_write(vcpu, p); 253 254 p->regval = vcpu_read_sys_reg(vcpu, ACTLR_EL1); 255 256 if (p->is_aarch32) { 257 if (r->Op2 & 2) 258 p->regval = upper_32_bits(p->regval); 259 else 260 p->regval = lower_32_bits(p->regval); 261 } 262 263 return true; 264 } 265 266 /* 267 * Trap handler for the GICv3 SGI generation system register. 268 * Forward the request to the VGIC emulation. 269 * The cp15_64 code makes sure this automatically works 270 * for both AArch64 and AArch32 accesses. 271 */ 272 static bool access_gic_sgi(struct kvm_vcpu *vcpu, 273 struct sys_reg_params *p, 274 const struct sys_reg_desc *r) 275 { 276 bool g1; 277 278 if (!p->is_write) 279 return read_from_write_only(vcpu, p, r); 280 281 /* 282 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates 283 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group, 284 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively 285 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure 286 * group. 287 */ 288 if (p->is_aarch32) { 289 switch (p->Op1) { 290 default: /* Keep GCC quiet */ 291 case 0: /* ICC_SGI1R */ 292 g1 = true; 293 break; 294 case 1: /* ICC_ASGI1R */ 295 case 2: /* ICC_SGI0R */ 296 g1 = false; 297 break; 298 } 299 } else { 300 switch (p->Op2) { 301 default: /* Keep GCC quiet */ 302 case 5: /* ICC_SGI1R_EL1 */ 303 g1 = true; 304 break; 305 case 6: /* ICC_ASGI1R_EL1 */ 306 case 7: /* ICC_SGI0R_EL1 */ 307 g1 = false; 308 break; 309 } 310 } 311 312 vgic_v3_dispatch_sgi(vcpu, p->regval, g1); 313 314 return true; 315 } 316 317 static bool access_gic_sre(struct kvm_vcpu *vcpu, 318 struct sys_reg_params *p, 319 const struct sys_reg_desc *r) 320 { 321 if (p->is_write) 322 return ignore_write(vcpu, p); 323 324 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre; 325 return true; 326 } 327 328 static bool trap_raz_wi(struct kvm_vcpu *vcpu, 329 struct sys_reg_params *p, 330 const struct sys_reg_desc *r) 331 { 332 if (p->is_write) 333 return ignore_write(vcpu, p); 334 else 335 return read_zero(vcpu, p); 336 } 337 338 /* 339 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the 340 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0 341 * system, these registers should UNDEF. LORID_EL1 being a RO register, we 342 * treat it separately. 343 */ 344 static bool trap_loregion(struct kvm_vcpu *vcpu, 345 struct sys_reg_params *p, 346 const struct sys_reg_desc *r) 347 { 348 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 349 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1, 350 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 351 352 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) { 353 kvm_inject_undefined(vcpu); 354 return false; 355 } 356 357 if (p->is_write && sr == SYS_LORID_EL1) 358 return write_to_read_only(vcpu, p, r); 359 360 return trap_raz_wi(vcpu, p, r); 361 } 362 363 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu, 364 struct sys_reg_params *p, 365 const struct sys_reg_desc *r) 366 { 367 if (p->is_write) { 368 return ignore_write(vcpu, p); 369 } else { 370 p->regval = (1 << 3); 371 return true; 372 } 373 } 374 375 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu, 376 struct sys_reg_params *p, 377 const struct sys_reg_desc *r) 378 { 379 if (p->is_write) { 380 return ignore_write(vcpu, p); 381 } else { 382 p->regval = read_sysreg(dbgauthstatus_el1); 383 return true; 384 } 385 } 386 387 /* 388 * We want to avoid world-switching all the DBG registers all the 389 * time: 390 * 391 * - If we've touched any debug register, it is likely that we're 392 * going to touch more of them. It then makes sense to disable the 393 * traps and start doing the save/restore dance 394 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is 395 * then mandatory to save/restore the registers, as the guest 396 * depends on them. 397 * 398 * For this, we use a DIRTY bit, indicating the guest has modified the 399 * debug registers, used as follow: 400 * 401 * On guest entry: 402 * - If the dirty bit is set (because we're coming back from trapping), 403 * disable the traps, save host registers, restore guest registers. 404 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), 405 * set the dirty bit, disable the traps, save host registers, 406 * restore guest registers. 407 * - Otherwise, enable the traps 408 * 409 * On guest exit: 410 * - If the dirty bit is set, save guest registers, restore host 411 * registers and clear the dirty bit. This ensure that the host can 412 * now use the debug registers. 413 */ 414 static bool trap_debug_regs(struct kvm_vcpu *vcpu, 415 struct sys_reg_params *p, 416 const struct sys_reg_desc *r) 417 { 418 if (p->is_write) { 419 vcpu_write_sys_reg(vcpu, p->regval, r->reg); 420 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 421 } else { 422 p->regval = vcpu_read_sys_reg(vcpu, r->reg); 423 } 424 425 trace_trap_reg(__func__, r->reg, p->is_write, p->regval); 426 427 return true; 428 } 429 430 /* 431 * reg_to_dbg/dbg_to_reg 432 * 433 * A 32 bit write to a debug register leave top bits alone 434 * A 32 bit read from a debug register only returns the bottom bits 435 * 436 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the 437 * hyp.S code switches between host and guest values in future. 438 */ 439 static void reg_to_dbg(struct kvm_vcpu *vcpu, 440 struct sys_reg_params *p, 441 u64 *dbg_reg) 442 { 443 u64 val = p->regval; 444 445 if (p->is_32bit) { 446 val &= 0xffffffffUL; 447 val |= ((*dbg_reg >> 32) << 32); 448 } 449 450 *dbg_reg = val; 451 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 452 } 453 454 static void dbg_to_reg(struct kvm_vcpu *vcpu, 455 struct sys_reg_params *p, 456 u64 *dbg_reg) 457 { 458 p->regval = *dbg_reg; 459 if (p->is_32bit) 460 p->regval &= 0xffffffffUL; 461 } 462 463 static bool trap_bvr(struct kvm_vcpu *vcpu, 464 struct sys_reg_params *p, 465 const struct sys_reg_desc *rd) 466 { 467 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 468 469 if (p->is_write) 470 reg_to_dbg(vcpu, p, dbg_reg); 471 else 472 dbg_to_reg(vcpu, p, dbg_reg); 473 474 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 475 476 return true; 477 } 478 479 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 480 const struct kvm_one_reg *reg, void __user *uaddr) 481 { 482 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 483 484 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 485 return -EFAULT; 486 return 0; 487 } 488 489 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 490 const struct kvm_one_reg *reg, void __user *uaddr) 491 { 492 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 493 494 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 495 return -EFAULT; 496 return 0; 497 } 498 499 static void reset_bvr(struct kvm_vcpu *vcpu, 500 const struct sys_reg_desc *rd) 501 { 502 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val; 503 } 504 505 static bool trap_bcr(struct kvm_vcpu *vcpu, 506 struct sys_reg_params *p, 507 const struct sys_reg_desc *rd) 508 { 509 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 510 511 if (p->is_write) 512 reg_to_dbg(vcpu, p, dbg_reg); 513 else 514 dbg_to_reg(vcpu, p, dbg_reg); 515 516 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 517 518 return true; 519 } 520 521 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 522 const struct kvm_one_reg *reg, void __user *uaddr) 523 { 524 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 525 526 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 527 return -EFAULT; 528 529 return 0; 530 } 531 532 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 533 const struct kvm_one_reg *reg, void __user *uaddr) 534 { 535 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg]; 536 537 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 538 return -EFAULT; 539 return 0; 540 } 541 542 static void reset_bcr(struct kvm_vcpu *vcpu, 543 const struct sys_reg_desc *rd) 544 { 545 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val; 546 } 547 548 static bool trap_wvr(struct kvm_vcpu *vcpu, 549 struct sys_reg_params *p, 550 const struct sys_reg_desc *rd) 551 { 552 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 553 554 if (p->is_write) 555 reg_to_dbg(vcpu, p, dbg_reg); 556 else 557 dbg_to_reg(vcpu, p, dbg_reg); 558 559 trace_trap_reg(__func__, rd->reg, p->is_write, 560 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]); 561 562 return true; 563 } 564 565 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 566 const struct kvm_one_reg *reg, void __user *uaddr) 567 { 568 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 569 570 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 571 return -EFAULT; 572 return 0; 573 } 574 575 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 576 const struct kvm_one_reg *reg, void __user *uaddr) 577 { 578 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]; 579 580 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 581 return -EFAULT; 582 return 0; 583 } 584 585 static void reset_wvr(struct kvm_vcpu *vcpu, 586 const struct sys_reg_desc *rd) 587 { 588 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val; 589 } 590 591 static bool trap_wcr(struct kvm_vcpu *vcpu, 592 struct sys_reg_params *p, 593 const struct sys_reg_desc *rd) 594 { 595 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 596 597 if (p->is_write) 598 reg_to_dbg(vcpu, p, dbg_reg); 599 else 600 dbg_to_reg(vcpu, p, dbg_reg); 601 602 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 603 604 return true; 605 } 606 607 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 608 const struct kvm_one_reg *reg, void __user *uaddr) 609 { 610 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 611 612 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0) 613 return -EFAULT; 614 return 0; 615 } 616 617 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 618 const struct kvm_one_reg *reg, void __user *uaddr) 619 { 620 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg]; 621 622 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0) 623 return -EFAULT; 624 return 0; 625 } 626 627 static void reset_wcr(struct kvm_vcpu *vcpu, 628 const struct sys_reg_desc *rd) 629 { 630 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val; 631 } 632 633 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 634 { 635 u64 amair = read_sysreg(amair_el1); 636 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1); 637 } 638 639 static void reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 640 { 641 u64 actlr = read_sysreg(actlr_el1); 642 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1); 643 } 644 645 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 646 { 647 u64 mpidr; 648 649 /* 650 * Map the vcpu_id into the first three affinity level fields of 651 * the MPIDR. We limit the number of VCPUs in level 0 due to a 652 * limitation to 16 CPUs in that level in the ICC_SGIxR registers 653 * of the GICv3 to be able to address each CPU directly when 654 * sending IPIs. 655 */ 656 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0); 657 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1); 658 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2); 659 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1); 660 } 661 662 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) 663 { 664 u64 pmcr, val; 665 666 pmcr = read_sysreg(pmcr_el0); 667 /* 668 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN 669 * except PMCR.E resetting to zero. 670 */ 671 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK) 672 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); 673 if (!system_supports_32bit_el0()) 674 val |= ARMV8_PMU_PMCR_LC; 675 __vcpu_sys_reg(vcpu, r->reg) = val; 676 } 677 678 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags) 679 { 680 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0); 681 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu); 682 683 if (!enabled) 684 kvm_inject_undefined(vcpu); 685 686 return !enabled; 687 } 688 689 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu) 690 { 691 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN); 692 } 693 694 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu) 695 { 696 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN); 697 } 698 699 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu) 700 { 701 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN); 702 } 703 704 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu) 705 { 706 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN); 707 } 708 709 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 710 const struct sys_reg_desc *r) 711 { 712 u64 val; 713 714 if (!kvm_arm_pmu_v3_ready(vcpu)) 715 return trap_raz_wi(vcpu, p, r); 716 717 if (pmu_access_el0_disabled(vcpu)) 718 return false; 719 720 if (p->is_write) { 721 /* Only update writeable bits of PMCR */ 722 val = __vcpu_sys_reg(vcpu, PMCR_EL0); 723 val &= ~ARMV8_PMU_PMCR_MASK; 724 val |= p->regval & ARMV8_PMU_PMCR_MASK; 725 if (!system_supports_32bit_el0()) 726 val |= ARMV8_PMU_PMCR_LC; 727 __vcpu_sys_reg(vcpu, PMCR_EL0) = val; 728 kvm_pmu_handle_pmcr(vcpu, val); 729 kvm_vcpu_pmu_restore_guest(vcpu); 730 } else { 731 /* PMCR.P & PMCR.C are RAZ */ 732 val = __vcpu_sys_reg(vcpu, PMCR_EL0) 733 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); 734 p->regval = val; 735 } 736 737 return true; 738 } 739 740 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 741 const struct sys_reg_desc *r) 742 { 743 if (!kvm_arm_pmu_v3_ready(vcpu)) 744 return trap_raz_wi(vcpu, p, r); 745 746 if (pmu_access_event_counter_el0_disabled(vcpu)) 747 return false; 748 749 if (p->is_write) 750 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval; 751 else 752 /* return PMSELR.SEL field */ 753 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0) 754 & ARMV8_PMU_COUNTER_MASK; 755 756 return true; 757 } 758 759 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 760 const struct sys_reg_desc *r) 761 { 762 u64 pmceid; 763 764 if (!kvm_arm_pmu_v3_ready(vcpu)) 765 return trap_raz_wi(vcpu, p, r); 766 767 BUG_ON(p->is_write); 768 769 if (pmu_access_el0_disabled(vcpu)) 770 return false; 771 772 if (!(p->Op2 & 1)) 773 pmceid = read_sysreg(pmceid0_el0); 774 else 775 pmceid = read_sysreg(pmceid1_el0); 776 777 p->regval = pmceid; 778 779 return true; 780 } 781 782 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx) 783 { 784 u64 pmcr, val; 785 786 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0); 787 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK; 788 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) { 789 kvm_inject_undefined(vcpu); 790 return false; 791 } 792 793 return true; 794 } 795 796 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, 797 struct sys_reg_params *p, 798 const struct sys_reg_desc *r) 799 { 800 u64 idx; 801 802 if (!kvm_arm_pmu_v3_ready(vcpu)) 803 return trap_raz_wi(vcpu, p, r); 804 805 if (r->CRn == 9 && r->CRm == 13) { 806 if (r->Op2 == 2) { 807 /* PMXEVCNTR_EL0 */ 808 if (pmu_access_event_counter_el0_disabled(vcpu)) 809 return false; 810 811 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) 812 & ARMV8_PMU_COUNTER_MASK; 813 } else if (r->Op2 == 0) { 814 /* PMCCNTR_EL0 */ 815 if (pmu_access_cycle_counter_el0_disabled(vcpu)) 816 return false; 817 818 idx = ARMV8_PMU_CYCLE_IDX; 819 } else { 820 return false; 821 } 822 } else if (r->CRn == 0 && r->CRm == 9) { 823 /* PMCCNTR */ 824 if (pmu_access_event_counter_el0_disabled(vcpu)) 825 return false; 826 827 idx = ARMV8_PMU_CYCLE_IDX; 828 } else if (r->CRn == 14 && (r->CRm & 12) == 8) { 829 /* PMEVCNTRn_EL0 */ 830 if (pmu_access_event_counter_el0_disabled(vcpu)) 831 return false; 832 833 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 834 } else { 835 return false; 836 } 837 838 if (!pmu_counter_idx_valid(vcpu, idx)) 839 return false; 840 841 if (p->is_write) { 842 if (pmu_access_el0_disabled(vcpu)) 843 return false; 844 845 kvm_pmu_set_counter_value(vcpu, idx, p->regval); 846 } else { 847 p->regval = kvm_pmu_get_counter_value(vcpu, idx); 848 } 849 850 return true; 851 } 852 853 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 854 const struct sys_reg_desc *r) 855 { 856 u64 idx, reg; 857 858 if (!kvm_arm_pmu_v3_ready(vcpu)) 859 return trap_raz_wi(vcpu, p, r); 860 861 if (pmu_access_el0_disabled(vcpu)) 862 return false; 863 864 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) { 865 /* PMXEVTYPER_EL0 */ 866 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK; 867 reg = PMEVTYPER0_EL0 + idx; 868 } else if (r->CRn == 14 && (r->CRm & 12) == 12) { 869 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7); 870 if (idx == ARMV8_PMU_CYCLE_IDX) 871 reg = PMCCFILTR_EL0; 872 else 873 /* PMEVTYPERn_EL0 */ 874 reg = PMEVTYPER0_EL0 + idx; 875 } else { 876 BUG(); 877 } 878 879 if (!pmu_counter_idx_valid(vcpu, idx)) 880 return false; 881 882 if (p->is_write) { 883 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); 884 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK; 885 kvm_vcpu_pmu_restore_guest(vcpu); 886 } else { 887 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK; 888 } 889 890 return true; 891 } 892 893 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 894 const struct sys_reg_desc *r) 895 { 896 u64 val, mask; 897 898 if (!kvm_arm_pmu_v3_ready(vcpu)) 899 return trap_raz_wi(vcpu, p, r); 900 901 if (pmu_access_el0_disabled(vcpu)) 902 return false; 903 904 mask = kvm_pmu_valid_counter_mask(vcpu); 905 if (p->is_write) { 906 val = p->regval & mask; 907 if (r->Op2 & 0x1) { 908 /* accessing PMCNTENSET_EL0 */ 909 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val; 910 kvm_pmu_enable_counter_mask(vcpu, val); 911 kvm_vcpu_pmu_restore_guest(vcpu); 912 } else { 913 /* accessing PMCNTENCLR_EL0 */ 914 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val; 915 kvm_pmu_disable_counter_mask(vcpu, val); 916 } 917 } else { 918 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask; 919 } 920 921 return true; 922 } 923 924 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 925 const struct sys_reg_desc *r) 926 { 927 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 928 929 if (!kvm_arm_pmu_v3_ready(vcpu)) 930 return trap_raz_wi(vcpu, p, r); 931 932 if (!vcpu_mode_priv(vcpu)) { 933 kvm_inject_undefined(vcpu); 934 return false; 935 } 936 937 if (p->is_write) { 938 u64 val = p->regval & mask; 939 940 if (r->Op2 & 0x1) 941 /* accessing PMINTENSET_EL1 */ 942 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val; 943 else 944 /* accessing PMINTENCLR_EL1 */ 945 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val; 946 } else { 947 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask; 948 } 949 950 return true; 951 } 952 953 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 954 const struct sys_reg_desc *r) 955 { 956 u64 mask = kvm_pmu_valid_counter_mask(vcpu); 957 958 if (!kvm_arm_pmu_v3_ready(vcpu)) 959 return trap_raz_wi(vcpu, p, r); 960 961 if (pmu_access_el0_disabled(vcpu)) 962 return false; 963 964 if (p->is_write) { 965 if (r->CRm & 0x2) 966 /* accessing PMOVSSET_EL0 */ 967 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask); 968 else 969 /* accessing PMOVSCLR_EL0 */ 970 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask); 971 } else { 972 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask; 973 } 974 975 return true; 976 } 977 978 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 979 const struct sys_reg_desc *r) 980 { 981 u64 mask; 982 983 if (!kvm_arm_pmu_v3_ready(vcpu)) 984 return trap_raz_wi(vcpu, p, r); 985 986 if (!p->is_write) 987 return read_from_write_only(vcpu, p, r); 988 989 if (pmu_write_swinc_el0_disabled(vcpu)) 990 return false; 991 992 mask = kvm_pmu_valid_counter_mask(vcpu); 993 kvm_pmu_software_increment(vcpu, p->regval & mask); 994 return true; 995 } 996 997 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 998 const struct sys_reg_desc *r) 999 { 1000 if (!kvm_arm_pmu_v3_ready(vcpu)) 1001 return trap_raz_wi(vcpu, p, r); 1002 1003 if (p->is_write) { 1004 if (!vcpu_mode_priv(vcpu)) { 1005 kvm_inject_undefined(vcpu); 1006 return false; 1007 } 1008 1009 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) = 1010 p->regval & ARMV8_PMU_USERENR_MASK; 1011 } else { 1012 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0) 1013 & ARMV8_PMU_USERENR_MASK; 1014 } 1015 1016 return true; 1017 } 1018 1019 #define reg_to_encoding(x) \ 1020 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \ 1021 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2); 1022 1023 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ 1024 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ 1025 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \ 1026 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \ 1027 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \ 1028 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \ 1029 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \ 1030 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \ 1031 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \ 1032 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr } 1033 1034 /* Macro to expand the PMEVCNTRn_EL0 register */ 1035 #define PMU_PMEVCNTR_EL0(n) \ 1036 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \ 1037 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), } 1038 1039 /* Macro to expand the PMEVTYPERn_EL0 register */ 1040 #define PMU_PMEVTYPER_EL0(n) \ 1041 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \ 1042 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), } 1043 1044 static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1045 const struct sys_reg_desc *r) 1046 { 1047 kvm_inject_undefined(vcpu); 1048 1049 return false; 1050 } 1051 1052 /* Macro to expand the AMU counter and type registers*/ 1053 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), access_amu } 1054 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), access_amu } 1055 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), access_amu } 1056 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), access_amu } 1057 1058 static bool trap_ptrauth(struct kvm_vcpu *vcpu, 1059 struct sys_reg_params *p, 1060 const struct sys_reg_desc *rd) 1061 { 1062 /* 1063 * If we land here, that is because we didn't fixup the access on exit 1064 * by allowing the PtrAuth sysregs. The only way this happens is when 1065 * the guest does not have PtrAuth support enabled. 1066 */ 1067 kvm_inject_undefined(vcpu); 1068 1069 return false; 1070 } 1071 1072 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu, 1073 const struct sys_reg_desc *rd) 1074 { 1075 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN_USER | REG_HIDDEN_GUEST; 1076 } 1077 1078 #define __PTRAUTH_KEY(k) \ 1079 { SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \ 1080 .visibility = ptrauth_visibility} 1081 1082 #define PTRAUTH_KEY(k) \ 1083 __PTRAUTH_KEY(k ## KEYLO_EL1), \ 1084 __PTRAUTH_KEY(k ## KEYHI_EL1) 1085 1086 static bool access_arch_timer(struct kvm_vcpu *vcpu, 1087 struct sys_reg_params *p, 1088 const struct sys_reg_desc *r) 1089 { 1090 enum kvm_arch_timers tmr; 1091 enum kvm_arch_timer_regs treg; 1092 u64 reg = reg_to_encoding(r); 1093 1094 switch (reg) { 1095 case SYS_CNTP_TVAL_EL0: 1096 case SYS_AARCH32_CNTP_TVAL: 1097 tmr = TIMER_PTIMER; 1098 treg = TIMER_REG_TVAL; 1099 break; 1100 case SYS_CNTP_CTL_EL0: 1101 case SYS_AARCH32_CNTP_CTL: 1102 tmr = TIMER_PTIMER; 1103 treg = TIMER_REG_CTL; 1104 break; 1105 case SYS_CNTP_CVAL_EL0: 1106 case SYS_AARCH32_CNTP_CVAL: 1107 tmr = TIMER_PTIMER; 1108 treg = TIMER_REG_CVAL; 1109 break; 1110 default: 1111 BUG(); 1112 } 1113 1114 if (p->is_write) 1115 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval); 1116 else 1117 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg); 1118 1119 return true; 1120 } 1121 1122 /* Read a sanitised cpufeature ID register by sys_reg_desc */ 1123 static u64 read_id_reg(const struct kvm_vcpu *vcpu, 1124 struct sys_reg_desc const *r, bool raz) 1125 { 1126 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, 1127 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); 1128 u64 val = raz ? 0 : read_sanitised_ftr_reg(id); 1129 1130 if (id == SYS_ID_AA64PFR0_EL1) { 1131 if (!vcpu_has_sve(vcpu)) 1132 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); 1133 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); 1134 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { 1135 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | 1136 (0xfUL << ID_AA64ISAR1_API_SHIFT) | 1137 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) | 1138 (0xfUL << ID_AA64ISAR1_GPI_SHIFT)); 1139 } else if (id == SYS_ID_AA64DFR0_EL1) { 1140 /* Limit guests to PMUv3 for ARMv8.1 */ 1141 val = cpuid_feature_cap_perfmon_field(val, 1142 ID_AA64DFR0_PMUVER_SHIFT, 1143 ID_AA64DFR0_PMUVER_8_1); 1144 } else if (id == SYS_ID_DFR0_EL1) { 1145 /* Limit guests to PMUv3 for ARMv8.1 */ 1146 val = cpuid_feature_cap_perfmon_field(val, 1147 ID_DFR0_PERFMON_SHIFT, 1148 ID_DFR0_PERFMON_8_1); 1149 } 1150 1151 return val; 1152 } 1153 1154 /* cpufeature ID register access trap handlers */ 1155 1156 static bool __access_id_reg(struct kvm_vcpu *vcpu, 1157 struct sys_reg_params *p, 1158 const struct sys_reg_desc *r, 1159 bool raz) 1160 { 1161 if (p->is_write) 1162 return write_to_read_only(vcpu, p, r); 1163 1164 p->regval = read_id_reg(vcpu, r, raz); 1165 return true; 1166 } 1167 1168 static bool access_id_reg(struct kvm_vcpu *vcpu, 1169 struct sys_reg_params *p, 1170 const struct sys_reg_desc *r) 1171 { 1172 return __access_id_reg(vcpu, p, r, false); 1173 } 1174 1175 static bool access_raz_id_reg(struct kvm_vcpu *vcpu, 1176 struct sys_reg_params *p, 1177 const struct sys_reg_desc *r) 1178 { 1179 return __access_id_reg(vcpu, p, r, true); 1180 } 1181 1182 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id); 1183 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id); 1184 static u64 sys_reg_to_index(const struct sys_reg_desc *reg); 1185 1186 /* Visibility overrides for SVE-specific control registers */ 1187 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu, 1188 const struct sys_reg_desc *rd) 1189 { 1190 if (vcpu_has_sve(vcpu)) 1191 return 0; 1192 1193 return REG_HIDDEN_USER | REG_HIDDEN_GUEST; 1194 } 1195 1196 /* Visibility overrides for SVE-specific ID registers */ 1197 static unsigned int sve_id_visibility(const struct kvm_vcpu *vcpu, 1198 const struct sys_reg_desc *rd) 1199 { 1200 if (vcpu_has_sve(vcpu)) 1201 return 0; 1202 1203 return REG_HIDDEN_USER; 1204 } 1205 1206 /* Generate the emulated ID_AA64ZFR0_EL1 value exposed to the guest */ 1207 static u64 guest_id_aa64zfr0_el1(const struct kvm_vcpu *vcpu) 1208 { 1209 if (!vcpu_has_sve(vcpu)) 1210 return 0; 1211 1212 return read_sanitised_ftr_reg(SYS_ID_AA64ZFR0_EL1); 1213 } 1214 1215 static bool access_id_aa64zfr0_el1(struct kvm_vcpu *vcpu, 1216 struct sys_reg_params *p, 1217 const struct sys_reg_desc *rd) 1218 { 1219 if (p->is_write) 1220 return write_to_read_only(vcpu, p, rd); 1221 1222 p->regval = guest_id_aa64zfr0_el1(vcpu); 1223 return true; 1224 } 1225 1226 static int get_id_aa64zfr0_el1(struct kvm_vcpu *vcpu, 1227 const struct sys_reg_desc *rd, 1228 const struct kvm_one_reg *reg, void __user *uaddr) 1229 { 1230 u64 val; 1231 1232 if (WARN_ON(!vcpu_has_sve(vcpu))) 1233 return -ENOENT; 1234 1235 val = guest_id_aa64zfr0_el1(vcpu); 1236 return reg_to_user(uaddr, &val, reg->id); 1237 } 1238 1239 static int set_id_aa64zfr0_el1(struct kvm_vcpu *vcpu, 1240 const struct sys_reg_desc *rd, 1241 const struct kvm_one_reg *reg, void __user *uaddr) 1242 { 1243 const u64 id = sys_reg_to_index(rd); 1244 int err; 1245 u64 val; 1246 1247 if (WARN_ON(!vcpu_has_sve(vcpu))) 1248 return -ENOENT; 1249 1250 err = reg_from_user(&val, uaddr, id); 1251 if (err) 1252 return err; 1253 1254 /* This is what we mean by invariant: you can't change it. */ 1255 if (val != guest_id_aa64zfr0_el1(vcpu)) 1256 return -EINVAL; 1257 1258 return 0; 1259 } 1260 1261 /* 1262 * cpufeature ID register user accessors 1263 * 1264 * For now, these registers are immutable for userspace, so no values 1265 * are stored, and for set_id_reg() we don't allow the effective value 1266 * to be changed. 1267 */ 1268 static int __get_id_reg(const struct kvm_vcpu *vcpu, 1269 const struct sys_reg_desc *rd, void __user *uaddr, 1270 bool raz) 1271 { 1272 const u64 id = sys_reg_to_index(rd); 1273 const u64 val = read_id_reg(vcpu, rd, raz); 1274 1275 return reg_to_user(uaddr, &val, id); 1276 } 1277 1278 static int __set_id_reg(const struct kvm_vcpu *vcpu, 1279 const struct sys_reg_desc *rd, void __user *uaddr, 1280 bool raz) 1281 { 1282 const u64 id = sys_reg_to_index(rd); 1283 int err; 1284 u64 val; 1285 1286 err = reg_from_user(&val, uaddr, id); 1287 if (err) 1288 return err; 1289 1290 /* This is what we mean by invariant: you can't change it. */ 1291 if (val != read_id_reg(vcpu, rd, raz)) 1292 return -EINVAL; 1293 1294 return 0; 1295 } 1296 1297 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1298 const struct kvm_one_reg *reg, void __user *uaddr) 1299 { 1300 return __get_id_reg(vcpu, rd, uaddr, false); 1301 } 1302 1303 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1304 const struct kvm_one_reg *reg, void __user *uaddr) 1305 { 1306 return __set_id_reg(vcpu, rd, uaddr, false); 1307 } 1308 1309 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1310 const struct kvm_one_reg *reg, void __user *uaddr) 1311 { 1312 return __get_id_reg(vcpu, rd, uaddr, true); 1313 } 1314 1315 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, 1316 const struct kvm_one_reg *reg, void __user *uaddr) 1317 { 1318 return __set_id_reg(vcpu, rd, uaddr, true); 1319 } 1320 1321 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1322 const struct sys_reg_desc *r) 1323 { 1324 if (p->is_write) 1325 return write_to_read_only(vcpu, p, r); 1326 1327 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0); 1328 return true; 1329 } 1330 1331 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1332 const struct sys_reg_desc *r) 1333 { 1334 if (p->is_write) 1335 return write_to_read_only(vcpu, p, r); 1336 1337 p->regval = read_sysreg(clidr_el1); 1338 return true; 1339 } 1340 1341 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1342 const struct sys_reg_desc *r) 1343 { 1344 int reg = r->reg; 1345 1346 /* See the 32bit mapping in kvm_host.h */ 1347 if (p->is_aarch32) 1348 reg = r->reg / 2; 1349 1350 if (p->is_write) 1351 vcpu_write_sys_reg(vcpu, p->regval, reg); 1352 else 1353 p->regval = vcpu_read_sys_reg(vcpu, reg); 1354 return true; 1355 } 1356 1357 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, 1358 const struct sys_reg_desc *r) 1359 { 1360 u32 csselr; 1361 1362 if (p->is_write) 1363 return write_to_read_only(vcpu, p, r); 1364 1365 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1); 1366 p->regval = get_ccsidr(csselr); 1367 1368 /* 1369 * Guests should not be doing cache operations by set/way at all, and 1370 * for this reason, we trap them and attempt to infer the intent, so 1371 * that we can flush the entire guest's address space at the appropriate 1372 * time. 1373 * To prevent this trapping from causing performance problems, let's 1374 * expose the geometry of all data and unified caches (which are 1375 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way. 1376 * [If guests should attempt to infer aliasing properties from the 1377 * geometry (which is not permitted by the architecture), they would 1378 * only do so for virtually indexed caches.] 1379 */ 1380 if (!(csselr & 1)) // data or unified cache 1381 p->regval &= ~GENMASK(27, 3); 1382 return true; 1383 } 1384 1385 /* sys_reg_desc initialiser for known cpufeature ID registers */ 1386 #define ID_SANITISED(name) { \ 1387 SYS_DESC(SYS_##name), \ 1388 .access = access_id_reg, \ 1389 .get_user = get_id_reg, \ 1390 .set_user = set_id_reg, \ 1391 } 1392 1393 /* 1394 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID 1395 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2 1396 * (1 <= crm < 8, 0 <= Op2 < 8). 1397 */ 1398 #define ID_UNALLOCATED(crm, op2) { \ 1399 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \ 1400 .access = access_raz_id_reg, \ 1401 .get_user = get_raz_id_reg, \ 1402 .set_user = set_raz_id_reg, \ 1403 } 1404 1405 /* 1406 * sys_reg_desc initialiser for known ID registers that we hide from guests. 1407 * For now, these are exposed just like unallocated ID regs: they appear 1408 * RAZ for the guest. 1409 */ 1410 #define ID_HIDDEN(name) { \ 1411 SYS_DESC(SYS_##name), \ 1412 .access = access_raz_id_reg, \ 1413 .get_user = get_raz_id_reg, \ 1414 .set_user = set_raz_id_reg, \ 1415 } 1416 1417 /* 1418 * Architected system registers. 1419 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 1420 * 1421 * Debug handling: We do trap most, if not all debug related system 1422 * registers. The implementation is good enough to ensure that a guest 1423 * can use these with minimal performance degradation. The drawback is 1424 * that we don't implement any of the external debug, none of the 1425 * OSlock protocol. This should be revisited if we ever encounter a 1426 * more demanding guest... 1427 */ 1428 static const struct sys_reg_desc sys_reg_descs[] = { 1429 { SYS_DESC(SYS_DC_ISW), access_dcsw }, 1430 { SYS_DESC(SYS_DC_CSW), access_dcsw }, 1431 { SYS_DESC(SYS_DC_CISW), access_dcsw }, 1432 1433 DBG_BCR_BVR_WCR_WVR_EL1(0), 1434 DBG_BCR_BVR_WCR_WVR_EL1(1), 1435 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 }, 1436 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 }, 1437 DBG_BCR_BVR_WCR_WVR_EL1(2), 1438 DBG_BCR_BVR_WCR_WVR_EL1(3), 1439 DBG_BCR_BVR_WCR_WVR_EL1(4), 1440 DBG_BCR_BVR_WCR_WVR_EL1(5), 1441 DBG_BCR_BVR_WCR_WVR_EL1(6), 1442 DBG_BCR_BVR_WCR_WVR_EL1(7), 1443 DBG_BCR_BVR_WCR_WVR_EL1(8), 1444 DBG_BCR_BVR_WCR_WVR_EL1(9), 1445 DBG_BCR_BVR_WCR_WVR_EL1(10), 1446 DBG_BCR_BVR_WCR_WVR_EL1(11), 1447 DBG_BCR_BVR_WCR_WVR_EL1(12), 1448 DBG_BCR_BVR_WCR_WVR_EL1(13), 1449 DBG_BCR_BVR_WCR_WVR_EL1(14), 1450 DBG_BCR_BVR_WCR_WVR_EL1(15), 1451 1452 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi }, 1453 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi }, 1454 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 }, 1455 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi }, 1456 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi }, 1457 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi }, 1458 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi }, 1459 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 }, 1460 1461 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi }, 1462 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi }, 1463 // DBGDTR[TR]X_EL0 share the same encoding 1464 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi }, 1465 1466 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 }, 1467 1468 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 }, 1469 1470 /* 1471 * ID regs: all ID_SANITISED() entries here must have corresponding 1472 * entries in arm64_ftr_regs[]. 1473 */ 1474 1475 /* AArch64 mappings of the AArch32 ID registers */ 1476 /* CRm=1 */ 1477 ID_SANITISED(ID_PFR0_EL1), 1478 ID_SANITISED(ID_PFR1_EL1), 1479 ID_SANITISED(ID_DFR0_EL1), 1480 ID_HIDDEN(ID_AFR0_EL1), 1481 ID_SANITISED(ID_MMFR0_EL1), 1482 ID_SANITISED(ID_MMFR1_EL1), 1483 ID_SANITISED(ID_MMFR2_EL1), 1484 ID_SANITISED(ID_MMFR3_EL1), 1485 1486 /* CRm=2 */ 1487 ID_SANITISED(ID_ISAR0_EL1), 1488 ID_SANITISED(ID_ISAR1_EL1), 1489 ID_SANITISED(ID_ISAR2_EL1), 1490 ID_SANITISED(ID_ISAR3_EL1), 1491 ID_SANITISED(ID_ISAR4_EL1), 1492 ID_SANITISED(ID_ISAR5_EL1), 1493 ID_SANITISED(ID_MMFR4_EL1), 1494 ID_SANITISED(ID_ISAR6_EL1), 1495 1496 /* CRm=3 */ 1497 ID_SANITISED(MVFR0_EL1), 1498 ID_SANITISED(MVFR1_EL1), 1499 ID_SANITISED(MVFR2_EL1), 1500 ID_UNALLOCATED(3,3), 1501 ID_SANITISED(ID_PFR2_EL1), 1502 ID_HIDDEN(ID_DFR1_EL1), 1503 ID_SANITISED(ID_MMFR5_EL1), 1504 ID_UNALLOCATED(3,7), 1505 1506 /* AArch64 ID registers */ 1507 /* CRm=4 */ 1508 ID_SANITISED(ID_AA64PFR0_EL1), 1509 ID_SANITISED(ID_AA64PFR1_EL1), 1510 ID_UNALLOCATED(4,2), 1511 ID_UNALLOCATED(4,3), 1512 { SYS_DESC(SYS_ID_AA64ZFR0_EL1), access_id_aa64zfr0_el1, .get_user = get_id_aa64zfr0_el1, .set_user = set_id_aa64zfr0_el1, .visibility = sve_id_visibility }, 1513 ID_UNALLOCATED(4,5), 1514 ID_UNALLOCATED(4,6), 1515 ID_UNALLOCATED(4,7), 1516 1517 /* CRm=5 */ 1518 ID_SANITISED(ID_AA64DFR0_EL1), 1519 ID_SANITISED(ID_AA64DFR1_EL1), 1520 ID_UNALLOCATED(5,2), 1521 ID_UNALLOCATED(5,3), 1522 ID_HIDDEN(ID_AA64AFR0_EL1), 1523 ID_HIDDEN(ID_AA64AFR1_EL1), 1524 ID_UNALLOCATED(5,6), 1525 ID_UNALLOCATED(5,7), 1526 1527 /* CRm=6 */ 1528 ID_SANITISED(ID_AA64ISAR0_EL1), 1529 ID_SANITISED(ID_AA64ISAR1_EL1), 1530 ID_UNALLOCATED(6,2), 1531 ID_UNALLOCATED(6,3), 1532 ID_UNALLOCATED(6,4), 1533 ID_UNALLOCATED(6,5), 1534 ID_UNALLOCATED(6,6), 1535 ID_UNALLOCATED(6,7), 1536 1537 /* CRm=7 */ 1538 ID_SANITISED(ID_AA64MMFR0_EL1), 1539 ID_SANITISED(ID_AA64MMFR1_EL1), 1540 ID_SANITISED(ID_AA64MMFR2_EL1), 1541 ID_UNALLOCATED(7,3), 1542 ID_UNALLOCATED(7,4), 1543 ID_UNALLOCATED(7,5), 1544 ID_UNALLOCATED(7,6), 1545 ID_UNALLOCATED(7,7), 1546 1547 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 }, 1548 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 }, 1549 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 }, 1550 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility }, 1551 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 }, 1552 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 }, 1553 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 }, 1554 1555 PTRAUTH_KEY(APIA), 1556 PTRAUTH_KEY(APIB), 1557 PTRAUTH_KEY(APDA), 1558 PTRAUTH_KEY(APDB), 1559 PTRAUTH_KEY(APGA), 1560 1561 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 }, 1562 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 }, 1563 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 }, 1564 1565 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi }, 1566 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi }, 1567 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi }, 1568 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi }, 1569 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi }, 1570 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi }, 1571 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi }, 1572 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi }, 1573 1574 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 }, 1575 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 }, 1576 1577 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, 1578 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 }, 1579 1580 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 }, 1581 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 }, 1582 1583 { SYS_DESC(SYS_LORSA_EL1), trap_loregion }, 1584 { SYS_DESC(SYS_LOREA_EL1), trap_loregion }, 1585 { SYS_DESC(SYS_LORN_EL1), trap_loregion }, 1586 { SYS_DESC(SYS_LORC_EL1), trap_loregion }, 1587 { SYS_DESC(SYS_LORID_EL1), trap_loregion }, 1588 1589 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 }, 1590 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 }, 1591 1592 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only }, 1593 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only }, 1594 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only }, 1595 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only }, 1596 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only }, 1597 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi }, 1598 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi }, 1599 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi }, 1600 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only }, 1601 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only }, 1602 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only }, 1603 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre }, 1604 1605 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 }, 1606 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 }, 1607 1608 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0}, 1609 1610 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr }, 1611 { SYS_DESC(SYS_CLIDR_EL1), access_clidr }, 1612 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 }, 1613 { SYS_DESC(SYS_CTR_EL0), access_ctr }, 1614 1615 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 }, 1616 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, 1617 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 }, 1618 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, 1619 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 }, 1620 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 }, 1621 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid }, 1622 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid }, 1623 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 }, 1624 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper }, 1625 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr }, 1626 /* 1627 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero 1628 * in 32bit mode. Here we choose to reset it as zero for consistency. 1629 */ 1630 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 }, 1631 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 }, 1632 1633 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 }, 1634 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 }, 1635 1636 { SYS_DESC(SYS_AMCR_EL0), access_amu }, 1637 { SYS_DESC(SYS_AMCFGR_EL0), access_amu }, 1638 { SYS_DESC(SYS_AMCGCR_EL0), access_amu }, 1639 { SYS_DESC(SYS_AMUSERENR_EL0), access_amu }, 1640 { SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu }, 1641 { SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu }, 1642 { SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu }, 1643 { SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu }, 1644 AMU_AMEVCNTR0_EL0(0), 1645 AMU_AMEVCNTR0_EL0(1), 1646 AMU_AMEVCNTR0_EL0(2), 1647 AMU_AMEVCNTR0_EL0(3), 1648 AMU_AMEVCNTR0_EL0(4), 1649 AMU_AMEVCNTR0_EL0(5), 1650 AMU_AMEVCNTR0_EL0(6), 1651 AMU_AMEVCNTR0_EL0(7), 1652 AMU_AMEVCNTR0_EL0(8), 1653 AMU_AMEVCNTR0_EL0(9), 1654 AMU_AMEVCNTR0_EL0(10), 1655 AMU_AMEVCNTR0_EL0(11), 1656 AMU_AMEVCNTR0_EL0(12), 1657 AMU_AMEVCNTR0_EL0(13), 1658 AMU_AMEVCNTR0_EL0(14), 1659 AMU_AMEVCNTR0_EL0(15), 1660 AMU_AMEVTYPER0_EL0(0), 1661 AMU_AMEVTYPER0_EL0(1), 1662 AMU_AMEVTYPER0_EL0(2), 1663 AMU_AMEVTYPER0_EL0(3), 1664 AMU_AMEVTYPER0_EL0(4), 1665 AMU_AMEVTYPER0_EL0(5), 1666 AMU_AMEVTYPER0_EL0(6), 1667 AMU_AMEVTYPER0_EL0(7), 1668 AMU_AMEVTYPER0_EL0(8), 1669 AMU_AMEVTYPER0_EL0(9), 1670 AMU_AMEVTYPER0_EL0(10), 1671 AMU_AMEVTYPER0_EL0(11), 1672 AMU_AMEVTYPER0_EL0(12), 1673 AMU_AMEVTYPER0_EL0(13), 1674 AMU_AMEVTYPER0_EL0(14), 1675 AMU_AMEVTYPER0_EL0(15), 1676 AMU_AMEVCNTR1_EL0(0), 1677 AMU_AMEVCNTR1_EL0(1), 1678 AMU_AMEVCNTR1_EL0(2), 1679 AMU_AMEVCNTR1_EL0(3), 1680 AMU_AMEVCNTR1_EL0(4), 1681 AMU_AMEVCNTR1_EL0(5), 1682 AMU_AMEVCNTR1_EL0(6), 1683 AMU_AMEVCNTR1_EL0(7), 1684 AMU_AMEVCNTR1_EL0(8), 1685 AMU_AMEVCNTR1_EL0(9), 1686 AMU_AMEVCNTR1_EL0(10), 1687 AMU_AMEVCNTR1_EL0(11), 1688 AMU_AMEVCNTR1_EL0(12), 1689 AMU_AMEVCNTR1_EL0(13), 1690 AMU_AMEVCNTR1_EL0(14), 1691 AMU_AMEVCNTR1_EL0(15), 1692 AMU_AMEVTYPER1_EL0(0), 1693 AMU_AMEVTYPER1_EL0(1), 1694 AMU_AMEVTYPER1_EL0(2), 1695 AMU_AMEVTYPER1_EL0(3), 1696 AMU_AMEVTYPER1_EL0(4), 1697 AMU_AMEVTYPER1_EL0(5), 1698 AMU_AMEVTYPER1_EL0(6), 1699 AMU_AMEVTYPER1_EL0(7), 1700 AMU_AMEVTYPER1_EL0(8), 1701 AMU_AMEVTYPER1_EL0(9), 1702 AMU_AMEVTYPER1_EL0(10), 1703 AMU_AMEVTYPER1_EL0(11), 1704 AMU_AMEVTYPER1_EL0(12), 1705 AMU_AMEVTYPER1_EL0(13), 1706 AMU_AMEVTYPER1_EL0(14), 1707 AMU_AMEVTYPER1_EL0(15), 1708 1709 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer }, 1710 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer }, 1711 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer }, 1712 1713 /* PMEVCNTRn_EL0 */ 1714 PMU_PMEVCNTR_EL0(0), 1715 PMU_PMEVCNTR_EL0(1), 1716 PMU_PMEVCNTR_EL0(2), 1717 PMU_PMEVCNTR_EL0(3), 1718 PMU_PMEVCNTR_EL0(4), 1719 PMU_PMEVCNTR_EL0(5), 1720 PMU_PMEVCNTR_EL0(6), 1721 PMU_PMEVCNTR_EL0(7), 1722 PMU_PMEVCNTR_EL0(8), 1723 PMU_PMEVCNTR_EL0(9), 1724 PMU_PMEVCNTR_EL0(10), 1725 PMU_PMEVCNTR_EL0(11), 1726 PMU_PMEVCNTR_EL0(12), 1727 PMU_PMEVCNTR_EL0(13), 1728 PMU_PMEVCNTR_EL0(14), 1729 PMU_PMEVCNTR_EL0(15), 1730 PMU_PMEVCNTR_EL0(16), 1731 PMU_PMEVCNTR_EL0(17), 1732 PMU_PMEVCNTR_EL0(18), 1733 PMU_PMEVCNTR_EL0(19), 1734 PMU_PMEVCNTR_EL0(20), 1735 PMU_PMEVCNTR_EL0(21), 1736 PMU_PMEVCNTR_EL0(22), 1737 PMU_PMEVCNTR_EL0(23), 1738 PMU_PMEVCNTR_EL0(24), 1739 PMU_PMEVCNTR_EL0(25), 1740 PMU_PMEVCNTR_EL0(26), 1741 PMU_PMEVCNTR_EL0(27), 1742 PMU_PMEVCNTR_EL0(28), 1743 PMU_PMEVCNTR_EL0(29), 1744 PMU_PMEVCNTR_EL0(30), 1745 /* PMEVTYPERn_EL0 */ 1746 PMU_PMEVTYPER_EL0(0), 1747 PMU_PMEVTYPER_EL0(1), 1748 PMU_PMEVTYPER_EL0(2), 1749 PMU_PMEVTYPER_EL0(3), 1750 PMU_PMEVTYPER_EL0(4), 1751 PMU_PMEVTYPER_EL0(5), 1752 PMU_PMEVTYPER_EL0(6), 1753 PMU_PMEVTYPER_EL0(7), 1754 PMU_PMEVTYPER_EL0(8), 1755 PMU_PMEVTYPER_EL0(9), 1756 PMU_PMEVTYPER_EL0(10), 1757 PMU_PMEVTYPER_EL0(11), 1758 PMU_PMEVTYPER_EL0(12), 1759 PMU_PMEVTYPER_EL0(13), 1760 PMU_PMEVTYPER_EL0(14), 1761 PMU_PMEVTYPER_EL0(15), 1762 PMU_PMEVTYPER_EL0(16), 1763 PMU_PMEVTYPER_EL0(17), 1764 PMU_PMEVTYPER_EL0(18), 1765 PMU_PMEVTYPER_EL0(19), 1766 PMU_PMEVTYPER_EL0(20), 1767 PMU_PMEVTYPER_EL0(21), 1768 PMU_PMEVTYPER_EL0(22), 1769 PMU_PMEVTYPER_EL0(23), 1770 PMU_PMEVTYPER_EL0(24), 1771 PMU_PMEVTYPER_EL0(25), 1772 PMU_PMEVTYPER_EL0(26), 1773 PMU_PMEVTYPER_EL0(27), 1774 PMU_PMEVTYPER_EL0(28), 1775 PMU_PMEVTYPER_EL0(29), 1776 PMU_PMEVTYPER_EL0(30), 1777 /* 1778 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero 1779 * in 32bit mode. Here we choose to reset it as zero for consistency. 1780 */ 1781 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 }, 1782 1783 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, 1784 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, 1785 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, 1786 }; 1787 1788 static bool trap_dbgidr(struct kvm_vcpu *vcpu, 1789 struct sys_reg_params *p, 1790 const struct sys_reg_desc *r) 1791 { 1792 if (p->is_write) { 1793 return ignore_write(vcpu, p); 1794 } else { 1795 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1796 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1797 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); 1798 1799 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | 1800 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | 1801 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) 1802 | (6 << 16) | (el3 << 14) | (el3 << 12)); 1803 return true; 1804 } 1805 } 1806 1807 static bool trap_debug32(struct kvm_vcpu *vcpu, 1808 struct sys_reg_params *p, 1809 const struct sys_reg_desc *r) 1810 { 1811 if (p->is_write) { 1812 vcpu_cp14(vcpu, r->reg) = p->regval; 1813 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 1814 } else { 1815 p->regval = vcpu_cp14(vcpu, r->reg); 1816 } 1817 1818 return true; 1819 } 1820 1821 /* AArch32 debug register mappings 1822 * 1823 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0] 1824 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32] 1825 * 1826 * All control registers and watchpoint value registers are mapped to 1827 * the lower 32 bits of their AArch64 equivalents. We share the trap 1828 * handlers with the above AArch64 code which checks what mode the 1829 * system is in. 1830 */ 1831 1832 static bool trap_xvr(struct kvm_vcpu *vcpu, 1833 struct sys_reg_params *p, 1834 const struct sys_reg_desc *rd) 1835 { 1836 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg]; 1837 1838 if (p->is_write) { 1839 u64 val = *dbg_reg; 1840 1841 val &= 0xffffffffUL; 1842 val |= p->regval << 32; 1843 *dbg_reg = val; 1844 1845 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY; 1846 } else { 1847 p->regval = *dbg_reg >> 32; 1848 } 1849 1850 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg); 1851 1852 return true; 1853 } 1854 1855 #define DBG_BCR_BVR_WCR_WVR(n) \ 1856 /* DBGBVRn */ \ 1857 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \ 1858 /* DBGBCRn */ \ 1859 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \ 1860 /* DBGWVRn */ \ 1861 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \ 1862 /* DBGWCRn */ \ 1863 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n } 1864 1865 #define DBGBXVR(n) \ 1866 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n } 1867 1868 /* 1869 * Trapped cp14 registers. We generally ignore most of the external 1870 * debug, on the principle that they don't really make sense to a 1871 * guest. Revisit this one day, would this principle change. 1872 */ 1873 static const struct sys_reg_desc cp14_regs[] = { 1874 /* DBGIDR */ 1875 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr }, 1876 /* DBGDTRRXext */ 1877 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi }, 1878 1879 DBG_BCR_BVR_WCR_WVR(0), 1880 /* DBGDSCRint */ 1881 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi }, 1882 DBG_BCR_BVR_WCR_WVR(1), 1883 /* DBGDCCINT */ 1884 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 }, 1885 /* DBGDSCRext */ 1886 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 }, 1887 DBG_BCR_BVR_WCR_WVR(2), 1888 /* DBGDTR[RT]Xint */ 1889 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi }, 1890 /* DBGDTR[RT]Xext */ 1891 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi }, 1892 DBG_BCR_BVR_WCR_WVR(3), 1893 DBG_BCR_BVR_WCR_WVR(4), 1894 DBG_BCR_BVR_WCR_WVR(5), 1895 /* DBGWFAR */ 1896 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi }, 1897 /* DBGOSECCR */ 1898 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi }, 1899 DBG_BCR_BVR_WCR_WVR(6), 1900 /* DBGVCR */ 1901 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 }, 1902 DBG_BCR_BVR_WCR_WVR(7), 1903 DBG_BCR_BVR_WCR_WVR(8), 1904 DBG_BCR_BVR_WCR_WVR(9), 1905 DBG_BCR_BVR_WCR_WVR(10), 1906 DBG_BCR_BVR_WCR_WVR(11), 1907 DBG_BCR_BVR_WCR_WVR(12), 1908 DBG_BCR_BVR_WCR_WVR(13), 1909 DBG_BCR_BVR_WCR_WVR(14), 1910 DBG_BCR_BVR_WCR_WVR(15), 1911 1912 /* DBGDRAR (32bit) */ 1913 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi }, 1914 1915 DBGBXVR(0), 1916 /* DBGOSLAR */ 1917 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi }, 1918 DBGBXVR(1), 1919 /* DBGOSLSR */ 1920 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 }, 1921 DBGBXVR(2), 1922 DBGBXVR(3), 1923 /* DBGOSDLR */ 1924 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi }, 1925 DBGBXVR(4), 1926 /* DBGPRCR */ 1927 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi }, 1928 DBGBXVR(5), 1929 DBGBXVR(6), 1930 DBGBXVR(7), 1931 DBGBXVR(8), 1932 DBGBXVR(9), 1933 DBGBXVR(10), 1934 DBGBXVR(11), 1935 DBGBXVR(12), 1936 DBGBXVR(13), 1937 DBGBXVR(14), 1938 DBGBXVR(15), 1939 1940 /* DBGDSAR (32bit) */ 1941 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi }, 1942 1943 /* DBGDEVID2 */ 1944 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi }, 1945 /* DBGDEVID1 */ 1946 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi }, 1947 /* DBGDEVID */ 1948 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi }, 1949 /* DBGCLAIMSET */ 1950 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi }, 1951 /* DBGCLAIMCLR */ 1952 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi }, 1953 /* DBGAUTHSTATUS */ 1954 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 }, 1955 }; 1956 1957 /* Trapped cp14 64bit registers */ 1958 static const struct sys_reg_desc cp14_64_regs[] = { 1959 /* DBGDRAR (64bit) */ 1960 { Op1( 0), CRm( 1), .access = trap_raz_wi }, 1961 1962 /* DBGDSAR (64bit) */ 1963 { Op1( 0), CRm( 2), .access = trap_raz_wi }, 1964 }; 1965 1966 /* Macro to expand the PMEVCNTRn register */ 1967 #define PMU_PMEVCNTR(n) \ 1968 /* PMEVCNTRn */ \ 1969 { Op1(0), CRn(0b1110), \ 1970 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1971 access_pmu_evcntr } 1972 1973 /* Macro to expand the PMEVTYPERn register */ 1974 #define PMU_PMEVTYPER(n) \ 1975 /* PMEVTYPERn */ \ 1976 { Op1(0), CRn(0b1110), \ 1977 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \ 1978 access_pmu_evtyper } 1979 1980 /* 1981 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding, 1982 * depending on the way they are accessed (as a 32bit or a 64bit 1983 * register). 1984 */ 1985 static const struct sys_reg_desc cp15_regs[] = { 1986 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr }, 1987 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR }, 1988 { Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr }, 1989 { Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr }, 1990 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, 1991 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 }, 1992 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR }, 1993 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR }, 1994 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR }, 1995 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR }, 1996 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR }, 1997 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR }, 1998 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR }, 1999 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR }, 2000 2001 /* 2002 * DC{C,I,CI}SW operations: 2003 */ 2004 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw }, 2005 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw }, 2006 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw }, 2007 2008 /* PMU */ 2009 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr }, 2010 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten }, 2011 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten }, 2012 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs }, 2013 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc }, 2014 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr }, 2015 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid }, 2016 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid }, 2017 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr }, 2018 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper }, 2019 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr }, 2020 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr }, 2021 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten }, 2022 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten }, 2023 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs }, 2024 2025 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR }, 2026 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR }, 2027 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 }, 2028 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 }, 2029 2030 /* ICC_SRE */ 2031 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre }, 2032 2033 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID }, 2034 2035 /* Arch Tmers */ 2036 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer }, 2037 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer }, 2038 2039 /* PMEVCNTRn */ 2040 PMU_PMEVCNTR(0), 2041 PMU_PMEVCNTR(1), 2042 PMU_PMEVCNTR(2), 2043 PMU_PMEVCNTR(3), 2044 PMU_PMEVCNTR(4), 2045 PMU_PMEVCNTR(5), 2046 PMU_PMEVCNTR(6), 2047 PMU_PMEVCNTR(7), 2048 PMU_PMEVCNTR(8), 2049 PMU_PMEVCNTR(9), 2050 PMU_PMEVCNTR(10), 2051 PMU_PMEVCNTR(11), 2052 PMU_PMEVCNTR(12), 2053 PMU_PMEVCNTR(13), 2054 PMU_PMEVCNTR(14), 2055 PMU_PMEVCNTR(15), 2056 PMU_PMEVCNTR(16), 2057 PMU_PMEVCNTR(17), 2058 PMU_PMEVCNTR(18), 2059 PMU_PMEVCNTR(19), 2060 PMU_PMEVCNTR(20), 2061 PMU_PMEVCNTR(21), 2062 PMU_PMEVCNTR(22), 2063 PMU_PMEVCNTR(23), 2064 PMU_PMEVCNTR(24), 2065 PMU_PMEVCNTR(25), 2066 PMU_PMEVCNTR(26), 2067 PMU_PMEVCNTR(27), 2068 PMU_PMEVCNTR(28), 2069 PMU_PMEVCNTR(29), 2070 PMU_PMEVCNTR(30), 2071 /* PMEVTYPERn */ 2072 PMU_PMEVTYPER(0), 2073 PMU_PMEVTYPER(1), 2074 PMU_PMEVTYPER(2), 2075 PMU_PMEVTYPER(3), 2076 PMU_PMEVTYPER(4), 2077 PMU_PMEVTYPER(5), 2078 PMU_PMEVTYPER(6), 2079 PMU_PMEVTYPER(7), 2080 PMU_PMEVTYPER(8), 2081 PMU_PMEVTYPER(9), 2082 PMU_PMEVTYPER(10), 2083 PMU_PMEVTYPER(11), 2084 PMU_PMEVTYPER(12), 2085 PMU_PMEVTYPER(13), 2086 PMU_PMEVTYPER(14), 2087 PMU_PMEVTYPER(15), 2088 PMU_PMEVTYPER(16), 2089 PMU_PMEVTYPER(17), 2090 PMU_PMEVTYPER(18), 2091 PMU_PMEVTYPER(19), 2092 PMU_PMEVTYPER(20), 2093 PMU_PMEVTYPER(21), 2094 PMU_PMEVTYPER(22), 2095 PMU_PMEVTYPER(23), 2096 PMU_PMEVTYPER(24), 2097 PMU_PMEVTYPER(25), 2098 PMU_PMEVTYPER(26), 2099 PMU_PMEVTYPER(27), 2100 PMU_PMEVTYPER(28), 2101 PMU_PMEVTYPER(29), 2102 PMU_PMEVTYPER(30), 2103 /* PMCCFILTR */ 2104 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper }, 2105 2106 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr }, 2107 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr }, 2108 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR }, 2109 }; 2110 2111 static const struct sys_reg_desc cp15_64_regs[] = { 2112 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 }, 2113 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr }, 2114 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */ 2115 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 }, 2116 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */ 2117 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */ 2118 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer }, 2119 }; 2120 2121 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n, 2122 bool is_32) 2123 { 2124 unsigned int i; 2125 2126 for (i = 0; i < n; i++) { 2127 if (!is_32 && table[i].reg && !table[i].reset) { 2128 kvm_err("sys_reg table %p entry %d has lacks reset\n", 2129 table, i); 2130 return 1; 2131 } 2132 2133 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) { 2134 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1); 2135 return 1; 2136 } 2137 } 2138 2139 return 0; 2140 } 2141 2142 static int match_sys_reg(const void *key, const void *elt) 2143 { 2144 const unsigned long pval = (unsigned long)key; 2145 const struct sys_reg_desc *r = elt; 2146 2147 return pval - reg_to_encoding(r); 2148 } 2149 2150 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params, 2151 const struct sys_reg_desc table[], 2152 unsigned int num) 2153 { 2154 unsigned long pval = reg_to_encoding(params); 2155 2156 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg); 2157 } 2158 2159 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu) 2160 { 2161 kvm_inject_undefined(vcpu); 2162 return 1; 2163 } 2164 2165 static void perform_access(struct kvm_vcpu *vcpu, 2166 struct sys_reg_params *params, 2167 const struct sys_reg_desc *r) 2168 { 2169 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r); 2170 2171 /* Check for regs disabled by runtime config */ 2172 if (sysreg_hidden_from_guest(vcpu, r)) { 2173 kvm_inject_undefined(vcpu); 2174 return; 2175 } 2176 2177 /* 2178 * Not having an accessor means that we have configured a trap 2179 * that we don't know how to handle. This certainly qualifies 2180 * as a gross bug that should be fixed right away. 2181 */ 2182 BUG_ON(!r->access); 2183 2184 /* Skip instruction if instructed so */ 2185 if (likely(r->access(vcpu, params, r))) 2186 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu)); 2187 } 2188 2189 /* 2190 * emulate_cp -- tries to match a sys_reg access in a handling table, and 2191 * call the corresponding trap handler. 2192 * 2193 * @params: pointer to the descriptor of the access 2194 * @table: array of trap descriptors 2195 * @num: size of the trap descriptor array 2196 * 2197 * Return 0 if the access has been handled, and -1 if not. 2198 */ 2199 static int emulate_cp(struct kvm_vcpu *vcpu, 2200 struct sys_reg_params *params, 2201 const struct sys_reg_desc *table, 2202 size_t num) 2203 { 2204 const struct sys_reg_desc *r; 2205 2206 if (!table) 2207 return -1; /* Not handled */ 2208 2209 r = find_reg(params, table, num); 2210 2211 if (r) { 2212 perform_access(vcpu, params, r); 2213 return 0; 2214 } 2215 2216 /* Not handled */ 2217 return -1; 2218 } 2219 2220 static void unhandled_cp_access(struct kvm_vcpu *vcpu, 2221 struct sys_reg_params *params) 2222 { 2223 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); 2224 int cp = -1; 2225 2226 switch (esr_ec) { 2227 case ESR_ELx_EC_CP15_32: 2228 case ESR_ELx_EC_CP15_64: 2229 cp = 15; 2230 break; 2231 case ESR_ELx_EC_CP14_MR: 2232 case ESR_ELx_EC_CP14_64: 2233 cp = 14; 2234 break; 2235 default: 2236 WARN_ON(1); 2237 } 2238 2239 print_sys_reg_msg(params, 2240 "Unsupported guest CP%d access at: %08lx [%08lx]\n", 2241 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2242 kvm_inject_undefined(vcpu); 2243 } 2244 2245 /** 2246 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access 2247 * @vcpu: The VCPU pointer 2248 * @run: The kvm_run struct 2249 */ 2250 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu, 2251 const struct sys_reg_desc *global, 2252 size_t nr_global) 2253 { 2254 struct sys_reg_params params; 2255 u32 esr = kvm_vcpu_get_esr(vcpu); 2256 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2257 int Rt2 = (esr >> 10) & 0x1f; 2258 2259 params.is_aarch32 = true; 2260 params.is_32bit = false; 2261 params.CRm = (esr >> 1) & 0xf; 2262 params.is_write = ((esr & 1) == 0); 2263 2264 params.Op0 = 0; 2265 params.Op1 = (esr >> 16) & 0xf; 2266 params.Op2 = 0; 2267 params.CRn = 0; 2268 2269 /* 2270 * Make a 64-bit value out of Rt and Rt2. As we use the same trap 2271 * backends between AArch32 and AArch64, we get away with it. 2272 */ 2273 if (params.is_write) { 2274 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff; 2275 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32; 2276 } 2277 2278 /* 2279 * If the table contains a handler, handle the 2280 * potential register operation in the case of a read and return 2281 * with success. 2282 */ 2283 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2284 /* Split up the value between registers for the read side */ 2285 if (!params.is_write) { 2286 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval)); 2287 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval)); 2288 } 2289 2290 return 1; 2291 } 2292 2293 unhandled_cp_access(vcpu, ¶ms); 2294 return 1; 2295 } 2296 2297 /** 2298 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access 2299 * @vcpu: The VCPU pointer 2300 * @run: The kvm_run struct 2301 */ 2302 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu, 2303 const struct sys_reg_desc *global, 2304 size_t nr_global) 2305 { 2306 struct sys_reg_params params; 2307 u32 esr = kvm_vcpu_get_esr(vcpu); 2308 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2309 2310 params.is_aarch32 = true; 2311 params.is_32bit = true; 2312 params.CRm = (esr >> 1) & 0xf; 2313 params.regval = vcpu_get_reg(vcpu, Rt); 2314 params.is_write = ((esr & 1) == 0); 2315 params.CRn = (esr >> 10) & 0xf; 2316 params.Op0 = 0; 2317 params.Op1 = (esr >> 14) & 0x7; 2318 params.Op2 = (esr >> 17) & 0x7; 2319 2320 if (!emulate_cp(vcpu, ¶ms, global, nr_global)) { 2321 if (!params.is_write) 2322 vcpu_set_reg(vcpu, Rt, params.regval); 2323 return 1; 2324 } 2325 2326 unhandled_cp_access(vcpu, ¶ms); 2327 return 1; 2328 } 2329 2330 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu) 2331 { 2332 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs)); 2333 } 2334 2335 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu) 2336 { 2337 return kvm_handle_cp_32(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs)); 2338 } 2339 2340 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu) 2341 { 2342 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs)); 2343 } 2344 2345 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu) 2346 { 2347 return kvm_handle_cp_32(vcpu, cp14_regs, ARRAY_SIZE(cp14_regs)); 2348 } 2349 2350 static bool is_imp_def_sys_reg(struct sys_reg_params *params) 2351 { 2352 // See ARM DDI 0487E.a, section D12.3.2 2353 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011; 2354 } 2355 2356 static int emulate_sys_reg(struct kvm_vcpu *vcpu, 2357 struct sys_reg_params *params) 2358 { 2359 const struct sys_reg_desc *r; 2360 2361 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2362 2363 if (likely(r)) { 2364 perform_access(vcpu, params, r); 2365 } else if (is_imp_def_sys_reg(params)) { 2366 kvm_inject_undefined(vcpu); 2367 } else { 2368 print_sys_reg_msg(params, 2369 "Unsupported guest sys_reg access at: %lx [%08lx]\n", 2370 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu)); 2371 kvm_inject_undefined(vcpu); 2372 } 2373 return 1; 2374 } 2375 2376 /** 2377 * kvm_reset_sys_regs - sets system registers to reset value 2378 * @vcpu: The VCPU pointer 2379 * 2380 * This function finds the right table above and sets the registers on the 2381 * virtual CPU struct to their architecturally defined reset values. 2382 */ 2383 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu) 2384 { 2385 unsigned long i; 2386 2387 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) 2388 if (sys_reg_descs[i].reset) 2389 sys_reg_descs[i].reset(vcpu, &sys_reg_descs[i]); 2390 } 2391 2392 /** 2393 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access 2394 * @vcpu: The VCPU pointer 2395 */ 2396 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu) 2397 { 2398 struct sys_reg_params params; 2399 unsigned long esr = kvm_vcpu_get_esr(vcpu); 2400 int Rt = kvm_vcpu_sys_get_rt(vcpu); 2401 int ret; 2402 2403 trace_kvm_handle_sys_reg(esr); 2404 2405 params.is_aarch32 = false; 2406 params.is_32bit = false; 2407 params.Op0 = (esr >> 20) & 3; 2408 params.Op1 = (esr >> 14) & 0x7; 2409 params.CRn = (esr >> 10) & 0xf; 2410 params.CRm = (esr >> 1) & 0xf; 2411 params.Op2 = (esr >> 17) & 0x7; 2412 params.regval = vcpu_get_reg(vcpu, Rt); 2413 params.is_write = !(esr & 1); 2414 2415 ret = emulate_sys_reg(vcpu, ¶ms); 2416 2417 if (!params.is_write) 2418 vcpu_set_reg(vcpu, Rt, params.regval); 2419 return ret; 2420 } 2421 2422 /****************************************************************************** 2423 * Userspace API 2424 *****************************************************************************/ 2425 2426 static bool index_to_params(u64 id, struct sys_reg_params *params) 2427 { 2428 switch (id & KVM_REG_SIZE_MASK) { 2429 case KVM_REG_SIZE_U64: 2430 /* Any unused index bits means it's not valid. */ 2431 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK 2432 | KVM_REG_ARM_COPROC_MASK 2433 | KVM_REG_ARM64_SYSREG_OP0_MASK 2434 | KVM_REG_ARM64_SYSREG_OP1_MASK 2435 | KVM_REG_ARM64_SYSREG_CRN_MASK 2436 | KVM_REG_ARM64_SYSREG_CRM_MASK 2437 | KVM_REG_ARM64_SYSREG_OP2_MASK)) 2438 return false; 2439 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK) 2440 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT); 2441 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK) 2442 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT); 2443 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK) 2444 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT); 2445 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK) 2446 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT); 2447 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK) 2448 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT); 2449 return true; 2450 default: 2451 return false; 2452 } 2453 } 2454 2455 const struct sys_reg_desc *find_reg_by_id(u64 id, 2456 struct sys_reg_params *params, 2457 const struct sys_reg_desc table[], 2458 unsigned int num) 2459 { 2460 if (!index_to_params(id, params)) 2461 return NULL; 2462 2463 return find_reg(params, table, num); 2464 } 2465 2466 /* Decode an index value, and find the sys_reg_desc entry. */ 2467 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu, 2468 u64 id) 2469 { 2470 const struct sys_reg_desc *r; 2471 struct sys_reg_params params; 2472 2473 /* We only do sys_reg for now. */ 2474 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG) 2475 return NULL; 2476 2477 if (!index_to_params(id, ¶ms)) 2478 return NULL; 2479 2480 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); 2481 2482 /* Not saved in the sys_reg array and not otherwise accessible? */ 2483 if (r && !(r->reg || r->get_user)) 2484 r = NULL; 2485 2486 return r; 2487 } 2488 2489 /* 2490 * These are the invariant sys_reg registers: we let the guest see the 2491 * host versions of these, so they're part of the guest state. 2492 * 2493 * A future CPU may provide a mechanism to present different values to 2494 * the guest, or a future kvm may trap them. 2495 */ 2496 2497 #define FUNCTION_INVARIANT(reg) \ 2498 static void get_##reg(struct kvm_vcpu *v, \ 2499 const struct sys_reg_desc *r) \ 2500 { \ 2501 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \ 2502 } 2503 2504 FUNCTION_INVARIANT(midr_el1) 2505 FUNCTION_INVARIANT(revidr_el1) 2506 FUNCTION_INVARIANT(clidr_el1) 2507 FUNCTION_INVARIANT(aidr_el1) 2508 2509 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r) 2510 { 2511 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0); 2512 } 2513 2514 /* ->val is filled in by kvm_sys_reg_table_init() */ 2515 static struct sys_reg_desc invariant_sys_regs[] = { 2516 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 }, 2517 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 }, 2518 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 }, 2519 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 }, 2520 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 }, 2521 }; 2522 2523 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id) 2524 { 2525 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0) 2526 return -EFAULT; 2527 return 0; 2528 } 2529 2530 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id) 2531 { 2532 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0) 2533 return -EFAULT; 2534 return 0; 2535 } 2536 2537 static int get_invariant_sys_reg(u64 id, void __user *uaddr) 2538 { 2539 struct sys_reg_params params; 2540 const struct sys_reg_desc *r; 2541 2542 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2543 ARRAY_SIZE(invariant_sys_regs)); 2544 if (!r) 2545 return -ENOENT; 2546 2547 return reg_to_user(uaddr, &r->val, id); 2548 } 2549 2550 static int set_invariant_sys_reg(u64 id, void __user *uaddr) 2551 { 2552 struct sys_reg_params params; 2553 const struct sys_reg_desc *r; 2554 int err; 2555 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */ 2556 2557 r = find_reg_by_id(id, ¶ms, invariant_sys_regs, 2558 ARRAY_SIZE(invariant_sys_regs)); 2559 if (!r) 2560 return -ENOENT; 2561 2562 err = reg_from_user(&val, uaddr, id); 2563 if (err) 2564 return err; 2565 2566 /* This is what we mean by invariant: you can't change it. */ 2567 if (r->val != val) 2568 return -EINVAL; 2569 2570 return 0; 2571 } 2572 2573 static bool is_valid_cache(u32 val) 2574 { 2575 u32 level, ctype; 2576 2577 if (val >= CSSELR_MAX) 2578 return false; 2579 2580 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */ 2581 level = (val >> 1); 2582 ctype = (cache_levels >> (level * 3)) & 7; 2583 2584 switch (ctype) { 2585 case 0: /* No cache */ 2586 return false; 2587 case 1: /* Instruction cache only */ 2588 return (val & 1); 2589 case 2: /* Data cache only */ 2590 case 4: /* Unified cache */ 2591 return !(val & 1); 2592 case 3: /* Separate instruction and data caches */ 2593 return true; 2594 default: /* Reserved: we can't know instruction or data. */ 2595 return false; 2596 } 2597 } 2598 2599 static int demux_c15_get(u64 id, void __user *uaddr) 2600 { 2601 u32 val; 2602 u32 __user *uval = uaddr; 2603 2604 /* Fail if we have unknown bits set. */ 2605 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2606 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2607 return -ENOENT; 2608 2609 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2610 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2611 if (KVM_REG_SIZE(id) != 4) 2612 return -ENOENT; 2613 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2614 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2615 if (!is_valid_cache(val)) 2616 return -ENOENT; 2617 2618 return put_user(get_ccsidr(val), uval); 2619 default: 2620 return -ENOENT; 2621 } 2622 } 2623 2624 static int demux_c15_set(u64 id, void __user *uaddr) 2625 { 2626 u32 val, newval; 2627 u32 __user *uval = uaddr; 2628 2629 /* Fail if we have unknown bits set. */ 2630 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK 2631 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1))) 2632 return -ENOENT; 2633 2634 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) { 2635 case KVM_REG_ARM_DEMUX_ID_CCSIDR: 2636 if (KVM_REG_SIZE(id) != 4) 2637 return -ENOENT; 2638 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK) 2639 >> KVM_REG_ARM_DEMUX_VAL_SHIFT; 2640 if (!is_valid_cache(val)) 2641 return -ENOENT; 2642 2643 if (get_user(newval, uval)) 2644 return -EFAULT; 2645 2646 /* This is also invariant: you can't change it. */ 2647 if (newval != get_ccsidr(val)) 2648 return -EINVAL; 2649 return 0; 2650 default: 2651 return -ENOENT; 2652 } 2653 } 2654 2655 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2656 { 2657 const struct sys_reg_desc *r; 2658 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2659 2660 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2661 return demux_c15_get(reg->id, uaddr); 2662 2663 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2664 return -ENOENT; 2665 2666 r = index_to_sys_reg_desc(vcpu, reg->id); 2667 if (!r) 2668 return get_invariant_sys_reg(reg->id, uaddr); 2669 2670 /* Check for regs disabled by runtime config */ 2671 if (sysreg_hidden_from_user(vcpu, r)) 2672 return -ENOENT; 2673 2674 if (r->get_user) 2675 return (r->get_user)(vcpu, r, reg, uaddr); 2676 2677 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id); 2678 } 2679 2680 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) 2681 { 2682 const struct sys_reg_desc *r; 2683 void __user *uaddr = (void __user *)(unsigned long)reg->addr; 2684 2685 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX) 2686 return demux_c15_set(reg->id, uaddr); 2687 2688 if (KVM_REG_SIZE(reg->id) != sizeof(__u64)) 2689 return -ENOENT; 2690 2691 r = index_to_sys_reg_desc(vcpu, reg->id); 2692 if (!r) 2693 return set_invariant_sys_reg(reg->id, uaddr); 2694 2695 /* Check for regs disabled by runtime config */ 2696 if (sysreg_hidden_from_user(vcpu, r)) 2697 return -ENOENT; 2698 2699 if (r->set_user) 2700 return (r->set_user)(vcpu, r, reg, uaddr); 2701 2702 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id); 2703 } 2704 2705 static unsigned int num_demux_regs(void) 2706 { 2707 unsigned int i, count = 0; 2708 2709 for (i = 0; i < CSSELR_MAX; i++) 2710 if (is_valid_cache(i)) 2711 count++; 2712 2713 return count; 2714 } 2715 2716 static int write_demux_regids(u64 __user *uindices) 2717 { 2718 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; 2719 unsigned int i; 2720 2721 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR; 2722 for (i = 0; i < CSSELR_MAX; i++) { 2723 if (!is_valid_cache(i)) 2724 continue; 2725 if (put_user(val | i, uindices)) 2726 return -EFAULT; 2727 uindices++; 2728 } 2729 return 0; 2730 } 2731 2732 static u64 sys_reg_to_index(const struct sys_reg_desc *reg) 2733 { 2734 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | 2735 KVM_REG_ARM64_SYSREG | 2736 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) | 2737 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) | 2738 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) | 2739 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) | 2740 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT)); 2741 } 2742 2743 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind) 2744 { 2745 if (!*uind) 2746 return true; 2747 2748 if (put_user(sys_reg_to_index(reg), *uind)) 2749 return false; 2750 2751 (*uind)++; 2752 return true; 2753 } 2754 2755 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, 2756 const struct sys_reg_desc *rd, 2757 u64 __user **uind, 2758 unsigned int *total) 2759 { 2760 /* 2761 * Ignore registers we trap but don't save, 2762 * and for which no custom user accessor is provided. 2763 */ 2764 if (!(rd->reg || rd->get_user)) 2765 return 0; 2766 2767 if (sysreg_hidden_from_user(vcpu, rd)) 2768 return 0; 2769 2770 if (!copy_reg_to_user(rd, uind)) 2771 return -EFAULT; 2772 2773 (*total)++; 2774 return 0; 2775 } 2776 2777 /* Assumed ordered tables, see kvm_sys_reg_table_init. */ 2778 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind) 2779 { 2780 const struct sys_reg_desc *i2, *end2; 2781 unsigned int total = 0; 2782 int err; 2783 2784 i2 = sys_reg_descs; 2785 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs); 2786 2787 while (i2 != end2) { 2788 err = walk_one_sys_reg(vcpu, i2++, &uind, &total); 2789 if (err) 2790 return err; 2791 } 2792 return total; 2793 } 2794 2795 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) 2796 { 2797 return ARRAY_SIZE(invariant_sys_regs) 2798 + num_demux_regs() 2799 + walk_sys_regs(vcpu, (u64 __user *)NULL); 2800 } 2801 2802 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices) 2803 { 2804 unsigned int i; 2805 int err; 2806 2807 /* Then give them all the invariant registers' indices. */ 2808 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) { 2809 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices)) 2810 return -EFAULT; 2811 uindices++; 2812 } 2813 2814 err = walk_sys_regs(vcpu, uindices); 2815 if (err < 0) 2816 return err; 2817 uindices += err; 2818 2819 return write_demux_regids(uindices); 2820 } 2821 2822 void kvm_sys_reg_table_init(void) 2823 { 2824 unsigned int i; 2825 struct sys_reg_desc clidr; 2826 2827 /* Make sure tables are unique and in order. */ 2828 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false)); 2829 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true)); 2830 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true)); 2831 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true)); 2832 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true)); 2833 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false)); 2834 2835 /* We abuse the reset function to overwrite the table itself. */ 2836 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) 2837 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]); 2838 2839 /* 2840 * CLIDR format is awkward, so clean it up. See ARM B4.1.20: 2841 * 2842 * If software reads the Cache Type fields from Ctype1 2843 * upwards, once it has seen a value of 0b000, no caches 2844 * exist at further-out levels of the hierarchy. So, for 2845 * example, if Ctype3 is the first Cache Type field with a 2846 * value of 0b000, the values of Ctype4 to Ctype7 must be 2847 * ignored. 2848 */ 2849 get_clidr_el1(NULL, &clidr); /* Ugly... */ 2850 cache_levels = clidr.val; 2851 for (i = 0; i < 7; i++) 2852 if (((cache_levels >> (i*3)) & 7) == 0) 2853 break; 2854 /* Clear all higher bits. */ 2855 cache_levels &= (1 << (i*3))-1; 2856 } 2857