1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine 4 * 5 * Copyright (C) 2012 Texas Instruments 6 * 7 */ 8 #include <linux/bitmap.h> 9 #include <linux/if_vlan.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/seq_file.h> 14 #include <linux/slab.h> 15 #include <linux/err.h> 16 #include <linux/io.h> 17 #include <linux/stat.h> 18 #include <linux/sysfs.h> 19 #include <linux/etherdevice.h> 20 21 #include "cpsw_ale.h" 22 23 #define BITMASK(bits) (BIT(bits) - 1) 24 25 #define ALE_VERSION_MAJOR(rev, mask) (((rev) >> 8) & (mask)) 26 #define ALE_VERSION_MINOR(rev) (rev & 0xff) 27 #define ALE_VERSION_1R3 0x0103 28 #define ALE_VERSION_1R4 0x0104 29 30 /* ALE Registers */ 31 #define ALE_IDVER 0x00 32 #define ALE_STATUS 0x04 33 #define ALE_CONTROL 0x08 34 #define ALE_PRESCALE 0x10 35 #define ALE_UNKNOWNVLAN 0x18 36 #define ALE_TABLE_CONTROL 0x20 37 #define ALE_TABLE 0x34 38 #define ALE_PORTCTL 0x40 39 40 /* ALE NetCP NU switch specific Registers */ 41 #define ALE_UNKNOWNVLAN_MEMBER 0x90 42 #define ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD 0x94 43 #define ALE_UNKNOWNVLAN_REG_MCAST_FLOOD 0x98 44 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C 45 #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg))) 46 47 #define AM65_CPSW_ALE_THREAD_DEF_REG 0x134 48 49 #define ALE_TABLE_WRITE BIT(31) 50 51 #define ALE_TYPE_FREE 0 52 #define ALE_TYPE_ADDR 1 53 #define ALE_TYPE_VLAN 2 54 #define ALE_TYPE_VLAN_ADDR 3 55 56 #define ALE_UCAST_PERSISTANT 0 57 #define ALE_UCAST_UNTOUCHED 1 58 #define ALE_UCAST_OUI 2 59 #define ALE_UCAST_TOUCHED 3 60 61 #define ALE_TABLE_SIZE_MULTIPLIER 1024 62 #define ALE_STATUS_SIZE_MASK 0x1f 63 #define ALE_TABLE_SIZE_DEFAULT 64 64 65 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) 66 { 67 int idx; 68 69 idx = start / 32; 70 start -= idx * 32; 71 idx = 2 - idx; /* flip */ 72 return (ale_entry[idx] >> start) & BITMASK(bits); 73 } 74 75 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, 76 u32 value) 77 { 78 int idx; 79 80 value &= BITMASK(bits); 81 idx = start / 32; 82 start -= idx * 32; 83 idx = 2 - idx; /* flip */ 84 ale_entry[idx] &= ~(BITMASK(bits) << start); 85 ale_entry[idx] |= (value << start); 86 } 87 88 #define DEFINE_ALE_FIELD(name, start, bits) \ 89 static inline int cpsw_ale_get_##name(u32 *ale_entry) \ 90 { \ 91 return cpsw_ale_get_field(ale_entry, start, bits); \ 92 } \ 93 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ 94 { \ 95 cpsw_ale_set_field(ale_entry, start, bits, value); \ 96 } 97 98 #define DEFINE_ALE_FIELD1(name, start) \ 99 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits) \ 100 { \ 101 return cpsw_ale_get_field(ale_entry, start, bits); \ 102 } \ 103 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value, \ 104 u32 bits) \ 105 { \ 106 cpsw_ale_set_field(ale_entry, start, bits, value); \ 107 } 108 109 DEFINE_ALE_FIELD(entry_type, 60, 2) 110 DEFINE_ALE_FIELD(vlan_id, 48, 12) 111 DEFINE_ALE_FIELD(mcast_state, 62, 2) 112 DEFINE_ALE_FIELD1(port_mask, 66) 113 DEFINE_ALE_FIELD(super, 65, 1) 114 DEFINE_ALE_FIELD(ucast_type, 62, 2) 115 DEFINE_ALE_FIELD1(port_num, 66) 116 DEFINE_ALE_FIELD(blocked, 65, 1) 117 DEFINE_ALE_FIELD(secure, 64, 1) 118 DEFINE_ALE_FIELD1(vlan_untag_force, 24) 119 DEFINE_ALE_FIELD1(vlan_reg_mcast, 16) 120 DEFINE_ALE_FIELD1(vlan_unreg_mcast, 8) 121 DEFINE_ALE_FIELD1(vlan_member_list, 0) 122 DEFINE_ALE_FIELD(mcast, 40, 1) 123 /* ALE NetCP nu switch specific */ 124 DEFINE_ALE_FIELD(vlan_unreg_mcast_idx, 20, 3) 125 DEFINE_ALE_FIELD(vlan_reg_mcast_idx, 44, 3) 126 127 #define NU_VLAN_UNREG_MCAST_IDX 1 128 129 /* The MAC address field in the ALE entry cannot be macroized as above */ 130 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) 131 { 132 int i; 133 134 for (i = 0; i < 6; i++) 135 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); 136 } 137 138 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr) 139 { 140 int i; 141 142 for (i = 0; i < 6; i++) 143 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); 144 } 145 146 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry) 147 { 148 int i; 149 150 WARN_ON(idx > ale->params.ale_entries); 151 152 writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL); 153 154 for (i = 0; i < ALE_ENTRY_WORDS; i++) 155 ale_entry[i] = readl_relaxed(ale->params.ale_regs + 156 ALE_TABLE + 4 * i); 157 158 return idx; 159 } 160 161 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry) 162 { 163 int i; 164 165 WARN_ON(idx > ale->params.ale_entries); 166 167 for (i = 0; i < ALE_ENTRY_WORDS; i++) 168 writel_relaxed(ale_entry[i], ale->params.ale_regs + 169 ALE_TABLE + 4 * i); 170 171 writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs + 172 ALE_TABLE_CONTROL); 173 174 return idx; 175 } 176 177 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid) 178 { 179 u32 ale_entry[ALE_ENTRY_WORDS]; 180 int type, idx; 181 182 for (idx = 0; idx < ale->params.ale_entries; idx++) { 183 u8 entry_addr[6]; 184 185 cpsw_ale_read(ale, idx, ale_entry); 186 type = cpsw_ale_get_entry_type(ale_entry); 187 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 188 continue; 189 if (cpsw_ale_get_vlan_id(ale_entry) != vid) 190 continue; 191 cpsw_ale_get_addr(ale_entry, entry_addr); 192 if (ether_addr_equal(entry_addr, addr)) 193 return idx; 194 } 195 return -ENOENT; 196 } 197 198 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid) 199 { 200 u32 ale_entry[ALE_ENTRY_WORDS]; 201 int type, idx; 202 203 for (idx = 0; idx < ale->params.ale_entries; idx++) { 204 cpsw_ale_read(ale, idx, ale_entry); 205 type = cpsw_ale_get_entry_type(ale_entry); 206 if (type != ALE_TYPE_VLAN) 207 continue; 208 if (cpsw_ale_get_vlan_id(ale_entry) == vid) 209 return idx; 210 } 211 return -ENOENT; 212 } 213 214 static int cpsw_ale_match_free(struct cpsw_ale *ale) 215 { 216 u32 ale_entry[ALE_ENTRY_WORDS]; 217 int type, idx; 218 219 for (idx = 0; idx < ale->params.ale_entries; idx++) { 220 cpsw_ale_read(ale, idx, ale_entry); 221 type = cpsw_ale_get_entry_type(ale_entry); 222 if (type == ALE_TYPE_FREE) 223 return idx; 224 } 225 return -ENOENT; 226 } 227 228 static int cpsw_ale_find_ageable(struct cpsw_ale *ale) 229 { 230 u32 ale_entry[ALE_ENTRY_WORDS]; 231 int type, idx; 232 233 for (idx = 0; idx < ale->params.ale_entries; idx++) { 234 cpsw_ale_read(ale, idx, ale_entry); 235 type = cpsw_ale_get_entry_type(ale_entry); 236 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 237 continue; 238 if (cpsw_ale_get_mcast(ale_entry)) 239 continue; 240 type = cpsw_ale_get_ucast_type(ale_entry); 241 if (type != ALE_UCAST_PERSISTANT && 242 type != ALE_UCAST_OUI) 243 return idx; 244 } 245 return -ENOENT; 246 } 247 248 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry, 249 int port_mask) 250 { 251 int mask; 252 253 mask = cpsw_ale_get_port_mask(ale_entry, 254 ale->port_mask_bits); 255 if ((mask & port_mask) == 0) 256 return; /* ports dont intersect, not interested */ 257 mask &= ~port_mask; 258 259 /* free if only remaining port is host port */ 260 if (mask) 261 cpsw_ale_set_port_mask(ale_entry, mask, 262 ale->port_mask_bits); 263 else 264 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 265 } 266 267 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid) 268 { 269 u32 ale_entry[ALE_ENTRY_WORDS]; 270 int ret, idx; 271 272 for (idx = 0; idx < ale->params.ale_entries; idx++) { 273 cpsw_ale_read(ale, idx, ale_entry); 274 ret = cpsw_ale_get_entry_type(ale_entry); 275 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR) 276 continue; 277 278 /* if vid passed is -1 then remove all multicast entry from 279 * the table irrespective of vlan id, if a valid vlan id is 280 * passed then remove only multicast added to that vlan id. 281 * if vlan id doesn't match then move on to next entry. 282 */ 283 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid) 284 continue; 285 286 if (cpsw_ale_get_mcast(ale_entry)) { 287 u8 addr[6]; 288 289 if (cpsw_ale_get_super(ale_entry)) 290 continue; 291 292 cpsw_ale_get_addr(ale_entry, addr); 293 if (!is_broadcast_ether_addr(addr)) 294 cpsw_ale_flush_mcast(ale, ale_entry, port_mask); 295 } 296 297 cpsw_ale_write(ale, idx, ale_entry); 298 } 299 return 0; 300 } 301 302 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry, 303 int flags, u16 vid) 304 { 305 if (flags & ALE_VLAN) { 306 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR); 307 cpsw_ale_set_vlan_id(ale_entry, vid); 308 } else { 309 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 310 } 311 } 312 313 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port, 314 int flags, u16 vid) 315 { 316 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 317 int idx; 318 319 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); 320 321 cpsw_ale_set_addr(ale_entry, addr); 322 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); 323 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); 324 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 325 cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits); 326 327 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 328 if (idx < 0) 329 idx = cpsw_ale_match_free(ale); 330 if (idx < 0) 331 idx = cpsw_ale_find_ageable(ale); 332 if (idx < 0) 333 return -ENOMEM; 334 335 cpsw_ale_write(ale, idx, ale_entry); 336 return 0; 337 } 338 339 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, 340 int flags, u16 vid) 341 { 342 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 343 int idx; 344 345 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 346 if (idx < 0) 347 return -ENOENT; 348 349 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 350 cpsw_ale_write(ale, idx, ale_entry); 351 return 0; 352 } 353 354 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 355 int flags, u16 vid, int mcast_state) 356 { 357 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 358 int idx, mask; 359 360 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 361 if (idx >= 0) 362 cpsw_ale_read(ale, idx, ale_entry); 363 364 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); 365 366 cpsw_ale_set_addr(ale_entry, addr); 367 cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0); 368 cpsw_ale_set_mcast_state(ale_entry, mcast_state); 369 370 mask = cpsw_ale_get_port_mask(ale_entry, 371 ale->port_mask_bits); 372 port_mask |= mask; 373 cpsw_ale_set_port_mask(ale_entry, port_mask, 374 ale->port_mask_bits); 375 376 if (idx < 0) 377 idx = cpsw_ale_match_free(ale); 378 if (idx < 0) 379 idx = cpsw_ale_find_ageable(ale); 380 if (idx < 0) 381 return -ENOMEM; 382 383 cpsw_ale_write(ale, idx, ale_entry); 384 return 0; 385 } 386 387 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 388 int flags, u16 vid) 389 { 390 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 391 int mcast_members = 0; 392 int idx; 393 394 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0); 395 if (idx < 0) 396 return -ENOENT; 397 398 cpsw_ale_read(ale, idx, ale_entry); 399 400 if (port_mask) { 401 mcast_members = cpsw_ale_get_port_mask(ale_entry, 402 ale->port_mask_bits); 403 mcast_members &= ~port_mask; 404 } 405 406 if (mcast_members) 407 cpsw_ale_set_port_mask(ale_entry, mcast_members, 408 ale->port_mask_bits); 409 else 410 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 411 412 cpsw_ale_write(ale, idx, ale_entry); 413 return 0; 414 } 415 416 /* ALE NetCP NU switch specific vlan functions */ 417 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry, 418 int reg_mcast, int unreg_mcast) 419 { 420 int idx; 421 422 /* Set VLAN registered multicast flood mask */ 423 idx = cpsw_ale_get_vlan_reg_mcast_idx(ale_entry); 424 writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 425 426 /* Set VLAN unregistered multicast flood mask */ 427 idx = cpsw_ale_get_vlan_unreg_mcast_idx(ale_entry); 428 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx)); 429 } 430 431 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry, 432 u16 vid, int untag_mask) 433 { 434 cpsw_ale_set_vlan_untag_force(ale_entry, 435 untag_mask, ale->vlan_field_bits); 436 if (untag_mask & ALE_PORT_HOST) 437 bitmap_set(ale->p0_untag_vid_mask, vid, 1); 438 else 439 bitmap_clear(ale->p0_untag_vid_mask, vid, 1); 440 } 441 442 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag, 443 int reg_mcast, int unreg_mcast) 444 { 445 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 446 int idx; 447 448 idx = cpsw_ale_match_vlan(ale, vid); 449 if (idx >= 0) 450 cpsw_ale_read(ale, idx, ale_entry); 451 452 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN); 453 cpsw_ale_set_vlan_id(ale_entry, vid); 454 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); 455 456 if (!ale->params.nu_switch_ale) { 457 cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast, 458 ale->vlan_field_bits); 459 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast, 460 ale->vlan_field_bits); 461 } else { 462 cpsw_ale_set_vlan_unreg_mcast_idx(ale_entry, 463 NU_VLAN_UNREG_MCAST_IDX); 464 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast); 465 } 466 cpsw_ale_set_vlan_member_list(ale_entry, port_mask, 467 ale->vlan_field_bits); 468 469 if (idx < 0) 470 idx = cpsw_ale_match_free(ale); 471 if (idx < 0) 472 idx = cpsw_ale_find_ageable(ale); 473 if (idx < 0) 474 return -ENOMEM; 475 476 cpsw_ale_write(ale, idx, ale_entry); 477 return 0; 478 } 479 480 static void cpsw_ale_del_vlan_modify(struct cpsw_ale *ale, u32 *ale_entry, 481 u16 vid, int port_mask) 482 { 483 int reg_mcast, unreg_mcast; 484 int members, untag; 485 486 members = cpsw_ale_get_vlan_member_list(ale_entry, 487 ale->vlan_field_bits); 488 members &= ~port_mask; 489 if (!members) { 490 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 491 return; 492 } 493 494 untag = cpsw_ale_get_vlan_untag_force(ale_entry, 495 ale->vlan_field_bits); 496 reg_mcast = cpsw_ale_get_vlan_reg_mcast(ale_entry, 497 ale->vlan_field_bits); 498 unreg_mcast = cpsw_ale_get_vlan_unreg_mcast(ale_entry, 499 ale->vlan_field_bits); 500 untag &= members; 501 reg_mcast &= members; 502 unreg_mcast &= members; 503 504 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag); 505 506 if (!ale->params.nu_switch_ale) { 507 cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast, 508 ale->vlan_field_bits); 509 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast, 510 ale->vlan_field_bits); 511 } else { 512 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, 513 unreg_mcast); 514 } 515 cpsw_ale_set_vlan_member_list(ale_entry, members, 516 ale->vlan_field_bits); 517 } 518 519 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) 520 { 521 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 522 int idx; 523 524 idx = cpsw_ale_match_vlan(ale, vid); 525 if (idx < 0) 526 return -ENOENT; 527 528 cpsw_ale_read(ale, idx, ale_entry); 529 530 if (port_mask) { 531 cpsw_ale_del_vlan_modify(ale, ale_entry, vid, port_mask); 532 } else { 533 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0); 534 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE); 535 } 536 537 cpsw_ale_write(ale, idx, ale_entry); 538 539 return 0; 540 } 541 542 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask, 543 int untag_mask, int reg_mask, int unreg_mask) 544 { 545 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 546 int reg_mcast_members, unreg_mcast_members; 547 int vlan_members, untag_members; 548 int idx, ret = 0; 549 550 idx = cpsw_ale_match_vlan(ale, vid); 551 if (idx >= 0) 552 cpsw_ale_read(ale, idx, ale_entry); 553 554 vlan_members = cpsw_ale_get_vlan_member_list(ale_entry, 555 ale->vlan_field_bits); 556 reg_mcast_members = cpsw_ale_get_vlan_reg_mcast(ale_entry, 557 ale->vlan_field_bits); 558 unreg_mcast_members = 559 cpsw_ale_get_vlan_unreg_mcast(ale_entry, 560 ale->vlan_field_bits); 561 untag_members = cpsw_ale_get_vlan_untag_force(ale_entry, 562 ale->vlan_field_bits); 563 564 vlan_members |= port_mask; 565 untag_members = (untag_members & ~port_mask) | untag_mask; 566 reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask; 567 unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask; 568 569 ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members, 570 reg_mcast_members, unreg_mcast_members); 571 if (ret) { 572 dev_err(ale->params.dev, "Unable to add vlan\n"); 573 return ret; 574 } 575 dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members, 576 untag_mask); 577 578 return ret; 579 } 580 581 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask, 582 bool add) 583 { 584 u32 ale_entry[ALE_ENTRY_WORDS]; 585 int unreg_members = 0; 586 int type, idx; 587 588 for (idx = 0; idx < ale->params.ale_entries; idx++) { 589 cpsw_ale_read(ale, idx, ale_entry); 590 type = cpsw_ale_get_entry_type(ale_entry); 591 if (type != ALE_TYPE_VLAN) 592 continue; 593 594 unreg_members = 595 cpsw_ale_get_vlan_unreg_mcast(ale_entry, 596 ale->vlan_field_bits); 597 if (add) 598 unreg_members |= unreg_mcast_mask; 599 else 600 unreg_members &= ~unreg_mcast_mask; 601 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_members, 602 ale->vlan_field_bits); 603 cpsw_ale_write(ale, idx, ale_entry); 604 } 605 } 606 607 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port) 608 { 609 u32 ale_entry[ALE_ENTRY_WORDS]; 610 int unreg_mcast = 0; 611 int type, idx; 612 613 for (idx = 0; idx < ale->params.ale_entries; idx++) { 614 int vlan_members; 615 616 cpsw_ale_read(ale, idx, ale_entry); 617 type = cpsw_ale_get_entry_type(ale_entry); 618 if (type != ALE_TYPE_VLAN) 619 continue; 620 vlan_members = 621 cpsw_ale_get_vlan_member_list(ale_entry, 622 ale->vlan_field_bits); 623 624 if (port != -1 && !(vlan_members & BIT(port))) 625 continue; 626 627 unreg_mcast = 628 cpsw_ale_get_vlan_unreg_mcast(ale_entry, 629 ale->vlan_field_bits); 630 if (allmulti) 631 unreg_mcast |= ALE_PORT_HOST; 632 else 633 unreg_mcast &= ~ALE_PORT_HOST; 634 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast, 635 ale->vlan_field_bits); 636 cpsw_ale_write(ale, idx, ale_entry); 637 } 638 } 639 640 struct ale_control_info { 641 const char *name; 642 int offset, port_offset; 643 int shift, port_shift; 644 int bits; 645 }; 646 647 static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = { 648 [ALE_ENABLE] = { 649 .name = "enable", 650 .offset = ALE_CONTROL, 651 .port_offset = 0, 652 .shift = 31, 653 .port_shift = 0, 654 .bits = 1, 655 }, 656 [ALE_CLEAR] = { 657 .name = "clear", 658 .offset = ALE_CONTROL, 659 .port_offset = 0, 660 .shift = 30, 661 .port_shift = 0, 662 .bits = 1, 663 }, 664 [ALE_AGEOUT] = { 665 .name = "ageout", 666 .offset = ALE_CONTROL, 667 .port_offset = 0, 668 .shift = 29, 669 .port_shift = 0, 670 .bits = 1, 671 }, 672 [ALE_P0_UNI_FLOOD] = { 673 .name = "port0_unicast_flood", 674 .offset = ALE_CONTROL, 675 .port_offset = 0, 676 .shift = 8, 677 .port_shift = 0, 678 .bits = 1, 679 }, 680 [ALE_VLAN_NOLEARN] = { 681 .name = "vlan_nolearn", 682 .offset = ALE_CONTROL, 683 .port_offset = 0, 684 .shift = 7, 685 .port_shift = 0, 686 .bits = 1, 687 }, 688 [ALE_NO_PORT_VLAN] = { 689 .name = "no_port_vlan", 690 .offset = ALE_CONTROL, 691 .port_offset = 0, 692 .shift = 6, 693 .port_shift = 0, 694 .bits = 1, 695 }, 696 [ALE_OUI_DENY] = { 697 .name = "oui_deny", 698 .offset = ALE_CONTROL, 699 .port_offset = 0, 700 .shift = 5, 701 .port_shift = 0, 702 .bits = 1, 703 }, 704 [ALE_BYPASS] = { 705 .name = "bypass", 706 .offset = ALE_CONTROL, 707 .port_offset = 0, 708 .shift = 4, 709 .port_shift = 0, 710 .bits = 1, 711 }, 712 [ALE_RATE_LIMIT_TX] = { 713 .name = "rate_limit_tx", 714 .offset = ALE_CONTROL, 715 .port_offset = 0, 716 .shift = 3, 717 .port_shift = 0, 718 .bits = 1, 719 }, 720 [ALE_VLAN_AWARE] = { 721 .name = "vlan_aware", 722 .offset = ALE_CONTROL, 723 .port_offset = 0, 724 .shift = 2, 725 .port_shift = 0, 726 .bits = 1, 727 }, 728 [ALE_AUTH_ENABLE] = { 729 .name = "auth_enable", 730 .offset = ALE_CONTROL, 731 .port_offset = 0, 732 .shift = 1, 733 .port_shift = 0, 734 .bits = 1, 735 }, 736 [ALE_RATE_LIMIT] = { 737 .name = "rate_limit", 738 .offset = ALE_CONTROL, 739 .port_offset = 0, 740 .shift = 0, 741 .port_shift = 0, 742 .bits = 1, 743 }, 744 [ALE_PORT_STATE] = { 745 .name = "port_state", 746 .offset = ALE_PORTCTL, 747 .port_offset = 4, 748 .shift = 0, 749 .port_shift = 0, 750 .bits = 2, 751 }, 752 [ALE_PORT_DROP_UNTAGGED] = { 753 .name = "drop_untagged", 754 .offset = ALE_PORTCTL, 755 .port_offset = 4, 756 .shift = 2, 757 .port_shift = 0, 758 .bits = 1, 759 }, 760 [ALE_PORT_DROP_UNKNOWN_VLAN] = { 761 .name = "drop_unknown", 762 .offset = ALE_PORTCTL, 763 .port_offset = 4, 764 .shift = 3, 765 .port_shift = 0, 766 .bits = 1, 767 }, 768 [ALE_PORT_NOLEARN] = { 769 .name = "nolearn", 770 .offset = ALE_PORTCTL, 771 .port_offset = 4, 772 .shift = 4, 773 .port_shift = 0, 774 .bits = 1, 775 }, 776 [ALE_PORT_NO_SA_UPDATE] = { 777 .name = "no_source_update", 778 .offset = ALE_PORTCTL, 779 .port_offset = 4, 780 .shift = 5, 781 .port_shift = 0, 782 .bits = 1, 783 }, 784 [ALE_PORT_MACONLY] = { 785 .name = "mac_only_port_mode", 786 .offset = ALE_PORTCTL, 787 .port_offset = 4, 788 .shift = 11, 789 .port_shift = 0, 790 .bits = 1, 791 }, 792 [ALE_PORT_MACONLY_CAF] = { 793 .name = "mac_only_port_caf", 794 .offset = ALE_PORTCTL, 795 .port_offset = 4, 796 .shift = 13, 797 .port_shift = 0, 798 .bits = 1, 799 }, 800 [ALE_PORT_MCAST_LIMIT] = { 801 .name = "mcast_limit", 802 .offset = ALE_PORTCTL, 803 .port_offset = 4, 804 .shift = 16, 805 .port_shift = 0, 806 .bits = 8, 807 }, 808 [ALE_PORT_BCAST_LIMIT] = { 809 .name = "bcast_limit", 810 .offset = ALE_PORTCTL, 811 .port_offset = 4, 812 .shift = 24, 813 .port_shift = 0, 814 .bits = 8, 815 }, 816 [ALE_PORT_UNKNOWN_VLAN_MEMBER] = { 817 .name = "unknown_vlan_member", 818 .offset = ALE_UNKNOWNVLAN, 819 .port_offset = 0, 820 .shift = 0, 821 .port_shift = 0, 822 .bits = 6, 823 }, 824 [ALE_PORT_UNKNOWN_MCAST_FLOOD] = { 825 .name = "unknown_mcast_flood", 826 .offset = ALE_UNKNOWNVLAN, 827 .port_offset = 0, 828 .shift = 8, 829 .port_shift = 0, 830 .bits = 6, 831 }, 832 [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = { 833 .name = "unknown_reg_flood", 834 .offset = ALE_UNKNOWNVLAN, 835 .port_offset = 0, 836 .shift = 16, 837 .port_shift = 0, 838 .bits = 6, 839 }, 840 [ALE_PORT_UNTAGGED_EGRESS] = { 841 .name = "untagged_egress", 842 .offset = ALE_UNKNOWNVLAN, 843 .port_offset = 0, 844 .shift = 24, 845 .port_shift = 0, 846 .bits = 6, 847 }, 848 [ALE_DEFAULT_THREAD_ID] = { 849 .name = "default_thread_id", 850 .offset = AM65_CPSW_ALE_THREAD_DEF_REG, 851 .port_offset = 0, 852 .shift = 0, 853 .port_shift = 0, 854 .bits = 6, 855 }, 856 [ALE_DEFAULT_THREAD_ENABLE] = { 857 .name = "default_thread_id_enable", 858 .offset = AM65_CPSW_ALE_THREAD_DEF_REG, 859 .port_offset = 0, 860 .shift = 15, 861 .port_shift = 0, 862 .bits = 1, 863 }, 864 }; 865 866 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control, 867 int value) 868 { 869 const struct ale_control_info *info; 870 int offset, shift; 871 u32 tmp, mask; 872 873 if (control < 0 || control >= ARRAY_SIZE(ale_controls)) 874 return -EINVAL; 875 876 info = &ale_controls[control]; 877 if (info->port_offset == 0 && info->port_shift == 0) 878 port = 0; /* global, port is a dont care */ 879 880 if (port < 0 || port >= ale->params.ale_ports) 881 return -EINVAL; 882 883 mask = BITMASK(info->bits); 884 if (value & ~mask) 885 return -EINVAL; 886 887 offset = info->offset + (port * info->port_offset); 888 shift = info->shift + (port * info->port_shift); 889 890 tmp = readl_relaxed(ale->params.ale_regs + offset); 891 tmp = (tmp & ~(mask << shift)) | (value << shift); 892 writel_relaxed(tmp, ale->params.ale_regs + offset); 893 894 return 0; 895 } 896 897 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control) 898 { 899 const struct ale_control_info *info; 900 int offset, shift; 901 u32 tmp; 902 903 if (control < 0 || control >= ARRAY_SIZE(ale_controls)) 904 return -EINVAL; 905 906 info = &ale_controls[control]; 907 if (info->port_offset == 0 && info->port_shift == 0) 908 port = 0; /* global, port is a dont care */ 909 910 if (port < 0 || port >= ale->params.ale_ports) 911 return -EINVAL; 912 913 offset = info->offset + (port * info->port_offset); 914 shift = info->shift + (port * info->port_shift); 915 916 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift; 917 return tmp & BITMASK(info->bits); 918 } 919 920 static void cpsw_ale_timer(struct timer_list *t) 921 { 922 struct cpsw_ale *ale = from_timer(ale, t, timer); 923 924 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1); 925 926 if (ale->ageout) { 927 ale->timer.expires = jiffies + ale->ageout; 928 add_timer(&ale->timer); 929 } 930 } 931 932 void cpsw_ale_start(struct cpsw_ale *ale) 933 { 934 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1); 935 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 936 937 timer_setup(&ale->timer, cpsw_ale_timer, 0); 938 if (ale->ageout) { 939 ale->timer.expires = jiffies + ale->ageout; 940 add_timer(&ale->timer); 941 } 942 } 943 944 void cpsw_ale_stop(struct cpsw_ale *ale) 945 { 946 del_timer_sync(&ale->timer); 947 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 948 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); 949 } 950 951 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) 952 { 953 struct cpsw_ale *ale; 954 u32 rev, ale_entries; 955 956 ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL); 957 if (!ale) 958 return NULL; 959 960 ale->p0_untag_vid_mask = 961 devm_kmalloc_array(params->dev, BITS_TO_LONGS(VLAN_N_VID), 962 sizeof(unsigned long), 963 GFP_KERNEL); 964 if (!ale->p0_untag_vid_mask) 965 return ERR_PTR(-ENOMEM); 966 967 ale->params = *params; 968 ale->ageout = ale->params.ale_ageout * HZ; 969 970 rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER); 971 if (!ale->params.major_ver_mask) 972 ale->params.major_ver_mask = 0xff; 973 ale->version = 974 (ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask) << 8) | 975 ALE_VERSION_MINOR(rev); 976 dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n", 977 ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask), 978 ALE_VERSION_MINOR(rev)); 979 980 if (!ale->params.ale_entries) { 981 ale_entries = 982 readl_relaxed(ale->params.ale_regs + ALE_STATUS) & 983 ALE_STATUS_SIZE_MASK; 984 /* ALE available on newer NetCP switches has introduced 985 * a register, ALE_STATUS, to indicate the size of ALE 986 * table which shows the size as a multiple of 1024 entries. 987 * For these, params.ale_entries will be set to zero. So 988 * read the register and update the value of ale_entries. 989 * ALE table on NetCP lite, is much smaller and is indicated 990 * by a value of zero in ALE_STATUS. So use a default value 991 * of ALE_TABLE_SIZE_DEFAULT for this. Caller is expected 992 * to set the value of ale_entries for all other versions 993 * of ALE. 994 */ 995 if (!ale_entries) 996 ale_entries = ALE_TABLE_SIZE_DEFAULT; 997 else 998 ale_entries *= ALE_TABLE_SIZE_MULTIPLIER; 999 ale->params.ale_entries = ale_entries; 1000 } 1001 dev_info(ale->params.dev, 1002 "ALE Table size %ld\n", ale->params.ale_entries); 1003 1004 /* set default bits for existing h/w */ 1005 ale->port_mask_bits = ale->params.ale_ports; 1006 ale->port_num_bits = order_base_2(ale->params.ale_ports); 1007 ale->vlan_field_bits = ale->params.ale_ports; 1008 1009 /* Set defaults override for ALE on NetCP NU switch and for version 1010 * 1R3 1011 */ 1012 if (ale->params.nu_switch_ale) { 1013 /* Separate registers for unknown vlan configuration. 1014 * Also there are N bits, where N is number of ale 1015 * ports and shift value should be 0 1016 */ 1017 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].bits = 1018 ale->params.ale_ports; 1019 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].offset = 1020 ALE_UNKNOWNVLAN_MEMBER; 1021 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].bits = 1022 ale->params.ale_ports; 1023 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].shift = 0; 1024 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].offset = 1025 ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD; 1026 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].bits = 1027 ale->params.ale_ports; 1028 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].shift = 0; 1029 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].offset = 1030 ALE_UNKNOWNVLAN_REG_MCAST_FLOOD; 1031 ale_controls[ALE_PORT_UNTAGGED_EGRESS].bits = 1032 ale->params.ale_ports; 1033 ale_controls[ALE_PORT_UNTAGGED_EGRESS].shift = 0; 1034 ale_controls[ALE_PORT_UNTAGGED_EGRESS].offset = 1035 ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS; 1036 } 1037 1038 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1); 1039 return ale; 1040 } 1041 1042 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data) 1043 { 1044 int i; 1045 1046 for (i = 0; i < ale->params.ale_entries; i++) { 1047 cpsw_ale_read(ale, i, data); 1048 data += ALE_ENTRY_WORDS; 1049 } 1050 } 1051