1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved. */ 3 4 #ifndef __QCOM_CLK_ALPHA_PLL_H__ 5 #define __QCOM_CLK_ALPHA_PLL_H__ 6 7 #include <linux/clk-provider.h> 8 #include "clk-regmap.h" 9 10 /* Alpha PLL types */ 11 enum { 12 CLK_ALPHA_PLL_TYPE_DEFAULT, 13 CLK_ALPHA_PLL_TYPE_HUAYRA, 14 CLK_ALPHA_PLL_TYPE_BRAMMO, 15 CLK_ALPHA_PLL_TYPE_FABIA, 16 CLK_ALPHA_PLL_TYPE_TRION, 17 CLK_ALPHA_PLL_TYPE_MAX, 18 }; 19 20 enum { 21 PLL_OFF_L_VAL, 22 PLL_OFF_CAL_L_VAL, 23 PLL_OFF_ALPHA_VAL, 24 PLL_OFF_ALPHA_VAL_U, 25 PLL_OFF_USER_CTL, 26 PLL_OFF_USER_CTL_U, 27 PLL_OFF_USER_CTL_U1, 28 PLL_OFF_CONFIG_CTL, 29 PLL_OFF_CONFIG_CTL_U, 30 PLL_OFF_CONFIG_CTL_U1, 31 PLL_OFF_TEST_CTL, 32 PLL_OFF_TEST_CTL_U, 33 PLL_OFF_STATUS, 34 PLL_OFF_OPMODE, 35 PLL_OFF_FRAC, 36 PLL_OFF_CAL_VAL, 37 PLL_OFF_MAX_REGS 38 }; 39 40 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS]; 41 42 struct pll_vco { 43 unsigned long min_freq; 44 unsigned long max_freq; 45 u32 val; 46 }; 47 48 /** 49 * struct clk_alpha_pll - phase locked loop (PLL) 50 * @offset: base address of registers 51 * @vco_table: array of VCO settings 52 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 53 * @clkr: regmap clock handle 54 */ 55 struct clk_alpha_pll { 56 u32 offset; 57 const u8 *regs; 58 59 const struct pll_vco *vco_table; 60 size_t num_vco; 61 #define SUPPORTS_OFFLINE_REQ BIT(0) 62 #define SUPPORTS_FSM_MODE BIT(2) 63 #define SUPPORTS_DYNAMIC_UPDATE BIT(3) 64 u8 flags; 65 66 struct clk_regmap clkr; 67 }; 68 69 /** 70 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 71 * @offset: base address of registers 72 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 73 * @width: width of post-divider 74 * @post_div_shift: shift to differentiate between odd & even post-divider 75 * @post_div_table: table with PLL odd and even post-divider settings 76 * @num_post_div: Number of PLL post-divider settings 77 * 78 * @clkr: regmap clock handle 79 */ 80 struct clk_alpha_pll_postdiv { 81 u32 offset; 82 u8 width; 83 const u8 *regs; 84 85 struct clk_regmap clkr; 86 int post_div_shift; 87 const struct clk_div_table *post_div_table; 88 size_t num_post_div; 89 }; 90 91 struct alpha_pll_config { 92 u32 l; 93 u32 alpha; 94 u32 alpha_hi; 95 u32 config_ctl_val; 96 u32 config_ctl_hi_val; 97 u32 user_ctl_val; 98 u32 user_ctl_hi_val; 99 u32 test_ctl_val; 100 u32 test_ctl_hi_val; 101 u32 main_output_mask; 102 u32 aux_output_mask; 103 u32 aux2_output_mask; 104 u32 early_output_mask; 105 u32 alpha_en_mask; 106 u32 alpha_mode_mask; 107 u32 pre_div_val; 108 u32 pre_div_mask; 109 u32 post_div_val; 110 u32 post_div_mask; 111 u32 vco_val; 112 u32 vco_mask; 113 }; 114 115 extern const struct clk_ops clk_alpha_pll_ops; 116 extern const struct clk_ops clk_alpha_pll_fixed_ops; 117 extern const struct clk_ops clk_alpha_pll_hwfsm_ops; 118 extern const struct clk_ops clk_alpha_pll_postdiv_ops; 119 extern const struct clk_ops clk_alpha_pll_huayra_ops; 120 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; 121 122 extern const struct clk_ops clk_alpha_pll_fabia_ops; 123 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; 124 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops; 125 126 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 127 const struct alpha_pll_config *config); 128 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 129 const struct alpha_pll_config *config); 130 extern const struct clk_ops clk_trion_fixed_pll_ops; 131 extern const struct clk_ops clk_trion_pll_postdiv_ops; 132 133 #endif 134