1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #ifndef __AMDGPU_XGMI_H__ 23 #define __AMDGPU_XGMI_H__ 24 25 #include <drm/task_barrier.h> 26 #include "amdgpu_psp.h" 27 28 struct amdgpu_hive_info { 29 uint64_t hive_id; 30 struct list_head device_list; 31 int number_devices; 32 struct mutex hive_lock, reset_lock; 33 struct kobject *kobj; 34 struct device_attribute dev_attr; 35 struct amdgpu_device *adev; 36 int pstate; /*0 -- low , 1 -- high , -1 unknown*/ 37 struct task_barrier tb; 38 }; 39 40 struct amdgpu_pcs_ras_field { 41 const char *err_name; 42 uint32_t pcs_err_mask; 43 uint32_t pcs_err_shift; 44 }; 45 46 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev, int lock); 47 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev); 48 int amdgpu_xgmi_add_device(struct amdgpu_device *adev); 49 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev); 50 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate); 51 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, 52 struct amdgpu_device *peer_adev); 53 int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev); 54 void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev); 55 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev, 56 uint64_t addr); 57 int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, 58 void *ras_error_status); 59 60 static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev, 61 struct amdgpu_device *bo_adev) 62 { 63 return (adev != bo_adev && 64 adev->gmc.xgmi.hive_id && 65 adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id); 66 } 67 68 #endif 69