1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/acpi.h> 4 #include <linux/bitfield.h> 5 #include <linux/bitops.h> 6 #include <linux/device.h> 7 #include <linux/gpio/driver.h> 8 #include <linux/io.h> 9 #include <linux/ioport.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm.h> 14 #include <linux/resource.h> 15 #include <linux/spinlock.h> 16 #include <linux/types.h> 17 #include <linux/version.h> 18 19 /* 20 * There are 3 YU GPIO blocks: 21 * gpio[0]: HOST_GPIO0->HOST_GPIO31 22 * gpio[1]: HOST_GPIO32->HOST_GPIO63 23 * gpio[2]: HOST_GPIO64->HOST_GPIO69 24 */ 25 #define MLXBF2_GPIO_MAX_PINS_PER_BLOCK 32 26 27 /* 28 * arm_gpio_lock register: 29 * bit[31] lock status: active if set 30 * bit[15:0] set lock 31 * The lock is enabled only if 0xd42f is written to this field 32 */ 33 #define YU_ARM_GPIO_LOCK_ADDR 0x2801088 34 #define YU_ARM_GPIO_LOCK_SIZE 0x8 35 #define YU_LOCK_ACTIVE_BIT(val) (val >> 31) 36 #define YU_ARM_GPIO_LOCK_ACQUIRE 0xd42f 37 #define YU_ARM_GPIO_LOCK_RELEASE 0x0 38 39 /* 40 * gpio[x] block registers and their offset 41 */ 42 #define YU_GPIO_DATAIN 0x04 43 #define YU_GPIO_MODE1 0x08 44 #define YU_GPIO_MODE0 0x0c 45 #define YU_GPIO_DATASET 0x14 46 #define YU_GPIO_DATACLEAR 0x18 47 #define YU_GPIO_MODE1_CLEAR 0x50 48 #define YU_GPIO_MODE0_SET 0x54 49 #define YU_GPIO_MODE0_CLEAR 0x58 50 51 #ifdef CONFIG_PM 52 struct mlxbf2_gpio_context_save_regs { 53 u32 gpio_mode0; 54 u32 gpio_mode1; 55 }; 56 #endif 57 58 /* BlueField-2 gpio block context structure. */ 59 struct mlxbf2_gpio_context { 60 struct gpio_chip gc; 61 62 /* YU GPIO blocks address */ 63 void __iomem *gpio_io; 64 65 #ifdef CONFIG_PM 66 struct mlxbf2_gpio_context_save_regs *csave_regs; 67 #endif 68 }; 69 70 /* BlueField-2 gpio shared structure. */ 71 struct mlxbf2_gpio_param { 72 void __iomem *io; 73 struct resource *res; 74 struct mutex *lock; 75 }; 76 77 static struct resource yu_arm_gpio_lock_res = { 78 .start = YU_ARM_GPIO_LOCK_ADDR, 79 .end = YU_ARM_GPIO_LOCK_ADDR + YU_ARM_GPIO_LOCK_SIZE - 1, 80 .name = "YU_ARM_GPIO_LOCK", 81 }; 82 83 static DEFINE_MUTEX(yu_arm_gpio_lock_mutex); 84 85 static struct mlxbf2_gpio_param yu_arm_gpio_lock_param = { 86 .res = &yu_arm_gpio_lock_res, 87 .lock = &yu_arm_gpio_lock_mutex, 88 }; 89 90 /* Request memory region and map yu_arm_gpio_lock resource */ 91 static int mlxbf2_gpio_get_lock_res(struct platform_device *pdev) 92 { 93 struct device *dev = &pdev->dev; 94 struct resource *res; 95 resource_size_t size; 96 int ret = 0; 97 98 mutex_lock(yu_arm_gpio_lock_param.lock); 99 100 /* Check if the memory map already exists */ 101 if (yu_arm_gpio_lock_param.io) 102 goto exit; 103 104 res = yu_arm_gpio_lock_param.res; 105 size = resource_size(res); 106 107 if (!devm_request_mem_region(dev, res->start, size, res->name)) { 108 ret = -EFAULT; 109 goto exit; 110 } 111 112 yu_arm_gpio_lock_param.io = devm_ioremap(dev, res->start, size); 113 if (IS_ERR(yu_arm_gpio_lock_param.io)) 114 ret = PTR_ERR(yu_arm_gpio_lock_param.io); 115 116 exit: 117 mutex_unlock(yu_arm_gpio_lock_param.lock); 118 119 return ret; 120 } 121 122 /* 123 * Acquire the YU arm_gpio_lock to be able to change the direction 124 * mode. If the lock_active bit is already set, return an error. 125 */ 126 static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs) 127 { 128 u32 arm_gpio_lock_val; 129 130 spin_lock(&gs->gc.bgpio_lock); 131 mutex_lock(yu_arm_gpio_lock_param.lock); 132 133 arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io); 134 135 /* 136 * When lock active bit[31] is set, ModeX is write enabled 137 */ 138 if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) { 139 mutex_unlock(yu_arm_gpio_lock_param.lock); 140 spin_unlock(&gs->gc.bgpio_lock); 141 return -EINVAL; 142 } 143 144 writel(YU_ARM_GPIO_LOCK_ACQUIRE, yu_arm_gpio_lock_param.io); 145 146 return 0; 147 } 148 149 /* 150 * Release the YU arm_gpio_lock after changing the direction mode. 151 */ 152 static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs) 153 { 154 writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io); 155 mutex_unlock(yu_arm_gpio_lock_param.lock); 156 spin_unlock(&gs->gc.bgpio_lock); 157 } 158 159 /* 160 * mode0 and mode1 are both locked by the gpio_lock field. 161 * 162 * Together, mode0 and mode1 define the gpio Mode dependeing also 163 * on Reg_DataOut. 164 * 165 * {mode1,mode0}:{Reg_DataOut=0,Reg_DataOut=1}->{DataOut=0,DataOut=1} 166 * 167 * {0,0}:Reg_DataOut{0,1}->{Z,Z} Input PAD 168 * {0,1}:Reg_DataOut{0,1}->{0,1} Full drive Output PAD 169 * {1,0}:Reg_DataOut{0,1}->{0,Z} 0-set PAD to low, 1-float 170 * {1,1}:Reg_DataOut{0,1}->{Z,1} 0-float, 1-set PAD to high 171 */ 172 173 /* 174 * Set input direction: 175 * {mode1,mode0} = {0,0} 176 */ 177 static int mlxbf2_gpio_direction_input(struct gpio_chip *chip, 178 unsigned int offset) 179 { 180 struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip); 181 int ret; 182 183 /* 184 * Although the arm_gpio_lock was set in the probe function, check again 185 * if it is still enabled to be able to write to the ModeX registers. 186 */ 187 ret = mlxbf2_gpio_lock_acquire(gs); 188 if (ret < 0) 189 return ret; 190 191 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_CLEAR); 192 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR); 193 194 mlxbf2_gpio_lock_release(gs); 195 196 return ret; 197 } 198 199 /* 200 * Set output direction: 201 * {mode1,mode0} = {0,1} 202 */ 203 static int mlxbf2_gpio_direction_output(struct gpio_chip *chip, 204 unsigned int offset, 205 int value) 206 { 207 struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip); 208 int ret = 0; 209 210 /* 211 * Although the arm_gpio_lock was set in the probe function, 212 * check again it is still enabled to be able to write to the 213 * ModeX registers. 214 */ 215 ret = mlxbf2_gpio_lock_acquire(gs); 216 if (ret < 0) 217 return ret; 218 219 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR); 220 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_SET); 221 222 mlxbf2_gpio_lock_release(gs); 223 224 return ret; 225 } 226 227 /* BlueField-2 GPIO driver initialization routine. */ 228 static int 229 mlxbf2_gpio_probe(struct platform_device *pdev) 230 { 231 struct mlxbf2_gpio_context *gs; 232 struct device *dev = &pdev->dev; 233 struct gpio_chip *gc; 234 struct resource *res; 235 unsigned int npins; 236 int ret; 237 238 gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL); 239 if (!gs) 240 return -ENOMEM; 241 242 /* YU GPIO block address */ 243 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 244 if (!res) 245 return -ENODEV; 246 247 gs->gpio_io = devm_ioremap(dev, res->start, resource_size(res)); 248 if (!gs->gpio_io) 249 return -ENOMEM; 250 251 ret = mlxbf2_gpio_get_lock_res(pdev); 252 if (ret) { 253 dev_err(dev, "Failed to get yu_arm_gpio_lock resource\n"); 254 return ret; 255 } 256 257 if (device_property_read_u32(dev, "npins", &npins)) 258 npins = MLXBF2_GPIO_MAX_PINS_PER_BLOCK; 259 260 gc = &gs->gc; 261 262 ret = bgpio_init(gc, dev, 4, 263 gs->gpio_io + YU_GPIO_DATAIN, 264 gs->gpio_io + YU_GPIO_DATASET, 265 gs->gpio_io + YU_GPIO_DATACLEAR, 266 NULL, 267 NULL, 268 0); 269 270 gc->direction_input = mlxbf2_gpio_direction_input; 271 gc->direction_output = mlxbf2_gpio_direction_output; 272 gc->ngpio = npins; 273 gc->owner = THIS_MODULE; 274 275 platform_set_drvdata(pdev, gs); 276 277 ret = devm_gpiochip_add_data(dev, &gs->gc, gs); 278 if (ret) { 279 dev_err(dev, "Failed adding memory mapped gpiochip\n"); 280 return ret; 281 } 282 283 return 0; 284 } 285 286 #ifdef CONFIG_PM 287 static int mlxbf2_gpio_suspend(struct platform_device *pdev, 288 pm_message_t state) 289 { 290 struct mlxbf2_gpio_context *gs = platform_get_drvdata(pdev); 291 292 gs->csave_regs->gpio_mode0 = readl(gs->gpio_io + 293 YU_GPIO_MODE0); 294 gs->csave_regs->gpio_mode1 = readl(gs->gpio_io + 295 YU_GPIO_MODE1); 296 297 return 0; 298 } 299 300 static int mlxbf2_gpio_resume(struct platform_device *pdev) 301 { 302 struct mlxbf2_gpio_context *gs = platform_get_drvdata(pdev); 303 304 writel(gs->csave_regs->gpio_mode0, gs->gpio_io + 305 YU_GPIO_MODE0); 306 writel(gs->csave_regs->gpio_mode1, gs->gpio_io + 307 YU_GPIO_MODE1); 308 309 return 0; 310 } 311 #endif 312 313 static const struct acpi_device_id mlxbf2_gpio_acpi_match[] = { 314 { "MLNXBF22", 0 }, 315 {}, 316 }; 317 MODULE_DEVICE_TABLE(acpi, mlxbf2_gpio_acpi_match); 318 319 static struct platform_driver mlxbf2_gpio_driver = { 320 .driver = { 321 .name = "mlxbf2_gpio", 322 .acpi_match_table = ACPI_PTR(mlxbf2_gpio_acpi_match), 323 }, 324 .probe = mlxbf2_gpio_probe, 325 #ifdef CONFIG_PM 326 .suspend = mlxbf2_gpio_suspend, 327 .resume = mlxbf2_gpio_resume, 328 #endif 329 }; 330 331 module_platform_driver(mlxbf2_gpio_driver); 332 333 MODULE_DESCRIPTION("Mellanox BlueField-2 GPIO Driver"); 334 MODULE_AUTHOR("Mellanox Technologies"); 335 MODULE_LICENSE("GPL v2"); 336