1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de> 4 * JZ4740 platform PWM support 5 * 6 * Limitations: 7 * - The .apply callback doesn't complete the currently running period before 8 * reconfiguring the hardware. 9 * - Each period starts with the inactive part. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/gpio.h> 15 #include <linux/kernel.h> 16 #include <linux/mfd/ingenic-tcu.h> 17 #include <linux/mfd/syscon.h> 18 #include <linux/module.h> 19 #include <linux/of_device.h> 20 #include <linux/platform_device.h> 21 #include <linux/pwm.h> 22 #include <linux/regmap.h> 23 24 #define NUM_PWM 8 25 26 struct jz4740_pwm_chip { 27 struct pwm_chip chip; 28 struct regmap *map; 29 }; 30 31 static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip) 32 { 33 return container_of(chip, struct jz4740_pwm_chip, chip); 34 } 35 36 static bool jz4740_pwm_can_use_chn(struct jz4740_pwm_chip *jz, 37 unsigned int channel) 38 { 39 /* Enable all TCU channels for PWM use by default except channels 0/1 */ 40 u32 pwm_channels_mask = GENMASK(NUM_PWM - 1, 2); 41 42 device_property_read_u32(jz->chip.dev->parent, 43 "ingenic,pwm-channels-mask", 44 &pwm_channels_mask); 45 46 return !!(pwm_channels_mask & BIT(channel)); 47 } 48 49 static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 50 { 51 struct jz4740_pwm_chip *jz = to_jz4740(chip); 52 struct clk *clk; 53 char name[16]; 54 int err; 55 56 if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm)) 57 return -EBUSY; 58 59 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm); 60 61 clk = clk_get(chip->dev, name); 62 if (IS_ERR(clk)) { 63 if (PTR_ERR(clk) != -EPROBE_DEFER) 64 dev_err(chip->dev, "Failed to get clock: %pe", clk); 65 66 return PTR_ERR(clk); 67 } 68 69 err = clk_prepare_enable(clk); 70 if (err < 0) { 71 clk_put(clk); 72 return err; 73 } 74 75 pwm_set_chip_data(pwm, clk); 76 77 return 0; 78 } 79 80 static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 81 { 82 struct clk *clk = pwm_get_chip_data(pwm); 83 84 clk_disable_unprepare(clk); 85 clk_put(clk); 86 } 87 88 static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) 89 { 90 struct jz4740_pwm_chip *jz = to_jz4740(chip); 91 92 /* Enable PWM output */ 93 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), 94 TCU_TCSR_PWM_EN, TCU_TCSR_PWM_EN); 95 96 /* Start counter */ 97 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm)); 98 99 return 0; 100 } 101 102 static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) 103 { 104 struct jz4740_pwm_chip *jz = to_jz4740(chip); 105 106 /* 107 * Set duty > period. This trick allows the TCU channels in TCU2 mode to 108 * properly return to their init level. 109 */ 110 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff); 111 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0); 112 113 /* 114 * Disable PWM output. 115 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the 116 * counter is stopped, while in TCU1 mode the order does not matter. 117 */ 118 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm), 119 TCU_TCSR_PWM_EN, 0); 120 121 /* Stop counter */ 122 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm)); 123 } 124 125 static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 126 const struct pwm_state *state) 127 { 128 struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip); 129 unsigned long long tmp = 0xffffull * NSEC_PER_SEC; 130 struct clk *clk = pwm_get_chip_data(pwm); 131 unsigned long period, duty; 132 long rate; 133 int err; 134 135 /* 136 * Limit the clock to a maximum rate that still gives us a period value 137 * which fits in 16 bits. 138 */ 139 do_div(tmp, state->period); 140 141 /* 142 * /!\ IMPORTANT NOTE: 143 * ------------------- 144 * This code relies on the fact that clk_round_rate() will always round 145 * down, which is not a valid assumption given by the clk API, but only 146 * happens to be true with the clk drivers used for Ingenic SoCs. 147 * 148 * Right now, there is no alternative as the clk API does not have a 149 * round-down function (and won't have one for a while), but if it ever 150 * comes to light, a round-down function should be used instead. 151 */ 152 rate = clk_round_rate(clk, tmp); 153 if (rate < 0) { 154 dev_err(chip->dev, "Unable to round rate: %ld", rate); 155 return rate; 156 } 157 158 /* Calculate period value */ 159 tmp = (unsigned long long)rate * state->period; 160 do_div(tmp, NSEC_PER_SEC); 161 period = (unsigned long)tmp; 162 163 /* Calculate duty value */ 164 tmp = (unsigned long long)period * state->duty_cycle; 165 do_div(tmp, state->period); 166 duty = period - tmp; 167 168 if (duty >= period) 169 duty = period - 1; 170 171 jz4740_pwm_disable(chip, pwm); 172 173 err = clk_set_rate(clk, rate); 174 if (err) { 175 dev_err(chip->dev, "Unable to set rate: %d", err); 176 return err; 177 } 178 179 /* Reset counter to 0 */ 180 regmap_write(jz4740->map, TCU_REG_TCNTc(pwm->hwpwm), 0); 181 182 /* Set duty */ 183 regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), duty); 184 185 /* Set period */ 186 regmap_write(jz4740->map, TCU_REG_TDFRc(pwm->hwpwm), period); 187 188 /* Set abrupt shutdown */ 189 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm), 190 TCU_TCSR_PWM_SD, TCU_TCSR_PWM_SD); 191 192 /* Set polarity */ 193 switch (state->polarity) { 194 case PWM_POLARITY_NORMAL: 195 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm), 196 TCU_TCSR_PWM_INITL_HIGH, 0); 197 break; 198 case PWM_POLARITY_INVERSED: 199 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm), 200 TCU_TCSR_PWM_INITL_HIGH, 201 TCU_TCSR_PWM_INITL_HIGH); 202 break; 203 } 204 205 if (state->enabled) 206 jz4740_pwm_enable(chip, pwm); 207 208 return 0; 209 } 210 211 static const struct pwm_ops jz4740_pwm_ops = { 212 .request = jz4740_pwm_request, 213 .free = jz4740_pwm_free, 214 .apply = jz4740_pwm_apply, 215 .owner = THIS_MODULE, 216 }; 217 218 static int jz4740_pwm_probe(struct platform_device *pdev) 219 { 220 struct device *dev = &pdev->dev; 221 struct jz4740_pwm_chip *jz4740; 222 223 jz4740 = devm_kzalloc(dev, sizeof(*jz4740), GFP_KERNEL); 224 if (!jz4740) 225 return -ENOMEM; 226 227 jz4740->map = device_node_to_regmap(dev->parent->of_node); 228 if (IS_ERR(jz4740->map)) { 229 dev_err(dev, "regmap not found: %ld\n", PTR_ERR(jz4740->map)); 230 return PTR_ERR(jz4740->map); 231 } 232 233 jz4740->chip.dev = dev; 234 jz4740->chip.ops = &jz4740_pwm_ops; 235 jz4740->chip.npwm = NUM_PWM; 236 jz4740->chip.base = -1; 237 jz4740->chip.of_xlate = of_pwm_xlate_with_flags; 238 jz4740->chip.of_pwm_n_cells = 3; 239 240 platform_set_drvdata(pdev, jz4740); 241 242 return pwmchip_add(&jz4740->chip); 243 } 244 245 static int jz4740_pwm_remove(struct platform_device *pdev) 246 { 247 struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev); 248 249 return pwmchip_remove(&jz4740->chip); 250 } 251 252 #ifdef CONFIG_OF 253 static const struct of_device_id jz4740_pwm_dt_ids[] = { 254 { .compatible = "ingenic,jz4740-pwm", }, 255 {}, 256 }; 257 MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids); 258 #endif 259 260 static struct platform_driver jz4740_pwm_driver = { 261 .driver = { 262 .name = "jz4740-pwm", 263 .of_match_table = of_match_ptr(jz4740_pwm_dt_ids), 264 }, 265 .probe = jz4740_pwm_probe, 266 .remove = jz4740_pwm_remove, 267 }; 268 module_platform_driver(jz4740_pwm_driver); 269 270 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 271 MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver"); 272 MODULE_ALIAS("platform:jz4740-pwm"); 273 MODULE_LICENSE("GPL"); 274