1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/renesas,irqc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: DT bindings for the R-Mobile/R-Car/RZ/G interrupt controller 8 9maintainers: 10 - Geert Uytterhoeven <geert+renesas@glider.be> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - renesas,irqc-r8a73a4 # R-Mobile APE6 17 - renesas,irqc-r8a7743 # RZ/G1M 18 - renesas,irqc-r8a7744 # RZ/G1N 19 - renesas,irqc-r8a7745 # RZ/G1E 20 - renesas,irqc-r8a77470 # RZ/G1C 21 - renesas,irqc-r8a7790 # R-Car H2 22 - renesas,irqc-r8a7791 # R-Car M2-W 23 - renesas,irqc-r8a7792 # R-Car V2H 24 - renesas,irqc-r8a7793 # R-Car M2-N 25 - renesas,irqc-r8a7794 # R-Car E2 26 - renesas,intc-ex-r8a774a1 # RZ/G2M 27 - renesas,intc-ex-r8a774b1 # RZ/G2N 28 - renesas,intc-ex-r8a774c0 # RZ/G2E 29 - renesas,intc-ex-r8a7795 # R-Car H3 30 - renesas,intc-ex-r8a7796 # R-Car M3-W 31 - renesas,intc-ex-r8a77965 # R-Car M3-N 32 - renesas,intc-ex-r8a77970 # R-Car V3M 33 - renesas,intc-ex-r8a77980 # R-Car V3H 34 - renesas,intc-ex-r8a77990 # R-Car E3 35 - renesas,intc-ex-r8a77995 # R-Car D3 36 - const: renesas,irqc 37 38 '#interrupt-cells': 39 # an interrupt index and flags, as defined in interrupts.txt in 40 # this directory 41 const: 2 42 43 interrupt-controller: true 44 45 reg: 46 maxItems: 1 47 48 interrupts: 49 minItems: 1 50 maxItems: 32 51 52 clocks: 53 maxItems: 1 54 55 power-domains: 56 maxItems: 1 57 58 resets: 59 maxItems: 1 60 61required: 62 - compatible 63 - '#interrupt-cells' 64 - interrupt-controller 65 - reg 66 - interrupts 67 - clocks 68 69additionalProperties: false 70 71examples: 72 - | 73 #include <dt-bindings/clock/r8a7790-cpg-mssr.h> 74 #include <dt-bindings/interrupt-controller/arm-gic.h> 75 #include <dt-bindings/interrupt-controller/irq.h> 76 77 irqc0: interrupt-controller@e61c0000 { 78 compatible = "renesas,irqc-r8a7790", "renesas,irqc"; 79 #interrupt-cells = <2>; 80 interrupt-controller; 81 reg = <0 0xe61c0000 0 0x200>; 82 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 86 clocks = <&cpg CPG_MOD 407>; 87 }; 88