1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mediatek 8173 ALSA SoC AFE platform driver 4 * 5 * Copyright (c) 2015 MediaTek Inc. 6 * Author: Koro Chen <koro.chen@mediatek.com> 7 * Sascha Hauer <s.hauer@pengutronix.de> 8 * Hidalgo Huang <hidalgo.huang@mediatek.com> 9 * Ir Lian <ir.lian@mediatek.com> 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/pm_runtime.h> 18 #include <sound/soc.h> 19 #include "mt8173-afe-common.h" 20 #include "../common/mtk-base-afe.h" 21 #include "../common/mtk-afe-platform-driver.h" 22 #include "../common/mtk-afe-fe-dai.h" 23 24 /***************************************************************************** 25 * R E G I S T E R D E F I N I T I O N 26 *****************************************************************************/ 27 #define AUDIO_TOP_CON0 0x0000 28 #define AUDIO_TOP_CON1 0x0004 29 #define AFE_DAC_CON0 0x0010 30 #define AFE_DAC_CON1 0x0014 31 #define AFE_I2S_CON1 0x0034 32 #define AFE_I2S_CON2 0x0038 33 #define AFE_CONN_24BIT 0x006c 34 #define AFE_MEMIF_MSB 0x00cc 35 36 #define AFE_CONN1 0x0024 37 #define AFE_CONN2 0x0028 38 #define AFE_CONN3 0x002c 39 #define AFE_CONN7 0x0460 40 #define AFE_CONN8 0x0464 41 #define AFE_HDMI_CONN0 0x0390 42 43 /* Memory interface */ 44 #define AFE_DL1_BASE 0x0040 45 #define AFE_DL1_CUR 0x0044 46 #define AFE_DL1_END 0x0048 47 #define AFE_DL2_BASE 0x0050 48 #define AFE_DL2_CUR 0x0054 49 #define AFE_AWB_BASE 0x0070 50 #define AFE_AWB_CUR 0x007c 51 #define AFE_VUL_BASE 0x0080 52 #define AFE_VUL_CUR 0x008c 53 #define AFE_VUL_END 0x0088 54 #define AFE_DAI_BASE 0x0090 55 #define AFE_DAI_CUR 0x009c 56 #define AFE_MOD_PCM_BASE 0x0330 57 #define AFE_MOD_PCM_CUR 0x033c 58 #define AFE_HDMI_OUT_BASE 0x0374 59 #define AFE_HDMI_OUT_CUR 0x0378 60 #define AFE_HDMI_OUT_END 0x037c 61 62 #define AFE_ADDA_TOP_CON0 0x0120 63 #define AFE_ADDA2_TOP_CON0 0x0600 64 65 #define AFE_HDMI_OUT_CON0 0x0370 66 67 #define AFE_IRQ_MCU_CON 0x03a0 68 #define AFE_IRQ_STATUS 0x03a4 69 #define AFE_IRQ_CLR 0x03a8 70 #define AFE_IRQ_CNT1 0x03ac 71 #define AFE_IRQ_CNT2 0x03b0 72 #define AFE_IRQ_MCU_EN 0x03b4 73 #define AFE_IRQ_CNT5 0x03bc 74 #define AFE_IRQ_CNT7 0x03dc 75 76 #define AFE_TDM_CON1 0x0548 77 #define AFE_TDM_CON2 0x054c 78 79 #define AFE_IRQ_STATUS_BITS 0xff 80 81 /* AUDIO_TOP_CON0 (0x0000) */ 82 #define AUD_TCON0_PDN_SPDF (0x1 << 21) 83 #define AUD_TCON0_PDN_HDMI (0x1 << 20) 84 #define AUD_TCON0_PDN_24M (0x1 << 9) 85 #define AUD_TCON0_PDN_22M (0x1 << 8) 86 #define AUD_TCON0_PDN_AFE (0x1 << 2) 87 88 /* AFE_I2S_CON1 (0x0034) */ 89 #define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12) 90 #define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8) 91 #define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3) 92 #define AFE_I2S_CON1_EN (0x1 << 0) 93 94 /* AFE_I2S_CON2 (0x0038) */ 95 #define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12) 96 #define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8) 97 #define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3) 98 #define AFE_I2S_CON2_EN (0x1 << 0) 99 100 /* AFE_CONN_24BIT (0x006c) */ 101 #define AFE_CONN_24BIT_O04 (0x1 << 4) 102 #define AFE_CONN_24BIT_O03 (0x1 << 3) 103 104 /* AFE_HDMI_CONN0 (0x0390) */ 105 #define AFE_HDMI_CONN0_O37_I37 (0x7 << 21) 106 #define AFE_HDMI_CONN0_O36_I36 (0x6 << 18) 107 #define AFE_HDMI_CONN0_O35_I33 (0x3 << 15) 108 #define AFE_HDMI_CONN0_O34_I32 (0x2 << 12) 109 #define AFE_HDMI_CONN0_O33_I35 (0x5 << 9) 110 #define AFE_HDMI_CONN0_O32_I34 (0x4 << 6) 111 #define AFE_HDMI_CONN0_O31_I31 (0x1 << 3) 112 #define AFE_HDMI_CONN0_O30_I30 (0x0 << 0) 113 114 /* AFE_TDM_CON1 (0x0548) */ 115 #define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24) 116 #define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12) 117 #define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8) 118 #define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4) 119 #define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3) 120 #define AFE_TDM_CON1_LRCK_INV (0x1 << 2) 121 #define AFE_TDM_CON1_BCK_INV (0x1 << 1) 122 #define AFE_TDM_CON1_EN (0x1 << 0) 123 124 enum afe_tdm_ch_start { 125 AFE_TDM_CH_START_O30_O31 = 0, 126 AFE_TDM_CH_START_O32_O33, 127 AFE_TDM_CH_START_O34_O35, 128 AFE_TDM_CH_START_O36_O37, 129 AFE_TDM_CH_ZERO, 130 }; 131 132 static const unsigned int mt8173_afe_backup_list[] = { 133 AUDIO_TOP_CON0, 134 AFE_CONN1, 135 AFE_CONN2, 136 AFE_CONN7, 137 AFE_CONN8, 138 AFE_DAC_CON1, 139 AFE_DL1_BASE, 140 AFE_DL1_END, 141 AFE_VUL_BASE, 142 AFE_VUL_END, 143 AFE_HDMI_OUT_BASE, 144 AFE_HDMI_OUT_END, 145 AFE_HDMI_CONN0, 146 AFE_DAC_CON0, 147 }; 148 149 struct mt8173_afe_private { 150 struct clk *clocks[MT8173_CLK_NUM]; 151 }; 152 153 static const struct snd_pcm_hardware mt8173_afe_hardware = { 154 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 155 SNDRV_PCM_INFO_MMAP_VALID), 156 .buffer_bytes_max = 256 * 1024, 157 .period_bytes_min = 512, 158 .period_bytes_max = 128 * 1024, 159 .periods_min = 2, 160 .periods_max = 256, 161 .fifo_size = 0, 162 }; 163 164 struct mt8173_afe_rate { 165 unsigned int rate; 166 unsigned int regvalue; 167 }; 168 169 static const struct mt8173_afe_rate mt8173_afe_i2s_rates[] = { 170 { .rate = 8000, .regvalue = 0 }, 171 { .rate = 11025, .regvalue = 1 }, 172 { .rate = 12000, .regvalue = 2 }, 173 { .rate = 16000, .regvalue = 4 }, 174 { .rate = 22050, .regvalue = 5 }, 175 { .rate = 24000, .regvalue = 6 }, 176 { .rate = 32000, .regvalue = 8 }, 177 { .rate = 44100, .regvalue = 9 }, 178 { .rate = 48000, .regvalue = 10 }, 179 { .rate = 88000, .regvalue = 11 }, 180 { .rate = 96000, .regvalue = 12 }, 181 { .rate = 174000, .regvalue = 13 }, 182 { .rate = 192000, .regvalue = 14 }, 183 }; 184 185 static int mt8173_afe_i2s_fs(unsigned int sample_rate) 186 { 187 int i; 188 189 for (i = 0; i < ARRAY_SIZE(mt8173_afe_i2s_rates); i++) 190 if (mt8173_afe_i2s_rates[i].rate == sample_rate) 191 return mt8173_afe_i2s_rates[i].regvalue; 192 193 return -EINVAL; 194 } 195 196 static int mt8173_afe_set_i2s(struct mtk_base_afe *afe, unsigned int rate) 197 { 198 unsigned int val; 199 int fs = mt8173_afe_i2s_fs(rate); 200 201 if (fs < 0) 202 return -EINVAL; 203 204 /* from external ADC */ 205 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1); 206 regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1); 207 208 /* set input */ 209 val = AFE_I2S_CON2_LOW_JITTER_CLK | 210 AFE_I2S_CON2_RATE(fs) | 211 AFE_I2S_CON2_FORMAT_I2S; 212 213 regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val); 214 215 /* set output */ 216 val = AFE_I2S_CON1_LOW_JITTER_CLK | 217 AFE_I2S_CON1_RATE(fs) | 218 AFE_I2S_CON1_FORMAT_I2S; 219 220 regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val); 221 return 0; 222 } 223 224 static void mt8173_afe_set_i2s_enable(struct mtk_base_afe *afe, bool enable) 225 { 226 unsigned int val; 227 228 regmap_read(afe->regmap, AFE_I2S_CON2, &val); 229 if (!!(val & AFE_I2S_CON2_EN) == enable) 230 return; 231 232 /* input */ 233 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable); 234 235 /* output */ 236 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable); 237 } 238 239 static int mt8173_afe_dais_enable_clks(struct mtk_base_afe *afe, 240 struct clk *m_ck, struct clk *b_ck) 241 { 242 int ret; 243 244 if (m_ck) { 245 ret = clk_prepare_enable(m_ck); 246 if (ret) { 247 dev_err(afe->dev, "Failed to enable m_ck\n"); 248 return ret; 249 } 250 } 251 252 if (b_ck) { 253 ret = clk_prepare_enable(b_ck); 254 if (ret) { 255 dev_err(afe->dev, "Failed to enable b_ck\n"); 256 return ret; 257 } 258 } 259 return 0; 260 } 261 262 static int mt8173_afe_dais_set_clks(struct mtk_base_afe *afe, 263 struct clk *m_ck, unsigned int mck_rate, 264 struct clk *b_ck, unsigned int bck_rate) 265 { 266 int ret; 267 268 if (m_ck) { 269 ret = clk_set_rate(m_ck, mck_rate); 270 if (ret) { 271 dev_err(afe->dev, "Failed to set m_ck rate\n"); 272 return ret; 273 } 274 } 275 276 if (b_ck) { 277 ret = clk_set_rate(b_ck, bck_rate); 278 if (ret) { 279 dev_err(afe->dev, "Failed to set b_ck rate\n"); 280 return ret; 281 } 282 } 283 return 0; 284 } 285 286 static void mt8173_afe_dais_disable_clks(struct mtk_base_afe *afe, 287 struct clk *m_ck, struct clk *b_ck) 288 { 289 if (m_ck) 290 clk_disable_unprepare(m_ck); 291 if (b_ck) 292 clk_disable_unprepare(b_ck); 293 } 294 295 static int mt8173_afe_i2s_startup(struct snd_pcm_substream *substream, 296 struct snd_soc_dai *dai) 297 { 298 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 299 300 if (snd_soc_dai_active(dai)) 301 return 0; 302 303 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 304 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0); 305 return 0; 306 } 307 308 static void mt8173_afe_i2s_shutdown(struct snd_pcm_substream *substream, 309 struct snd_soc_dai *dai) 310 { 311 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 312 313 if (snd_soc_dai_active(dai)) 314 return; 315 316 mt8173_afe_set_i2s_enable(afe, false); 317 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 318 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 319 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M); 320 } 321 322 static int mt8173_afe_i2s_prepare(struct snd_pcm_substream *substream, 323 struct snd_soc_dai *dai) 324 { 325 struct snd_pcm_runtime * const runtime = substream->runtime; 326 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 327 struct mt8173_afe_private *afe_priv = afe->platform_priv; 328 int ret; 329 330 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M], 331 runtime->rate * 256, NULL, 0); 332 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M], 333 runtime->rate * 256, NULL, 0); 334 /* config I2S */ 335 ret = mt8173_afe_set_i2s(afe, substream->runtime->rate); 336 if (ret) 337 return ret; 338 339 mt8173_afe_set_i2s_enable(afe, true); 340 341 return 0; 342 } 343 344 static int mt8173_afe_hdmi_startup(struct snd_pcm_substream *substream, 345 struct snd_soc_dai *dai) 346 { 347 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 348 struct mt8173_afe_private *afe_priv = afe->platform_priv; 349 350 if (snd_soc_dai_active(dai)) 351 return 0; 352 353 mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 354 afe_priv->clocks[MT8173_CLK_I2S3_B]); 355 return 0; 356 } 357 358 static void mt8173_afe_hdmi_shutdown(struct snd_pcm_substream *substream, 359 struct snd_soc_dai *dai) 360 { 361 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 362 struct mt8173_afe_private *afe_priv = afe->platform_priv; 363 364 if (snd_soc_dai_active(dai)) 365 return; 366 367 mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 368 afe_priv->clocks[MT8173_CLK_I2S3_B]); 369 } 370 371 static int mt8173_afe_hdmi_prepare(struct snd_pcm_substream *substream, 372 struct snd_soc_dai *dai) 373 { 374 struct snd_pcm_runtime * const runtime = substream->runtime; 375 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 376 struct mt8173_afe_private *afe_priv = afe->platform_priv; 377 378 unsigned int val; 379 380 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 381 runtime->rate * 128, 382 afe_priv->clocks[MT8173_CLK_I2S3_B], 383 runtime->rate * runtime->channels * 32); 384 385 val = AFE_TDM_CON1_BCK_INV | 386 AFE_TDM_CON1_LRCK_INV | 387 AFE_TDM_CON1_1_BCK_DELAY | 388 AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */ 389 AFE_TDM_CON1_WLEN_32BIT | 390 AFE_TDM_CON1_32_BCK_CYCLES | 391 AFE_TDM_CON1_LRCK_WIDTH(32); 392 regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val); 393 394 /* set tdm2 config */ 395 switch (runtime->channels) { 396 case 1: 397 case 2: 398 val = AFE_TDM_CH_START_O30_O31; 399 val |= (AFE_TDM_CH_ZERO << 4); 400 val |= (AFE_TDM_CH_ZERO << 8); 401 val |= (AFE_TDM_CH_ZERO << 12); 402 break; 403 case 3: 404 case 4: 405 val = AFE_TDM_CH_START_O30_O31; 406 val |= (AFE_TDM_CH_START_O32_O33 << 4); 407 val |= (AFE_TDM_CH_ZERO << 8); 408 val |= (AFE_TDM_CH_ZERO << 12); 409 break; 410 case 5: 411 case 6: 412 val = AFE_TDM_CH_START_O30_O31; 413 val |= (AFE_TDM_CH_START_O32_O33 << 4); 414 val |= (AFE_TDM_CH_START_O34_O35 << 8); 415 val |= (AFE_TDM_CH_ZERO << 12); 416 break; 417 case 7: 418 case 8: 419 val = AFE_TDM_CH_START_O30_O31; 420 val |= (AFE_TDM_CH_START_O32_O33 << 4); 421 val |= (AFE_TDM_CH_START_O34_O35 << 8); 422 val |= (AFE_TDM_CH_START_O36_O37 << 12); 423 break; 424 default: 425 val = 0; 426 } 427 regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val); 428 429 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 430 0x000000f0, runtime->channels << 4); 431 return 0; 432 } 433 434 static int mt8173_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd, 435 struct snd_soc_dai *dai) 436 { 437 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 438 439 dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name); 440 441 switch (cmd) { 442 case SNDRV_PCM_TRIGGER_START: 443 case SNDRV_PCM_TRIGGER_RESUME: 444 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 445 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0); 446 447 /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */ 448 regmap_write(afe->regmap, AFE_HDMI_CONN0, 449 AFE_HDMI_CONN0_O30_I30 | 450 AFE_HDMI_CONN0_O31_I31 | 451 AFE_HDMI_CONN0_O32_I34 | 452 AFE_HDMI_CONN0_O33_I35 | 453 AFE_HDMI_CONN0_O34_I32 | 454 AFE_HDMI_CONN0_O35_I33 | 455 AFE_HDMI_CONN0_O36_I36 | 456 AFE_HDMI_CONN0_O37_I37); 457 458 /* enable Out control */ 459 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1); 460 461 /* enable tdm */ 462 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1); 463 464 return 0; 465 case SNDRV_PCM_TRIGGER_STOP: 466 case SNDRV_PCM_TRIGGER_SUSPEND: 467 /* disable tdm */ 468 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0); 469 470 /* disable Out control */ 471 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0); 472 473 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 474 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 475 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF); 476 return 0; 477 default: 478 return -EINVAL; 479 } 480 } 481 482 static int mt8173_memif_fs(struct snd_pcm_substream *substream, 483 unsigned int rate) 484 { 485 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 486 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 487 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 488 struct mtk_base_afe_memif *memif = &afe->memif[asoc_rtd_to_cpu(rtd, 0)->id]; 489 int fs; 490 491 if (memif->data->id == MT8173_AFE_MEMIF_DAI || 492 memif->data->id == MT8173_AFE_MEMIF_MOD_DAI) { 493 switch (rate) { 494 case 8000: 495 fs = 0; 496 break; 497 case 16000: 498 fs = 1; 499 break; 500 case 32000: 501 fs = 2; 502 break; 503 default: 504 return -EINVAL; 505 } 506 } else { 507 fs = mt8173_afe_i2s_fs(rate); 508 } 509 return fs; 510 } 511 512 static int mt8173_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) 513 { 514 return mt8173_afe_i2s_fs(rate); 515 } 516 517 /* BE DAIs */ 518 static const struct snd_soc_dai_ops mt8173_afe_i2s_ops = { 519 .startup = mt8173_afe_i2s_startup, 520 .shutdown = mt8173_afe_i2s_shutdown, 521 .prepare = mt8173_afe_i2s_prepare, 522 }; 523 524 static const struct snd_soc_dai_ops mt8173_afe_hdmi_ops = { 525 .startup = mt8173_afe_hdmi_startup, 526 .shutdown = mt8173_afe_hdmi_shutdown, 527 .prepare = mt8173_afe_hdmi_prepare, 528 .trigger = mt8173_afe_hdmi_trigger, 529 }; 530 531 static struct snd_soc_dai_driver mt8173_afe_pcm_dais[] = { 532 /* FE DAIs: memory intefaces to CPU */ 533 { 534 .name = "DL1", /* downlink 1 */ 535 .id = MT8173_AFE_MEMIF_DL1, 536 .playback = { 537 .stream_name = "DL1", 538 .channels_min = 1, 539 .channels_max = 2, 540 .rates = SNDRV_PCM_RATE_8000_48000, 541 .formats = SNDRV_PCM_FMTBIT_S16_LE, 542 }, 543 .ops = &mtk_afe_fe_ops, 544 }, { 545 .name = "VUL", /* voice uplink */ 546 .id = MT8173_AFE_MEMIF_VUL, 547 .capture = { 548 .stream_name = "VUL", 549 .channels_min = 1, 550 .channels_max = 2, 551 .rates = SNDRV_PCM_RATE_8000_48000, 552 .formats = SNDRV_PCM_FMTBIT_S16_LE, 553 }, 554 .ops = &mtk_afe_fe_ops, 555 }, { 556 /* BE DAIs */ 557 .name = "I2S", 558 .id = MT8173_AFE_IO_I2S, 559 .playback = { 560 .stream_name = "I2S Playback", 561 .channels_min = 1, 562 .channels_max = 2, 563 .rates = SNDRV_PCM_RATE_8000_48000, 564 .formats = SNDRV_PCM_FMTBIT_S16_LE, 565 }, 566 .capture = { 567 .stream_name = "I2S Capture", 568 .channels_min = 1, 569 .channels_max = 2, 570 .rates = SNDRV_PCM_RATE_8000_48000, 571 .formats = SNDRV_PCM_FMTBIT_S16_LE, 572 }, 573 .ops = &mt8173_afe_i2s_ops, 574 .symmetric_rates = 1, 575 }, 576 }; 577 578 static struct snd_soc_dai_driver mt8173_afe_hdmi_dais[] = { 579 /* FE DAIs */ 580 { 581 .name = "HDMI", 582 .id = MT8173_AFE_MEMIF_HDMI, 583 .playback = { 584 .stream_name = "HDMI", 585 .channels_min = 2, 586 .channels_max = 8, 587 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 588 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 589 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 590 SNDRV_PCM_RATE_192000, 591 .formats = SNDRV_PCM_FMTBIT_S16_LE, 592 }, 593 .ops = &mtk_afe_fe_ops, 594 }, { 595 /* BE DAIs */ 596 .name = "HDMIO", 597 .id = MT8173_AFE_IO_HDMI, 598 .playback = { 599 .stream_name = "HDMIO Playback", 600 .channels_min = 2, 601 .channels_max = 8, 602 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 603 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 604 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 605 SNDRV_PCM_RATE_192000, 606 .formats = SNDRV_PCM_FMTBIT_S16_LE, 607 }, 608 .ops = &mt8173_afe_hdmi_ops, 609 }, 610 }; 611 612 static const struct snd_kcontrol_new mt8173_afe_o03_mix[] = { 613 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0), 614 }; 615 616 static const struct snd_kcontrol_new mt8173_afe_o04_mix[] = { 617 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0), 618 }; 619 620 static const struct snd_kcontrol_new mt8173_afe_o09_mix[] = { 621 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0), 622 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0), 623 }; 624 625 static const struct snd_kcontrol_new mt8173_afe_o10_mix[] = { 626 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0), 627 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0), 628 }; 629 630 static const struct snd_soc_dapm_widget mt8173_afe_pcm_widgets[] = { 631 /* inter-connections */ 632 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0), 633 SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0), 634 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0), 635 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0), 636 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0), 637 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0), 638 639 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, 640 mt8173_afe_o03_mix, ARRAY_SIZE(mt8173_afe_o03_mix)), 641 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0, 642 mt8173_afe_o04_mix, ARRAY_SIZE(mt8173_afe_o04_mix)), 643 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0, 644 mt8173_afe_o09_mix, ARRAY_SIZE(mt8173_afe_o09_mix)), 645 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0, 646 mt8173_afe_o10_mix, ARRAY_SIZE(mt8173_afe_o10_mix)), 647 }; 648 649 static const struct snd_soc_dapm_route mt8173_afe_pcm_routes[] = { 650 {"I05", NULL, "DL1"}, 651 {"I06", NULL, "DL1"}, 652 {"I2S Playback", NULL, "O03"}, 653 {"I2S Playback", NULL, "O04"}, 654 {"VUL", NULL, "O09"}, 655 {"VUL", NULL, "O10"}, 656 {"I03", NULL, "I2S Capture"}, 657 {"I04", NULL, "I2S Capture"}, 658 {"I17", NULL, "I2S Capture"}, 659 {"I18", NULL, "I2S Capture"}, 660 { "O03", "I05 Switch", "I05" }, 661 { "O04", "I06 Switch", "I06" }, 662 { "O09", "I17 Switch", "I17" }, 663 { "O09", "I03 Switch", "I03" }, 664 { "O10", "I18 Switch", "I18" }, 665 { "O10", "I04 Switch", "I04" }, 666 }; 667 668 static const struct snd_soc_dapm_route mt8173_afe_hdmi_routes[] = { 669 {"HDMIO Playback", NULL, "HDMI"}, 670 }; 671 672 static const struct snd_soc_component_driver mt8173_afe_pcm_dai_component = { 673 .name = "mt8173-afe-pcm-dai", 674 .dapm_widgets = mt8173_afe_pcm_widgets, 675 .num_dapm_widgets = ARRAY_SIZE(mt8173_afe_pcm_widgets), 676 .dapm_routes = mt8173_afe_pcm_routes, 677 .num_dapm_routes = ARRAY_SIZE(mt8173_afe_pcm_routes), 678 .suspend = mtk_afe_suspend, 679 .resume = mtk_afe_resume, 680 }; 681 682 static const struct snd_soc_component_driver mt8173_afe_hdmi_dai_component = { 683 .name = "mt8173-afe-hdmi-dai", 684 .dapm_routes = mt8173_afe_hdmi_routes, 685 .num_dapm_routes = ARRAY_SIZE(mt8173_afe_hdmi_routes), 686 .suspend = mtk_afe_suspend, 687 .resume = mtk_afe_resume, 688 }; 689 690 static const char *aud_clks[MT8173_CLK_NUM] = { 691 [MT8173_CLK_INFRASYS_AUD] = "infra_sys_audio_clk", 692 [MT8173_CLK_TOP_PDN_AUD] = "top_pdn_audio", 693 [MT8173_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus", 694 [MT8173_CLK_I2S0_M] = "i2s0_m", 695 [MT8173_CLK_I2S1_M] = "i2s1_m", 696 [MT8173_CLK_I2S2_M] = "i2s2_m", 697 [MT8173_CLK_I2S3_M] = "i2s3_m", 698 [MT8173_CLK_I2S3_B] = "i2s3_b", 699 [MT8173_CLK_BCK0] = "bck0", 700 [MT8173_CLK_BCK1] = "bck1", 701 }; 702 703 static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = { 704 { 705 .name = "DL1", 706 .id = MT8173_AFE_MEMIF_DL1, 707 .reg_ofs_base = AFE_DL1_BASE, 708 .reg_ofs_cur = AFE_DL1_CUR, 709 .fs_reg = AFE_DAC_CON1, 710 .fs_shift = 0, 711 .fs_maskbit = 0xf, 712 .mono_reg = AFE_DAC_CON1, 713 .mono_shift = 21, 714 .hd_reg = -1, 715 .enable_reg = AFE_DAC_CON0, 716 .enable_shift = 1, 717 .msb_reg = AFE_MEMIF_MSB, 718 .msb_shift = 0, 719 .agent_disable_reg = -1, 720 }, { 721 .name = "DL2", 722 .id = MT8173_AFE_MEMIF_DL2, 723 .reg_ofs_base = AFE_DL2_BASE, 724 .reg_ofs_cur = AFE_DL2_CUR, 725 .fs_reg = AFE_DAC_CON1, 726 .fs_shift = 4, 727 .fs_maskbit = 0xf, 728 .mono_reg = AFE_DAC_CON1, 729 .mono_shift = 22, 730 .hd_reg = -1, 731 .enable_reg = AFE_DAC_CON0, 732 .enable_shift = 2, 733 .msb_reg = AFE_MEMIF_MSB, 734 .msb_shift = 1, 735 .agent_disable_reg = -1, 736 }, { 737 .name = "VUL", 738 .id = MT8173_AFE_MEMIF_VUL, 739 .reg_ofs_base = AFE_VUL_BASE, 740 .reg_ofs_cur = AFE_VUL_CUR, 741 .fs_reg = AFE_DAC_CON1, 742 .fs_shift = 16, 743 .fs_maskbit = 0xf, 744 .mono_reg = AFE_DAC_CON1, 745 .mono_shift = 27, 746 .hd_reg = -1, 747 .enable_reg = AFE_DAC_CON0, 748 .enable_shift = 3, 749 .msb_reg = AFE_MEMIF_MSB, 750 .msb_shift = 6, 751 .agent_disable_reg = -1, 752 }, { 753 .name = "DAI", 754 .id = MT8173_AFE_MEMIF_DAI, 755 .reg_ofs_base = AFE_DAI_BASE, 756 .reg_ofs_cur = AFE_DAI_CUR, 757 .fs_reg = AFE_DAC_CON0, 758 .fs_shift = 24, 759 .fs_maskbit = 0x3, 760 .mono_reg = -1, 761 .mono_shift = -1, 762 .hd_reg = -1, 763 .enable_reg = AFE_DAC_CON0, 764 .enable_shift = 4, 765 .msb_reg = AFE_MEMIF_MSB, 766 .msb_shift = 5, 767 .agent_disable_reg = -1, 768 }, { 769 .name = "AWB", 770 .id = MT8173_AFE_MEMIF_AWB, 771 .reg_ofs_base = AFE_AWB_BASE, 772 .reg_ofs_cur = AFE_AWB_CUR, 773 .fs_reg = AFE_DAC_CON1, 774 .fs_shift = 12, 775 .fs_maskbit = 0xf, 776 .mono_reg = AFE_DAC_CON1, 777 .mono_shift = 24, 778 .hd_reg = -1, 779 .enable_reg = AFE_DAC_CON0, 780 .enable_shift = 6, 781 .msb_reg = AFE_MEMIF_MSB, 782 .msb_shift = 3, 783 .agent_disable_reg = -1, 784 }, { 785 .name = "MOD_DAI", 786 .id = MT8173_AFE_MEMIF_MOD_DAI, 787 .reg_ofs_base = AFE_MOD_PCM_BASE, 788 .reg_ofs_cur = AFE_MOD_PCM_CUR, 789 .fs_reg = AFE_DAC_CON1, 790 .fs_shift = 30, 791 .fs_maskbit = 0x3, 792 .mono_reg = AFE_DAC_CON1, 793 .mono_shift = 30, 794 .hd_reg = -1, 795 .enable_reg = AFE_DAC_CON0, 796 .enable_shift = 7, 797 .msb_reg = AFE_MEMIF_MSB, 798 .msb_shift = 4, 799 .agent_disable_reg = -1, 800 }, { 801 .name = "HDMI", 802 .id = MT8173_AFE_MEMIF_HDMI, 803 .reg_ofs_base = AFE_HDMI_OUT_BASE, 804 .reg_ofs_cur = AFE_HDMI_OUT_CUR, 805 .fs_reg = -1, 806 .fs_shift = -1, 807 .fs_maskbit = -1, 808 .mono_reg = -1, 809 .mono_shift = -1, 810 .hd_reg = -1, 811 .enable_reg = -1, 812 .msb_reg = AFE_MEMIF_MSB, 813 .msb_shift = 8, 814 .agent_disable_reg = -1, 815 }, 816 }; 817 818 static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = { 819 { 820 .id = MT8173_AFE_IRQ_DL1, 821 .irq_cnt_reg = AFE_IRQ_CNT1, 822 .irq_cnt_shift = 0, 823 .irq_cnt_maskbit = 0x3ffff, 824 .irq_en_reg = AFE_IRQ_MCU_CON, 825 .irq_en_shift = 0, 826 .irq_fs_reg = AFE_IRQ_MCU_CON, 827 .irq_fs_shift = 4, 828 .irq_fs_maskbit = 0xf, 829 .irq_clr_reg = AFE_IRQ_CLR, 830 .irq_clr_shift = 0, 831 }, { 832 .id = MT8173_AFE_IRQ_DL2, 833 .irq_cnt_reg = AFE_IRQ_CNT1, 834 .irq_cnt_shift = 20, 835 .irq_cnt_maskbit = 0x3ffff, 836 .irq_en_reg = AFE_IRQ_MCU_CON, 837 .irq_en_shift = 2, 838 .irq_fs_reg = AFE_IRQ_MCU_CON, 839 .irq_fs_shift = 16, 840 .irq_fs_maskbit = 0xf, 841 .irq_clr_reg = AFE_IRQ_CLR, 842 .irq_clr_shift = 2, 843 844 }, { 845 .id = MT8173_AFE_IRQ_VUL, 846 .irq_cnt_reg = AFE_IRQ_CNT2, 847 .irq_cnt_shift = 0, 848 .irq_cnt_maskbit = 0x3ffff, 849 .irq_en_reg = AFE_IRQ_MCU_CON, 850 .irq_en_shift = 1, 851 .irq_fs_reg = AFE_IRQ_MCU_CON, 852 .irq_fs_shift = 8, 853 .irq_fs_maskbit = 0xf, 854 .irq_clr_reg = AFE_IRQ_CLR, 855 .irq_clr_shift = 1, 856 }, { 857 .id = MT8173_AFE_IRQ_DAI, 858 .irq_cnt_reg = AFE_IRQ_CNT2, 859 .irq_cnt_shift = 20, 860 .irq_cnt_maskbit = 0x3ffff, 861 .irq_en_reg = AFE_IRQ_MCU_CON, 862 .irq_en_shift = 3, 863 .irq_fs_reg = AFE_IRQ_MCU_CON, 864 .irq_fs_shift = 20, 865 .irq_fs_maskbit = 0xf, 866 .irq_clr_reg = AFE_IRQ_CLR, 867 .irq_clr_shift = 3, 868 }, { 869 .id = MT8173_AFE_IRQ_AWB, 870 .irq_cnt_reg = AFE_IRQ_CNT7, 871 .irq_cnt_shift = 0, 872 .irq_cnt_maskbit = 0x3ffff, 873 .irq_en_reg = AFE_IRQ_MCU_CON, 874 .irq_en_shift = 14, 875 .irq_fs_reg = AFE_IRQ_MCU_CON, 876 .irq_fs_shift = 24, 877 .irq_fs_maskbit = 0xf, 878 .irq_clr_reg = AFE_IRQ_CLR, 879 .irq_clr_shift = 6, 880 }, { 881 .id = MT8173_AFE_IRQ_DAI, 882 .irq_cnt_reg = AFE_IRQ_CNT2, 883 .irq_cnt_shift = 20, 884 .irq_cnt_maskbit = 0x3ffff, 885 .irq_en_reg = AFE_IRQ_MCU_CON, 886 .irq_en_shift = 3, 887 .irq_fs_reg = AFE_IRQ_MCU_CON, 888 .irq_fs_shift = 20, 889 .irq_fs_maskbit = 0xf, 890 .irq_clr_reg = AFE_IRQ_CLR, 891 .irq_clr_shift = 3, 892 }, { 893 .id = MT8173_AFE_IRQ_HDMI, 894 .irq_cnt_reg = AFE_IRQ_CNT5, 895 .irq_cnt_shift = 0, 896 .irq_cnt_maskbit = 0x3ffff, 897 .irq_en_reg = AFE_IRQ_MCU_CON, 898 .irq_en_shift = 12, 899 .irq_fs_reg = -1, 900 .irq_fs_maskbit = -1, 901 .irq_clr_reg = AFE_IRQ_CLR, 902 .irq_clr_shift = 4, 903 }, 904 }; 905 906 static const struct regmap_config mt8173_afe_regmap_config = { 907 .reg_bits = 32, 908 .reg_stride = 4, 909 .val_bits = 32, 910 .max_register = AFE_ADDA2_TOP_CON0, 911 .cache_type = REGCACHE_NONE, 912 }; 913 914 static irqreturn_t mt8173_afe_irq_handler(int irq, void *dev_id) 915 { 916 struct mtk_base_afe *afe = dev_id; 917 unsigned int reg_value; 918 int i, ret; 919 920 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, ®_value); 921 if (ret) { 922 dev_err(afe->dev, "%s irq status err\n", __func__); 923 reg_value = AFE_IRQ_STATUS_BITS; 924 goto err_irq; 925 } 926 927 for (i = 0; i < MT8173_AFE_MEMIF_NUM; i++) { 928 struct mtk_base_afe_memif *memif = &afe->memif[i]; 929 struct mtk_base_afe_irq *irq; 930 931 if (memif->irq_usage < 0) 932 continue; 933 934 irq = &afe->irqs[memif->irq_usage]; 935 936 if (!(reg_value & (1 << irq->irq_data->irq_clr_shift))) 937 continue; 938 939 snd_pcm_period_elapsed(memif->substream); 940 } 941 942 err_irq: 943 /* clear irq */ 944 regmap_write(afe->regmap, AFE_IRQ_CLR, 945 reg_value & AFE_IRQ_STATUS_BITS); 946 947 return IRQ_HANDLED; 948 } 949 950 static int mt8173_afe_runtime_suspend(struct device *dev) 951 { 952 struct mtk_base_afe *afe = dev_get_drvdata(dev); 953 struct mt8173_afe_private *afe_priv = afe->platform_priv; 954 955 /* disable AFE */ 956 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0); 957 958 /* disable AFE clk */ 959 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 960 AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE); 961 962 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]); 963 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]); 964 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]); 965 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]); 966 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); 967 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); 968 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); 969 return 0; 970 } 971 972 static int mt8173_afe_runtime_resume(struct device *dev) 973 { 974 struct mtk_base_afe *afe = dev_get_drvdata(dev); 975 struct mt8173_afe_private *afe_priv = afe->platform_priv; 976 int ret; 977 978 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); 979 if (ret) 980 return ret; 981 982 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); 983 if (ret) 984 goto err_infra; 985 986 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); 987 if (ret) 988 goto err_top_aud_bus; 989 990 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]); 991 if (ret) 992 goto err_top_aud; 993 994 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]); 995 if (ret) 996 goto err_bck0; 997 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]); 998 if (ret) 999 goto err_i2s1_m; 1000 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]); 1001 if (ret) 1002 goto err_i2s2_m; 1003 1004 /* enable AFE clk */ 1005 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0); 1006 1007 /* set O3/O4 16bits */ 1008 regmap_update_bits(afe->regmap, AFE_CONN_24BIT, 1009 AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0); 1010 1011 /* unmask all IRQs */ 1012 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff); 1013 1014 /* enable AFE */ 1015 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); 1016 return 0; 1017 1018 err_i2s1_m: 1019 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]); 1020 err_i2s2_m: 1021 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]); 1022 err_bck0: 1023 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]); 1024 err_top_aud: 1025 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); 1026 err_top_aud_bus: 1027 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); 1028 err_infra: 1029 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); 1030 return ret; 1031 } 1032 1033 static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe) 1034 { 1035 size_t i; 1036 struct mt8173_afe_private *afe_priv = afe->platform_priv; 1037 1038 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) { 1039 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]); 1040 if (IS_ERR(afe_priv->clocks[i])) { 1041 dev_err(afe->dev, "%s devm_clk_get %s fail\n", 1042 __func__, aud_clks[i]); 1043 return PTR_ERR(afe_priv->clocks[i]); 1044 } 1045 } 1046 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */ 1047 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */ 1048 return 0; 1049 } 1050 1051 static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev) 1052 { 1053 int ret, i; 1054 int irq_id; 1055 struct mtk_base_afe *afe; 1056 struct mt8173_afe_private *afe_priv; 1057 1058 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33)); 1059 if (ret) 1060 return ret; 1061 1062 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 1063 if (!afe) 1064 return -ENOMEM; 1065 1066 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 1067 GFP_KERNEL); 1068 afe_priv = afe->platform_priv; 1069 if (!afe_priv) 1070 return -ENOMEM; 1071 1072 afe->dev = &pdev->dev; 1073 1074 irq_id = platform_get_irq(pdev, 0); 1075 if (irq_id <= 0) 1076 return irq_id < 0 ? irq_id : -ENXIO; 1077 ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler, 1078 0, "Afe_ISR_Handle", (void *)afe); 1079 if (ret) { 1080 dev_err(afe->dev, "could not request_irq\n"); 1081 return ret; 1082 } 1083 1084 afe->base_addr = devm_platform_ioremap_resource(pdev, 0); 1085 if (IS_ERR(afe->base_addr)) 1086 return PTR_ERR(afe->base_addr); 1087 1088 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, 1089 &mt8173_afe_regmap_config); 1090 if (IS_ERR(afe->regmap)) 1091 return PTR_ERR(afe->regmap); 1092 1093 /* initial audio related clock */ 1094 ret = mt8173_afe_init_audio_clk(afe); 1095 if (ret) { 1096 dev_err(afe->dev, "mt8173_afe_init_audio_clk fail\n"); 1097 return ret; 1098 } 1099 1100 /* memif % irq initialize*/ 1101 afe->memif_size = MT8173_AFE_MEMIF_NUM; 1102 afe->memif = devm_kcalloc(afe->dev, afe->memif_size, 1103 sizeof(*afe->memif), GFP_KERNEL); 1104 if (!afe->memif) 1105 return -ENOMEM; 1106 1107 afe->irqs_size = MT8173_AFE_IRQ_NUM; 1108 afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size, 1109 sizeof(*afe->irqs), GFP_KERNEL); 1110 if (!afe->irqs) 1111 return -ENOMEM; 1112 1113 for (i = 0; i < afe->irqs_size; i++) { 1114 afe->memif[i].data = &memif_data[i]; 1115 afe->irqs[i].irq_data = &irq_data[i]; 1116 afe->irqs[i].irq_occupyed = true; 1117 afe->memif[i].irq_usage = i; 1118 afe->memif[i].const_irq = 1; 1119 } 1120 1121 afe->mtk_afe_hardware = &mt8173_afe_hardware; 1122 afe->memif_fs = mt8173_memif_fs; 1123 afe->irq_fs = mt8173_irq_fs; 1124 1125 platform_set_drvdata(pdev, afe); 1126 1127 pm_runtime_enable(&pdev->dev); 1128 if (!pm_runtime_enabled(&pdev->dev)) { 1129 ret = mt8173_afe_runtime_resume(&pdev->dev); 1130 if (ret) 1131 goto err_pm_disable; 1132 } 1133 1134 afe->reg_back_up_list = mt8173_afe_backup_list; 1135 afe->reg_back_up_list_num = ARRAY_SIZE(mt8173_afe_backup_list); 1136 afe->runtime_resume = mt8173_afe_runtime_resume; 1137 afe->runtime_suspend = mt8173_afe_runtime_suspend; 1138 1139 ret = devm_snd_soc_register_component(&pdev->dev, 1140 &mtk_afe_pcm_platform, 1141 NULL, 0); 1142 if (ret) 1143 goto err_pm_disable; 1144 1145 ret = devm_snd_soc_register_component(&pdev->dev, 1146 &mt8173_afe_pcm_dai_component, 1147 mt8173_afe_pcm_dais, 1148 ARRAY_SIZE(mt8173_afe_pcm_dais)); 1149 if (ret) 1150 goto err_pm_disable; 1151 1152 ret = devm_snd_soc_register_component(&pdev->dev, 1153 &mt8173_afe_hdmi_dai_component, 1154 mt8173_afe_hdmi_dais, 1155 ARRAY_SIZE(mt8173_afe_hdmi_dais)); 1156 if (ret) 1157 goto err_pm_disable; 1158 1159 dev_info(&pdev->dev, "MT8173 AFE driver initialized.\n"); 1160 return 0; 1161 1162 err_pm_disable: 1163 pm_runtime_disable(&pdev->dev); 1164 return ret; 1165 } 1166 1167 static int mt8173_afe_pcm_dev_remove(struct platform_device *pdev) 1168 { 1169 pm_runtime_disable(&pdev->dev); 1170 if (!pm_runtime_status_suspended(&pdev->dev)) 1171 mt8173_afe_runtime_suspend(&pdev->dev); 1172 return 0; 1173 } 1174 1175 static const struct of_device_id mt8173_afe_pcm_dt_match[] = { 1176 { .compatible = "mediatek,mt8173-afe-pcm", }, 1177 { } 1178 }; 1179 MODULE_DEVICE_TABLE(of, mt8173_afe_pcm_dt_match); 1180 1181 static const struct dev_pm_ops mt8173_afe_pm_ops = { 1182 SET_RUNTIME_PM_OPS(mt8173_afe_runtime_suspend, 1183 mt8173_afe_runtime_resume, NULL) 1184 }; 1185 1186 static struct platform_driver mt8173_afe_pcm_driver = { 1187 .driver = { 1188 .name = "mt8173-afe-pcm", 1189 .of_match_table = mt8173_afe_pcm_dt_match, 1190 .pm = &mt8173_afe_pm_ops, 1191 }, 1192 .probe = mt8173_afe_pcm_dev_probe, 1193 .remove = mt8173_afe_pcm_dev_remove, 1194 }; 1195 1196 module_platform_driver(mt8173_afe_pcm_driver); 1197 1198 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver"); 1199 MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>"); 1200 MODULE_LICENSE("GPL v2"); 1201