1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "fw.h" 9 #include "tx.h" 10 #include "rx.h" 11 #include "phy.h" 12 #include "rtw8723d.h" 13 #include "rtw8723d_table.h" 14 #include "mac.h" 15 #include "reg.h" 16 #include "debug.h" 17 18 static const struct rtw_hw_reg rtw8723d_txagc[] = { 19 [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 }, 20 [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 }, 21 [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 }, 22 [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 }, 23 [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff }, 24 [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 }, 25 [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 }, 26 [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 }, 27 [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff }, 28 [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 }, 29 [DESC_RATE48M] = { .addr = 0xe04, .mask = 0x00ff0000 }, 30 [DESC_RATE54M] = { .addr = 0xe04, .mask = 0xff000000 }, 31 [DESC_RATEMCS0] = { .addr = 0xe10, .mask = 0x000000ff }, 32 [DESC_RATEMCS1] = { .addr = 0xe10, .mask = 0x0000ff00 }, 33 [DESC_RATEMCS2] = { .addr = 0xe10, .mask = 0x00ff0000 }, 34 [DESC_RATEMCS3] = { .addr = 0xe10, .mask = 0xff000000 }, 35 [DESC_RATEMCS4] = { .addr = 0xe14, .mask = 0x000000ff }, 36 [DESC_RATEMCS5] = { .addr = 0xe14, .mask = 0x0000ff00 }, 37 [DESC_RATEMCS6] = { .addr = 0xe14, .mask = 0x00ff0000 }, 38 [DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 }, 39 }; 40 41 #define WLAN_TXQ_RPT_EN 0x1F 42 #define WLAN_SLOT_TIME 0x09 43 #define WLAN_RL_VAL 0x3030 44 #define WLAN_BAR_VAL 0x0201ffff 45 #define BIT_MASK_TBTT_HOLD 0x00000fff 46 #define BIT_SHIFT_TBTT_HOLD 8 47 #define BIT_MASK_TBTT_SETUP 0x000000ff 48 #define BIT_SHIFT_TBTT_SETUP 0 49 #define BIT_MASK_TBTT_MASK ((BIT_MASK_TBTT_HOLD << BIT_SHIFT_TBTT_HOLD) | \ 50 (BIT_MASK_TBTT_SETUP << BIT_SHIFT_TBTT_SETUP)) 51 #define TBTT_TIME(s, h)((((s) & BIT_MASK_TBTT_SETUP) << BIT_SHIFT_TBTT_SETUP) |\ 52 (((h) & BIT_MASK_TBTT_HOLD) << BIT_SHIFT_TBTT_HOLD)) 53 #define WLAN_TBTT_TIME_NORMAL TBTT_TIME(0x04, 0x80) 54 #define WLAN_TBTT_TIME_STOP_BCN TBTT_TIME(0x04, 0x64) 55 #define WLAN_PIFS_VAL 0 56 #define WLAN_AGG_BRK_TIME 0x16 57 #define WLAN_NAV_PROT_LEN 0x0040 58 #define WLAN_SPEC_SIFS 0x100a 59 #define WLAN_RX_PKT_LIMIT 0x17 60 #define WLAN_MAX_AGG_NR 0x0A 61 #define WLAN_AMPDU_MAX_TIME 0x1C 62 #define WLAN_ANT_SEL 0x82 63 #define WLAN_LTR_IDLE_LAT 0x883C883C 64 #define WLAN_LTR_ACT_LAT 0x880B880B 65 #define WLAN_LTR_CTRL1 0xCB004010 66 #define WLAN_LTR_CTRL2 0x01233425 67 68 static void rtw8723d_lck(struct rtw_dev *rtwdev) 69 { 70 u32 lc_cal; 71 u8 val_ctx, rf_val; 72 int ret; 73 74 val_ctx = rtw_read8(rtwdev, REG_CTX); 75 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) 76 rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE); 77 else 78 rtw_write8(rtwdev, REG_TXPAUSE, 0xFF); 79 lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 80 81 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK); 82 83 ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1, 84 10000, 1000000, false, 85 rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK); 86 if (ret) 87 rtw_warn(rtwdev, "failed to poll LCK status bit\n"); 88 89 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal); 90 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) 91 rtw_write8(rtwdev, REG_CTX, val_ctx); 92 else 93 rtw_write8(rtwdev, REG_TXPAUSE, 0x00); 94 } 95 96 static const u32 rtw8723d_ofdm_swing_table[] = { 97 0x0b40002d, 0x0c000030, 0x0cc00033, 0x0d800036, 0x0e400039, 0x0f00003c, 98 0x10000040, 0x11000044, 0x12000048, 0x1300004c, 0x14400051, 0x15800056, 99 0x16c0005b, 0x18000060, 0x19800066, 0x1b00006c, 0x1c800072, 0x1e400079, 100 0x20000080, 0x22000088, 0x24000090, 0x26000098, 0x288000a2, 0x2ac000ab, 101 0x2d4000b5, 0x300000c0, 0x32c000cb, 0x35c000d7, 0x390000e4, 0x3c8000f2, 102 0x40000100, 0x43c0010f, 0x47c0011f, 0x4c000130, 0x50800142, 0x55400155, 103 0x5a400169, 0x5fc0017f, 0x65400195, 0x6b8001ae, 0x71c001c7, 0x788001e2, 104 0x7f8001fe, 105 }; 106 107 static const u32 rtw8723d_cck_swing_table[] = { 108 0x0CD, 0x0D9, 0x0E6, 0x0F3, 0x102, 0x111, 0x121, 0x132, 0x144, 0x158, 109 0x16C, 0x182, 0x198, 0x1B1, 0x1CA, 0x1E5, 0x202, 0x221, 0x241, 0x263, 110 0x287, 0x2AE, 0x2D6, 0x301, 0x32F, 0x35F, 0x392, 0x3C9, 0x402, 0x43F, 111 0x47F, 0x4C3, 0x50C, 0x558, 0x5A9, 0x5FF, 0x65A, 0x6BA, 0x720, 0x78C, 112 0x7FF, 113 }; 114 115 #define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_ofdm_swing_table) 116 #define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8723d_cck_swing_table) 117 118 static void rtw8723d_pwrtrack_init(struct rtw_dev *rtwdev) 119 { 120 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 121 u8 path; 122 123 dm_info->default_ofdm_index = RTW_DEF_OFDM_SWING_INDEX; 124 125 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 126 ewma_thermal_init(&dm_info->avg_thermal[path]); 127 dm_info->delta_power_index[path] = 0; 128 } 129 dm_info->pwr_trk_triggered = false; 130 dm_info->pwr_trk_init_trigger = true; 131 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 132 dm_info->txagc_remnant_cck = 0; 133 dm_info->txagc_remnant_ofdm = 0; 134 } 135 136 static void rtw8723d_phy_set_param(struct rtw_dev *rtwdev) 137 { 138 u8 xtal_cap; 139 u32 val32; 140 141 /* power on BB/RF domain */ 142 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, 143 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 144 rtw_write8_set(rtwdev, REG_RF_CTRL, 145 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 146 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); 147 148 rtw_phy_load_tables(rtwdev); 149 150 /* post init after header files config */ 151 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF); 152 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, BIT_HIQ_NO_LMT_EN_ROOT); 153 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN); 154 155 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 156 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 157 xtal_cap | (xtal_cap << 6)); 158 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); 159 if ((rtwdev->efuse.afe >> 4) == 14) { 160 rtw_write32_set(rtwdev, REG_AFE_CTRL3, BIT_XTAL_GMP_BIT4); 161 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BITS_PLL); 162 rtw_write32_set(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA1); 163 rtw_write32_clr(rtwdev, REG_LDO_SWR_CTRL, BIT_XTA0); 164 } 165 166 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 167 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 168 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL); 169 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL); 170 rtw_write8(rtwdev, REG_ATIMWND, 0x2); 171 rtw_write8(rtwdev, REG_BCN_CTRL, 172 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT); 173 val32 = rtw_read32(rtwdev, REG_TBTT_PROHIBIT); 174 val32 &= ~BIT_MASK_TBTT_MASK; 175 val32 |= WLAN_TBTT_TIME_STOP_BCN; 176 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, val32); 177 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL); 178 rtw_write8(rtwdev, REG_AGGR_BREAK_TIME, WLAN_AGG_BRK_TIME); 179 rtw_write16(rtwdev, REG_NAV_PROT_LEN, WLAN_NAV_PROT_LEN); 180 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS); 181 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); 182 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); 183 rtw_write8(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU); 184 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT); 185 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR); 186 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME); 187 rtw_write8(rtwdev, REG_LEDCFG2, WLAN_ANT_SEL); 188 189 rtw_write32(rtwdev, REG_LTR_IDLE_LATENCY, WLAN_LTR_IDLE_LAT); 190 rtw_write32(rtwdev, REG_LTR_ACTIVE_LATENCY, WLAN_LTR_ACT_LAT); 191 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC, WLAN_LTR_CTRL1); 192 rtw_write32(rtwdev, REG_LTR_CTRL_BASIC + 4, WLAN_LTR_CTRL2); 193 194 rtw_phy_init(rtwdev); 195 196 rtw_write16_set(rtwdev, REG_TXDMA_OFFSET_CHK, BIT_DROP_DATA_EN); 197 198 rtw8723d_lck(rtwdev); 199 200 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 201 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); 202 203 rtw8723d_pwrtrack_init(rtwdev); 204 } 205 206 static void rtw8723de_efuse_parsing(struct rtw_efuse *efuse, 207 struct rtw8723d_efuse *map) 208 { 209 ether_addr_copy(efuse->addr, map->e.mac_addr); 210 } 211 212 static int rtw8723d_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 213 { 214 struct rtw_efuse *efuse = &rtwdev->efuse; 215 struct rtw8723d_efuse *map; 216 int i; 217 218 map = (struct rtw8723d_efuse *)log_map; 219 220 efuse->rfe_option = 0; 221 efuse->rf_board_option = map->rf_board_option; 222 efuse->crystal_cap = map->xtal_k; 223 efuse->pa_type_2g = map->pa_type; 224 efuse->lna_type_2g = map->lna_type_2g[0]; 225 efuse->channel_plan = map->channel_plan; 226 efuse->country_code[0] = map->country_code[0]; 227 efuse->country_code[1] = map->country_code[1]; 228 efuse->bt_setting = map->rf_bt_setting; 229 efuse->regd = map->rf_board_option & 0x7; 230 efuse->thermal_meter[0] = map->thermal_meter; 231 efuse->thermal_meter_k = map->thermal_meter; 232 efuse->afe = map->afe; 233 234 for (i = 0; i < 4; i++) 235 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 236 237 switch (rtw_hci_type(rtwdev)) { 238 case RTW_HCI_TYPE_PCIE: 239 rtw8723de_efuse_parsing(efuse, map); 240 break; 241 default: 242 /* unsupported now */ 243 return -ENOTSUPP; 244 } 245 246 return 0; 247 } 248 249 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 250 struct rtw_rx_pkt_stat *pkt_stat) 251 { 252 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 253 s8 min_rx_power = -120; 254 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 255 256 pkt_stat->rx_power[RF_PATH_A] = pwdb - 97; 257 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 258 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 259 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 260 min_rx_power); 261 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 262 } 263 264 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 265 struct rtw_rx_pkt_stat *pkt_stat) 266 { 267 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 268 u8 rxsc, bw; 269 s8 min_rx_power = -120; 270 s8 rx_evm; 271 272 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 273 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 274 else 275 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 276 277 if (GET_PHY_STAT_P1_RF_MODE(phy_status) == 0) 278 bw = RTW_CHANNEL_WIDTH_20; 279 else if ((rxsc == 1) || (rxsc == 2)) 280 bw = RTW_CHANNEL_WIDTH_20; 281 else 282 bw = RTW_CHANNEL_WIDTH_40; 283 284 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 285 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 286 pkt_stat->bw = bw; 287 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 288 min_rx_power); 289 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 290 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 291 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 292 293 dm_info->curr_rx_rate = pkt_stat->rate; 294 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 295 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1; 296 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1; 297 298 rx_evm = clamp_t(s8, -pkt_stat->rx_evm[RF_PATH_A] >> 1, 0, 64); 299 rx_evm &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ 300 dm_info->rx_evm_dbm[RF_PATH_A] = rx_evm; 301 } 302 303 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 304 struct rtw_rx_pkt_stat *pkt_stat) 305 { 306 u8 page; 307 308 page = *phy_status & 0xf; 309 310 switch (page) { 311 case 0: 312 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 313 break; 314 case 1: 315 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 316 break; 317 default: 318 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 319 return; 320 } 321 } 322 323 static void rtw8723d_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 324 struct rtw_rx_pkt_stat *pkt_stat, 325 struct ieee80211_rx_status *rx_status) 326 { 327 struct ieee80211_hdr *hdr; 328 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 329 u8 *phy_status = NULL; 330 331 memset(pkt_stat, 0, sizeof(*pkt_stat)); 332 333 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 334 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 335 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 336 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 337 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 338 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 339 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 340 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 341 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 342 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 343 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 344 pkt_stat->ppdu_cnt = 0; 345 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 346 347 /* drv_info_sz is in unit of 8-bytes */ 348 pkt_stat->drv_info_sz *= 8; 349 350 /* c2h cmd pkt's rx/phy status is not interested */ 351 if (pkt_stat->is_c2h) 352 return; 353 354 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 355 pkt_stat->drv_info_sz); 356 if (pkt_stat->phy_status) { 357 phy_status = rx_desc + desc_sz + pkt_stat->shift; 358 query_phy_status(rtwdev, phy_status, pkt_stat); 359 } 360 361 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 362 } 363 364 static bool rtw8723d_check_spur_ov_thres(struct rtw_dev *rtwdev, 365 u8 channel, u32 thres) 366 { 367 u32 freq; 368 bool ret = false; 369 370 if (channel == 13) 371 freq = FREQ_CH13; 372 else if (channel == 14) 373 freq = FREQ_CH14; 374 else 375 return false; 376 377 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE); 378 rtw_write32(rtwdev, REG_PSDFN, freq); 379 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq); 380 381 msleep(30); 382 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres) 383 ret = true; 384 385 rtw_write32(rtwdev, REG_PSDFN, freq); 386 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE); 387 388 return ret; 389 } 390 391 static void rtw8723d_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch) 392 { 393 if (!notch) { 394 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); 395 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 396 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 397 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 398 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 399 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 400 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 401 return; 402 } 403 404 switch (channel) { 405 case 13: 406 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); 407 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 408 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x04000000); 409 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 410 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 411 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 412 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 413 break; 414 case 14: 415 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); 416 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 417 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 418 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 419 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 420 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00080000); 421 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 422 break; 423 default: 424 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 425 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 426 break; 427 } 428 } 429 430 static void rtw8723d_spur_cal(struct rtw_dev *rtwdev, u8 channel) 431 { 432 bool notch; 433 434 if (channel < 13) { 435 rtw8723d_cfg_notch(rtwdev, channel, false); 436 return; 437 } 438 439 notch = rtw8723d_check_spur_ov_thres(rtwdev, channel, SPUR_THRES); 440 rtw8723d_cfg_notch(rtwdev, channel, notch); 441 } 442 443 static void rtw8723d_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 444 { 445 u32 rf_cfgch_a, rf_cfgch_b; 446 447 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 448 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK); 449 450 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK; 451 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK; 452 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK); 453 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK); 454 455 rf_cfgch_a &= ~RFCFGCH_BW_MASK; 456 switch (bw) { 457 case RTW_CHANNEL_WIDTH_20: 458 rf_cfgch_a |= RFCFGCH_BW_20M; 459 break; 460 case RTW_CHANNEL_WIDTH_40: 461 rf_cfgch_a |= RFCFGCH_BW_40M; 462 break; 463 default: 464 break; 465 } 466 467 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a); 468 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b); 469 470 rtw8723d_spur_cal(rtwdev, channel); 471 } 472 473 static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR] = { 474 [0] = { 475 { .len = 4, .reg = 0xA24, .val = 0x64B80C1C }, 476 { .len = 4, .reg = 0xA28, .val = 0x00008810 }, 477 { .len = 4, .reg = 0xAAC, .val = 0x01235667 }, 478 }, 479 [1] = { 480 { .len = 4, .reg = 0xA24, .val = 0x0000B81C }, 481 { .len = 4, .reg = 0xA28, .val = 0x00000000 }, 482 { .len = 4, .reg = 0xAAC, .val = 0x00003667 }, 483 }, 484 }; 485 486 static void rtw8723d_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 487 u8 primary_ch_idx) 488 { 489 const struct rtw_backup_info *cck_dfir; 490 int i; 491 492 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1]; 493 494 for (i = 0; i < CCK_DFIR_NR; i++, cck_dfir++) 495 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); 496 497 switch (bw) { 498 case RTW_CHANNEL_WIDTH_20: 499 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); 500 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); 501 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 1); 502 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_MASK_RXBB_DFIR, 0xa); 503 break; 504 case RTW_CHANNEL_WIDTH_40: 505 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); 506 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); 507 rtw_write32_mask(rtwdev, REG_BBRX_DFIR, BIT_RXBB_DFIR_EN, 0); 508 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, 509 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 510 break; 511 default: 512 break; 513 } 514 } 515 516 static void rtw8723d_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 517 u8 primary_chan_idx) 518 { 519 rtw8723d_set_channel_rf(rtwdev, channel, bw); 520 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 521 rtw8723d_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 522 } 523 524 #define BIT_CFENDFORM BIT(9) 525 #define BIT_WMAC_TCR_ERR0 BIT(12) 526 #define BIT_WMAC_TCR_ERR1 BIT(13) 527 #define BIT_TCR_CFG (BIT_CFENDFORM | BIT_WMAC_TCR_ERR0 | \ 528 BIT_WMAC_TCR_ERR1) 529 #define WLAN_RX_FILTER0 0xFFFF 530 #define WLAN_RX_FILTER1 0x400 531 #define WLAN_RX_FILTER2 0xFFFF 532 #define WLAN_RCR_CFG 0x700060CE 533 534 static int rtw8723d_mac_init(struct rtw_dev *rtwdev) 535 { 536 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 537 rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG); 538 539 rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 540 rtw_write16(rtwdev, REG_RXFLTMAP1, WLAN_RX_FILTER1); 541 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 542 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 543 544 rtw_write32(rtwdev, REG_INT_MIG, 0); 545 rtw_write32(rtwdev, REG_MCUTST_1, 0x0); 546 547 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA); 548 rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0); 549 550 return 0; 551 } 552 553 static void rtw8723d_shutdown(struct rtw_dev *rtwdev) 554 { 555 rtw_write16_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS); 556 } 557 558 static void rtw8723d_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 559 { 560 u8 ldo_pwr; 561 562 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 563 if (enable) { 564 ldo_pwr &= ~BIT_MASK_LDO25_VOLTAGE; 565 ldo_pwr |= (BIT_LDO25_VOLTAGE_V25 << 4) | BIT_LDO25_EN; 566 } else { 567 ldo_pwr &= ~BIT_LDO25_EN; 568 } 569 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 570 } 571 572 static void 573 rtw8723d_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 574 { 575 struct rtw_hal *hal = &rtwdev->hal; 576 const struct rtw_hw_reg *txagc; 577 u8 rate, pwr_index; 578 int j; 579 580 for (j = 0; j < rtw_rate_size[rs]; j++) { 581 rate = rtw_rate_section[rs][j]; 582 pwr_index = hal->tx_pwr_tbl[path][rate]; 583 584 if (rate >= ARRAY_SIZE(rtw8723d_txagc)) { 585 rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate); 586 continue; 587 } 588 txagc = &rtw8723d_txagc[rate]; 589 if (!txagc->addr) { 590 rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate); 591 continue; 592 } 593 594 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index); 595 } 596 } 597 598 static void rtw8723d_set_tx_power_index(struct rtw_dev *rtwdev) 599 { 600 struct rtw_hal *hal = &rtwdev->hal; 601 int rs, path; 602 603 for (path = 0; path < hal->rf_path_num; path++) { 604 for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++) 605 rtw8723d_set_tx_power_index_by_rate(rtwdev, path, rs); 606 } 607 } 608 609 static void rtw8723d_efuse_grant(struct rtw_dev *rtwdev, bool on) 610 { 611 if (on) { 612 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); 613 614 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR); 615 rtw_write16_set(rtwdev, REG_SYS_CLKR, BIT_LOADER_CLK_EN | BIT_ANA8M); 616 } else { 617 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); 618 } 619 } 620 621 static void rtw8723d_false_alarm_statistics(struct rtw_dev *rtwdev) 622 { 623 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 624 u32 cck_fa_cnt; 625 u32 ofdm_fa_cnt; 626 u32 crc32_cnt; 627 u32 val32; 628 629 /* hold counter */ 630 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1); 631 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1); 632 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1); 633 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1); 634 635 cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0); 636 cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8; 637 638 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N); 639 ofdm_fa_cnt = u32_get_bits(val32, BIT_MASK_OFDM_FF_CNT); 640 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_SF_CNT); 641 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N); 642 dm_info->ofdm_cca_cnt = u32_get_bits(val32, BIT_MASK_OFDM_CCA_CNT); 643 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_PF_CNT); 644 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N); 645 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_RI_CNT); 646 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_CRC_CNT); 647 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N); 648 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_MNS_CNT); 649 650 dm_info->cck_fa_cnt = cck_fa_cnt; 651 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 652 dm_info->total_fa_cnt = cck_fa_cnt + ofdm_fa_cnt; 653 654 dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N); 655 dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N); 656 crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N); 657 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_ERR); 658 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_OK); 659 crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N); 660 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_ERR); 661 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_OK); 662 dm_info->vht_err_cnt = 0; 663 dm_info->vht_ok_cnt = 0; 664 665 val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N); 666 dm_info->cck_cca_cnt = (u32_get_bits(val32, BIT_MASK_CCK_FA_MSB) << 8) | 667 u32_get_bits(val32, BIT_MASK_CCK_FA_LSB); 668 dm_info->total_cca_cnt = dm_info->cck_cca_cnt + dm_info->ofdm_cca_cnt; 669 670 /* reset counter */ 671 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1); 672 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); 673 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1); 674 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); 675 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); 676 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0); 677 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0); 678 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2); 679 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0); 680 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2); 681 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1); 682 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0); 683 } 684 685 static const u32 iqk_adda_regs[] = { 686 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 687 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec 688 }; 689 690 static const u32 iqk_mac8_regs[] = {0x522, 0x550, 0x551}; 691 static const u32 iqk_mac32_regs[] = {0x40}; 692 693 static const u32 iqk_bb_regs[] = { 694 0xc04, 0xc08, 0x874, 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0xa04 695 }; 696 697 #define IQK_ADDA_REG_NUM ARRAY_SIZE(iqk_adda_regs) 698 #define IQK_MAC8_REG_NUM ARRAY_SIZE(iqk_mac8_regs) 699 #define IQK_MAC32_REG_NUM ARRAY_SIZE(iqk_mac32_regs) 700 #define IQK_BB_REG_NUM ARRAY_SIZE(iqk_bb_regs) 701 702 struct iqk_backup_regs { 703 u32 adda[IQK_ADDA_REG_NUM]; 704 u8 mac8[IQK_MAC8_REG_NUM]; 705 u32 mac32[IQK_MAC32_REG_NUM]; 706 u32 bb[IQK_BB_REG_NUM]; 707 708 u32 lte_path; 709 u32 lte_gnt; 710 711 u32 bb_sel_btg; 712 u8 btg_sel; 713 714 u8 igia; 715 u8 igib; 716 }; 717 718 static void rtw8723d_iqk_backup_regs(struct rtw_dev *rtwdev, 719 struct iqk_backup_regs *backup) 720 { 721 int i; 722 723 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 724 backup->adda[i] = rtw_read32(rtwdev, iqk_adda_regs[i]); 725 726 for (i = 0; i < IQK_MAC8_REG_NUM; i++) 727 backup->mac8[i] = rtw_read8(rtwdev, iqk_mac8_regs[i]); 728 for (i = 0; i < IQK_MAC32_REG_NUM; i++) 729 backup->mac32[i] = rtw_read32(rtwdev, iqk_mac32_regs[i]); 730 731 for (i = 0; i < IQK_BB_REG_NUM; i++) 732 backup->bb[i] = rtw_read32(rtwdev, iqk_bb_regs[i]); 733 734 backup->igia = rtw_read32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0); 735 backup->igib = rtw_read32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0); 736 737 backup->bb_sel_btg = rtw_read32(rtwdev, REG_BB_SEL_BTG); 738 } 739 740 static void rtw8723d_iqk_restore_regs(struct rtw_dev *rtwdev, 741 const struct iqk_backup_regs *backup) 742 { 743 int i; 744 745 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 746 rtw_write32(rtwdev, iqk_adda_regs[i], backup->adda[i]); 747 748 for (i = 0; i < IQK_MAC8_REG_NUM; i++) 749 rtw_write8(rtwdev, iqk_mac8_regs[i], backup->mac8[i]); 750 for (i = 0; i < IQK_MAC32_REG_NUM; i++) 751 rtw_write32(rtwdev, iqk_mac32_regs[i], backup->mac32[i]); 752 753 for (i = 0; i < IQK_BB_REG_NUM; i++) 754 rtw_write32(rtwdev, iqk_bb_regs[i], backup->bb[i]); 755 756 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 757 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia); 758 759 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50); 760 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib); 761 762 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00); 763 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00); 764 } 765 766 static void rtw8723d_iqk_backup_path_ctrl(struct rtw_dev *rtwdev, 767 struct iqk_backup_regs *backup) 768 { 769 backup->btg_sel = rtw_read8(rtwdev, REG_BTG_SEL); 770 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n", 771 backup->btg_sel); 772 } 773 774 static void rtw8723d_iqk_config_path_ctrl(struct rtw_dev *rtwdev) 775 { 776 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1); 777 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n", 778 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 779 } 780 781 static void rtw8723d_iqk_restore_path_ctrl(struct rtw_dev *rtwdev, 782 const struct iqk_backup_regs *backup) 783 { 784 rtw_write8(rtwdev, REG_BTG_SEL, backup->btg_sel); 785 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n", 786 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 787 } 788 789 static void rtw8723d_iqk_backup_lte_path_gnt(struct rtw_dev *rtwdev, 790 struct iqk_backup_regs *backup) 791 { 792 backup->lte_path = rtw_read32(rtwdev, REG_LTECOEX_PATH_CONTROL); 793 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038); 794 mdelay(1); 795 backup->lte_gnt = rtw_read32(rtwdev, REG_LTECOEX_READ_DATA); 796 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n", 797 backup->lte_gnt); 798 } 799 800 static void rtw8723d_iqk_config_lte_path_gnt(struct rtw_dev *rtwdev) 801 { 802 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, 0x0000ff00); 803 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038); 804 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL, BIT_LTE_MUX_CTRL_PATH, 0x1); 805 } 806 807 static void rtw8723d_iqk_restore_lte_path_gnt(struct rtw_dev *rtwdev, 808 const struct iqk_backup_regs *bak) 809 { 810 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, bak->lte_gnt); 811 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038); 812 rtw_write32(rtwdev, REG_LTECOEX_PATH_CONTROL, bak->lte_path); 813 } 814 815 struct rtw_8723d_iqk_cfg { 816 const char *name; 817 u32 val_bb_sel_btg; 818 u32 reg_lutwe; 819 u32 val_txiqk_pi; 820 u32 reg_padlut; 821 u32 reg_gaintx; 822 u32 reg_bspad; 823 u32 val_wlint; 824 u32 val_wlsel; 825 u32 val_iqkpts; 826 }; 827 828 static const struct rtw_8723d_iqk_cfg iqk_tx_cfg[PATH_NR] = { 829 [PATH_S1] = { 830 .name = "S1", 831 .val_bb_sel_btg = 0x99000000, 832 .reg_lutwe = RF_LUTWE, 833 .val_txiqk_pi = 0x8214019f, 834 .reg_padlut = RF_LUTDBG, 835 .reg_gaintx = RF_GAINTX, 836 .reg_bspad = RF_BSPAD, 837 .val_wlint = 0xe0d, 838 .val_wlsel = 0x60d, 839 .val_iqkpts = 0xfa000000, 840 }, 841 [PATH_S0] = { 842 .name = "S0", 843 .val_bb_sel_btg = 0x99000280, 844 .reg_lutwe = RF_LUTWE2, 845 .val_txiqk_pi = 0x8214018a, 846 .reg_padlut = RF_TXADBG, 847 .reg_gaintx = RF_TRXIQ, 848 .reg_bspad = RF_TXATANK, 849 .val_wlint = 0xe6d, 850 .val_wlsel = 0x66d, 851 .val_iqkpts = 0xf9000000, 852 }, 853 }; 854 855 static u8 rtw8723d_iqk_check_tx_failed(struct rtw_dev *rtwdev, 856 const struct rtw_8723d_iqk_cfg *iqk_cfg) 857 { 858 s32 tx_x, tx_y; 859 u32 tx_fail; 860 861 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n", 862 rtw_read32(rtwdev, REG_IQK_RES_RY)); 863 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", 864 rtw_read32(rtwdev, REG_IQK_RES_TX), 865 rtw_read32(rtwdev, REG_IQK_RES_TY)); 866 rtw_dbg(rtwdev, RTW_DBG_RFK, 867 "[IQK] 0xe90(before IQK)= 0x%x, 0xe98(afer IQK) = 0x%x\n", 868 rtw_read32(rtwdev, 0xe90), 869 rtw_read32(rtwdev, 0xe98)); 870 871 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL); 872 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 873 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 874 875 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR) 876 return IQK_TX_OK; 877 878 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s TXIQK is failed\n", 879 iqk_cfg->name); 880 881 return 0; 882 } 883 884 static u8 rtw8723d_iqk_check_rx_failed(struct rtw_dev *rtwdev, 885 const struct rtw_8723d_iqk_cfg *iqk_cfg) 886 { 887 s32 rx_x, rx_y; 888 u32 rx_fail; 889 890 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", 891 rtw_read32(rtwdev, REG_IQK_RES_RX), 892 rtw_read32(rtwdev, REG_IQK_RES_RY)); 893 894 rtw_dbg(rtwdev, RTW_DBG_RFK, 895 "[IQK] 0xea0(before IQK)= 0x%x, 0xea8(afer IQK) = 0x%x\n", 896 rtw_read32(rtwdev, 0xea0), 897 rtw_read32(rtwdev, 0xea8)); 898 899 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL); 900 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 901 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 902 rx_y = abs(iqkxy_to_s32(rx_y)); 903 904 if (!rx_fail && rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER && 905 rx_y < IQK_RX_Y_LMT) 906 return IQK_RX_OK; 907 908 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] %s RXIQK STEP2 is failed\n", 909 iqk_cfg->name); 910 911 return 0; 912 } 913 914 static void rtw8723d_iqk_one_shot(struct rtw_dev *rtwdev, bool tx, 915 const struct rtw_8723d_iqk_cfg *iqk_cfg) 916 { 917 u32 pts = (tx ? iqk_cfg->val_iqkpts : 0xf9000000); 918 919 /* enter IQK mode */ 920 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 921 rtw8723d_iqk_config_lte_path_gnt(rtwdev); 922 923 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0054); 924 mdelay(1); 925 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] GNT_BT @%s %sIQK1 = 0x%x\n", 926 iqk_cfg->name, tx ? "TX" : "RX", 927 rtw_read32(rtwdev, REG_LTECOEX_READ_DATA)); 928 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x948 @%s %sIQK1 = 0x%x\n", 929 iqk_cfg->name, tx ? "TX" : "RX", 930 rtw_read32(rtwdev, REG_BB_SEL_BTG)); 931 932 /* One shot, LOK & IQK */ 933 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, pts); 934 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000); 935 936 if (!check_hw_ready(rtwdev, REG_IQK_RES_RY, BIT_IQK_DONE, 1)) 937 rtw_warn(rtwdev, "%s %s IQK isn't done\n", iqk_cfg->name, 938 tx ? "TX" : "RX"); 939 } 940 941 static void rtw8723d_iqk_txrx_path_post(struct rtw_dev *rtwdev, 942 const struct rtw_8723d_iqk_cfg *iqk_cfg, 943 const struct iqk_backup_regs *backup) 944 { 945 rtw8723d_iqk_restore_lte_path_gnt(rtwdev, backup); 946 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); 947 948 /* leave IQK mode */ 949 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 950 mdelay(1); 951 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x0); 952 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, BIT(0), 0x0); 953 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, BIT(0), 0x0); 954 } 955 956 static u8 rtw8723d_iqk_tx_path(struct rtw_dev *rtwdev, 957 const struct rtw_8723d_iqk_cfg *iqk_cfg, 958 const struct iqk_backup_regs *backup) 959 { 960 u8 status; 961 962 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s TXIQK!!\n", iqk_cfg->name); 963 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s TXIQK = 0x%x\n", 964 iqk_cfg->name, 965 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 966 967 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); 968 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 969 mdelay(1); 970 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); 971 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00004); 972 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005d); 973 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xBFFE0); 974 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 975 976 /* IQK setting */ 977 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x08008c0c); 978 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 979 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, iqk_cfg->val_txiqk_pi); 980 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160200); 981 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 982 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 983 984 /* LOK setting */ 985 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911); 986 987 /* PA, PAD setting */ 988 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); 989 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); 990 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x1E0, 0x3); 991 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXIQGEN, 0x1F, 0xf); 992 993 /* LOK setting for 8723D */ 994 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x10, 0x1); 995 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_bspad, 0x1, 0x1); 996 997 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); 998 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); 999 1000 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s TXIQK = 0x%x\n", 1001 iqk_cfg->name, 1002 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 1003 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s TXIQK = 0x%x\n", 1004 iqk_cfg->name, 1005 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 1006 1007 rtw8723d_iqk_one_shot(rtwdev, true, iqk_cfg); 1008 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg); 1009 1010 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup); 1011 1012 return status; 1013 } 1014 1015 static u8 rtw8723d_iqk_rx_path(struct rtw_dev *rtwdev, 1016 const struct rtw_8723d_iqk_cfg *iqk_cfg, 1017 const struct iqk_backup_regs *backup) 1018 { 1019 u32 tx_x, tx_y; 1020 u8 status; 1021 1022 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK Step1!!\n", 1023 iqk_cfg->name); 1024 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK1 = 0x%x\n", 1025 iqk_cfg->name, 1026 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1027 rtw_write32(rtwdev, REG_BB_SEL_BTG, iqk_cfg->val_bb_sel_btg); 1028 1029 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1030 1031 /* IQK setting */ 1032 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1033 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1034 1035 /* path IQK setting */ 1036 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 1037 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 1038 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1039 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1040 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82160000); 1041 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160000); 1042 1043 /* LOK setting */ 1044 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911); 1045 1046 /* RXIQK mode */ 1047 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x80000); 1048 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00006); 1049 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); 1050 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xa7ffb); 1051 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 1052 1053 /* PA/PAD=0 */ 1054 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_padlut, 0x800, 0x1); 1055 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_gaintx, 0x600, 0x0); 1056 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, iqk_cfg->val_wlint); 1057 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK, iqk_cfg->val_wlsel); 1058 1059 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1@ path %s RXIQK1 = 0x%x\n", 1060 iqk_cfg->name, 1061 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 1062 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2@ path %s RXIQK1 = 0x%x\n", 1063 iqk_cfg->name, 1064 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 1065 1066 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg); 1067 status = rtw8723d_iqk_check_tx_failed(rtwdev, iqk_cfg); 1068 1069 if (!status) 1070 goto restore; 1071 1072 /* second round */ 1073 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1074 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1075 1076 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y)); 1077 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", 1078 rtw_read32(rtwdev, REG_TXIQK_11N), 1079 BIT_SET_TXIQK_11N(tx_x, tx_y)); 1080 1081 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path %s RXIQK STEP2!!\n", 1082 iqk_cfg->name); 1083 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @%s RXIQK2 = 0x%x\n", 1084 iqk_cfg->name, 1085 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1086 1087 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1088 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c); 1089 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c); 1090 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1091 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1092 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82170000); 1093 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28171400); 1094 1095 /* LOK setting */ 1096 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1); 1097 1098 /* RXIQK mode */ 1099 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1100 mdelay(1); 1101 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, 0x80000, 0x1); 1102 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00007); 1103 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x0005f); 1104 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0xb3fdb); 1105 rtw_write_rf(rtwdev, RF_PATH_A, iqk_cfg->reg_lutwe, RFREG_MASK, 0x00000); 1106 1107 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x1 @%s RXIQK2 = 0x%x\n", 1108 iqk_cfg->name, 1109 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK)); 1110 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] RF0x2 @%s RXIQK2 = 0x%x\n", 1111 iqk_cfg->name, 1112 rtw_read_rf(rtwdev, RF_PATH_A, RF_WLSEL, RFREG_MASK)); 1113 1114 rtw8723d_iqk_one_shot(rtwdev, false, iqk_cfg); 1115 status |= rtw8723d_iqk_check_rx_failed(rtwdev, iqk_cfg); 1116 1117 restore: 1118 rtw8723d_iqk_txrx_path_post(rtwdev, iqk_cfg, backup); 1119 1120 return status; 1121 } 1122 1123 static 1124 void rtw8723d_iqk_fill_s1_matrix(struct rtw_dev *rtwdev, const s32 result[]) 1125 { 1126 s32 oldval_1; 1127 s32 x, y; 1128 s32 tx1_a, tx1_a_ext; 1129 s32 tx1_c, tx1_c_ext; 1130 1131 if (result[IQK_S1_TX_X] == 0) 1132 return; 1133 1134 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1135 BIT_MASK_TXIQ_ELM_D); 1136 1137 x = iqkxy_to_s32(result[IQK_S1_TX_X]); 1138 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext); 1139 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1140 BIT_MASK_TXIQ_ELM_A, tx1_a); 1141 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1142 BIT_MASK_OFDM0_EXT_A, tx1_a_ext); 1143 1144 y = iqkxy_to_s32(result[IQK_S1_TX_Y]); 1145 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext); 1146 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1147 BIT_SET_TXIQ_ELM_C1(tx1_c)); 1148 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1149 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c)); 1150 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1151 BIT_MASK_OFDM0_EXT_C, tx1_c_ext); 1152 1153 rtw_dbg(rtwdev, RTW_DBG_RFK, 1154 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", 1155 x, tx1_a, oldval_1); 1156 rtw_dbg(rtwdev, RTW_DBG_RFK, 1157 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c); 1158 1159 if (result[IQK_S1_RX_X] == 0) 1160 return; 1161 1162 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_X, 1163 result[IQK_S1_RX_X]); 1164 rtw_write32_mask(rtwdev, REG_A_RXIQI, BIT_MASK_RXIQ_S1_Y1, 1165 BIT_SET_RXIQ_S1_Y1(result[IQK_S1_RX_Y])); 1166 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2, 1167 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y])); 1168 } 1169 1170 static 1171 void rtw8723d_iqk_fill_s0_matrix(struct rtw_dev *rtwdev, const s32 result[]) 1172 { 1173 s32 oldval_0; 1174 s32 x, y; 1175 s32 tx0_a, tx0_a_ext; 1176 s32 tx0_c, tx0_c_ext; 1177 1178 if (result[IQK_S0_TX_X] == 0) 1179 return; 1180 1181 oldval_0 = rtw_read32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0); 1182 1183 x = iqkxy_to_s32(result[IQK_S0_TX_X]); 1184 tx0_a = iqk_mult(x, oldval_0, &tx0_a_ext); 1185 1186 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, tx0_a); 1187 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, tx0_a_ext); 1188 1189 y = iqkxy_to_s32(result[IQK_S0_TX_Y]); 1190 tx0_c = iqk_mult(y, oldval_0, &tx0_c_ext); 1191 1192 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, tx0_c); 1193 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, tx0_c_ext); 1194 1195 if (result[IQK_S0_RX_X] == 0) 1196 return; 1197 1198 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_X_S0, 1199 result[IQK_S0_RX_X]); 1200 rtw_write32_mask(rtwdev, REG_RXIQ_AB_S0, BIT_MASK_RXIQ_Y_S0, 1201 result[IQK_S0_RX_Y]); 1202 } 1203 1204 static void rtw8723d_iqk_path_adda_on(struct rtw_dev *rtwdev) 1205 { 1206 int i; 1207 1208 for (i = 0; i < IQK_ADDA_REG_NUM; i++) 1209 rtw_write32(rtwdev, iqk_adda_regs[i], 0x03c00016); 1210 } 1211 1212 static void rtw8723d_iqk_config_mac(struct rtw_dev *rtwdev) 1213 { 1214 rtw_write8(rtwdev, REG_TXPAUSE, 0xff); 1215 } 1216 1217 static 1218 void rtw8723d_iqk_rf_standby(struct rtw_dev *rtwdev, enum rtw_rf_path path) 1219 { 1220 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path-%s standby mode!\n", 1221 path == RF_PATH_A ? "S1" : "S0"); 1222 1223 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1224 mdelay(1); 1225 rtw_write_rf(rtwdev, path, RF_MODE, RFREG_MASK, 0x10000); 1226 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 1227 } 1228 1229 static 1230 bool rtw8723d_iqk_similarity_cmp(struct rtw_dev *rtwdev, s32 result[][IQK_NR], 1231 u8 c1, u8 c2) 1232 { 1233 u32 i, j, diff; 1234 u32 bitmap = 0; 1235 u8 candidate[PATH_NR] = {IQK_ROUND_INVALID, IQK_ROUND_INVALID}; 1236 bool ret = true; 1237 1238 s32 tmp1, tmp2; 1239 1240 for (i = 0; i < IQK_NR; i++) { 1241 tmp1 = iqkxy_to_s32(result[c1][i]); 1242 tmp2 = iqkxy_to_s32(result[c2][i]); 1243 1244 diff = abs(tmp1 - tmp2); 1245 1246 if (diff <= MAX_TOLERANCE) 1247 continue; 1248 1249 if ((i == IQK_S1_RX_X || i == IQK_S0_RX_X) && !bitmap) { 1250 if (result[c1][i] + result[c1][i + 1] == 0) 1251 candidate[i / IQK_SX_NR] = c2; 1252 else if (result[c2][i] + result[c2][i + 1] == 0) 1253 candidate[i / IQK_SX_NR] = c1; 1254 else 1255 bitmap |= BIT(i); 1256 } else { 1257 bitmap |= BIT(i); 1258 } 1259 } 1260 1261 if (bitmap != 0) 1262 goto check_sim; 1263 1264 for (i = 0; i < PATH_NR; i++) { 1265 if (candidate[i] == IQK_ROUND_INVALID) 1266 continue; 1267 1268 for (j = i * IQK_SX_NR; j < i * IQK_SX_NR + 2; j++) 1269 result[IQK_ROUND_HYBRID][j] = result[candidate[i]][j]; 1270 ret = false; 1271 } 1272 1273 return ret; 1274 1275 check_sim: 1276 for (i = 0; i < IQK_NR; i++) { 1277 j = i & ~1; /* 2 bits are a pair for IQ[X, Y] */ 1278 if (bitmap & GENMASK(j + 1, j)) 1279 continue; 1280 1281 result[IQK_ROUND_HYBRID][i] = result[c1][i]; 1282 } 1283 1284 return false; 1285 } 1286 1287 static 1288 void rtw8723d_iqk_precfg_path(struct rtw_dev *rtwdev, enum rtw8723d_path path) 1289 { 1290 if (path == PATH_S0) { 1291 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_A); 1292 rtw8723d_iqk_path_adda_on(rtwdev); 1293 } 1294 1295 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 1296 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1297 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1298 1299 if (path == PATH_S1) { 1300 rtw8723d_iqk_rf_standby(rtwdev, RF_PATH_B); 1301 rtw8723d_iqk_path_adda_on(rtwdev); 1302 } 1303 } 1304 1305 static 1306 void rtw8723d_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, 1307 const struct iqk_backup_regs *backup) 1308 { 1309 u32 i; 1310 u8 s1_ok, s0_ok; 1311 1312 rtw_dbg(rtwdev, RTW_DBG_RFK, 1313 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t); 1314 1315 rtw8723d_iqk_path_adda_on(rtwdev); 1316 rtw8723d_iqk_config_mac(rtwdev); 1317 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); 1318 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05611); 1319 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4); 1320 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204200); 1321 rtw8723d_iqk_precfg_path(rtwdev, PATH_S1); 1322 1323 for (i = 0; i < PATH_IQK_RETRY; i++) { 1324 s1_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup); 1325 if (s1_ok == IQK_TX_OK) { 1326 rtw_dbg(rtwdev, RTW_DBG_RFK, 1327 "[IQK] path S1 Tx IQK Success!!\n"); 1328 result[t][IQK_S1_TX_X] = 1329 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1330 result[t][IQK_S1_TX_Y] = 1331 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1332 break; 1333 } 1334 1335 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Tx IQK Fail!!\n"); 1336 result[t][IQK_S1_TX_X] = 0x100; 1337 result[t][IQK_S1_TX_Y] = 0x0; 1338 } 1339 1340 for (i = 0; i < PATH_IQK_RETRY; i++) { 1341 s1_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S1], backup); 1342 if (s1_ok == (IQK_TX_OK | IQK_RX_OK)) { 1343 rtw_dbg(rtwdev, RTW_DBG_RFK, 1344 "[IQK] path S1 Rx IQK Success!!\n"); 1345 result[t][IQK_S1_RX_X] = 1346 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 1347 result[t][IQK_S1_RX_Y] = 1348 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 1349 break; 1350 } 1351 1352 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 Rx IQK Fail!!\n"); 1353 result[t][IQK_S1_RX_X] = 0x100; 1354 result[t][IQK_S1_RX_Y] = 0x0; 1355 } 1356 1357 if (s1_ok == 0x0) 1358 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S1 IQK is failed!!\n"); 1359 1360 rtw8723d_iqk_precfg_path(rtwdev, PATH_S0); 1361 1362 for (i = 0; i < PATH_IQK_RETRY; i++) { 1363 s0_ok = rtw8723d_iqk_tx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup); 1364 if (s0_ok == IQK_TX_OK) { 1365 rtw_dbg(rtwdev, RTW_DBG_RFK, 1366 "[IQK] path S0 Tx IQK Success!!\n"); 1367 result[t][IQK_S0_TX_X] = 1368 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1369 result[t][IQK_S0_TX_Y] = 1370 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1371 break; 1372 } 1373 1374 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Tx IQK Fail!!\n"); 1375 result[t][IQK_S0_TX_X] = 0x100; 1376 result[t][IQK_S0_TX_Y] = 0x0; 1377 } 1378 1379 for (i = 0; i < PATH_IQK_RETRY; i++) { 1380 s0_ok = rtw8723d_iqk_rx_path(rtwdev, &iqk_tx_cfg[PATH_S0], backup); 1381 if (s0_ok == (IQK_TX_OK | IQK_RX_OK)) { 1382 rtw_dbg(rtwdev, RTW_DBG_RFK, 1383 "[IQK] path S0 Rx IQK Success!!\n"); 1384 1385 result[t][IQK_S0_RX_X] = 1386 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 1387 result[t][IQK_S0_RX_Y] = 1388 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 1389 break; 1390 } 1391 1392 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 Rx IQK Fail!!\n"); 1393 result[t][IQK_S0_RX_X] = 0x100; 1394 result[t][IQK_S0_RX_Y] = 0x0; 1395 } 1396 1397 if (s0_ok == 0x0) 1398 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path S0 IQK is failed!!\n"); 1399 1400 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1401 mdelay(1); 1402 1403 rtw_dbg(rtwdev, RTW_DBG_RFK, 1404 "[IQK] back to BB mode, load original value!\n"); 1405 } 1406 1407 static void rtw8723d_phy_calibration(struct rtw_dev *rtwdev) 1408 { 1409 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1410 s32 result[IQK_ROUND_SIZE][IQK_NR]; 1411 struct iqk_backup_regs backup; 1412 u8 i, j; 1413 u8 final_candidate = IQK_ROUND_INVALID; 1414 bool good; 1415 1416 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!!!\n"); 1417 1418 memset(result, 0, sizeof(result)); 1419 1420 rtw8723d_iqk_backup_path_ctrl(rtwdev, &backup); 1421 rtw8723d_iqk_backup_lte_path_gnt(rtwdev, &backup); 1422 rtw8723d_iqk_backup_regs(rtwdev, &backup); 1423 1424 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) { 1425 rtw8723d_iqk_config_path_ctrl(rtwdev); 1426 rtw8723d_iqk_config_lte_path_gnt(rtwdev); 1427 1428 rtw8723d_iqk_one_round(rtwdev, result, i, &backup); 1429 1430 if (i > IQK_ROUND_0) 1431 rtw8723d_iqk_restore_regs(rtwdev, &backup); 1432 rtw8723d_iqk_restore_lte_path_gnt(rtwdev, &backup); 1433 rtw8723d_iqk_restore_path_ctrl(rtwdev, &backup); 1434 1435 for (j = IQK_ROUND_0; j < i; j++) { 1436 good = rtw8723d_iqk_similarity_cmp(rtwdev, result, j, i); 1437 1438 if (good) { 1439 final_candidate = j; 1440 rtw_dbg(rtwdev, RTW_DBG_RFK, 1441 "[IQK] cmp %d:%d final_candidate is %x\n", 1442 j, i, final_candidate); 1443 goto iqk_done; 1444 } 1445 } 1446 } 1447 1448 if (final_candidate == IQK_ROUND_INVALID) { 1449 s32 reg_tmp = 0; 1450 1451 for (i = 0; i < IQK_NR; i++) 1452 reg_tmp += result[IQK_ROUND_HYBRID][i]; 1453 1454 if (reg_tmp != 0) { 1455 final_candidate = IQK_ROUND_HYBRID; 1456 } else { 1457 WARN(1, "IQK is failed\n"); 1458 goto out; 1459 } 1460 } 1461 1462 iqk_done: 1463 rtw8723d_iqk_fill_s1_matrix(rtwdev, result[final_candidate]); 1464 rtw8723d_iqk_fill_s0_matrix(rtwdev, result[final_candidate]); 1465 1466 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X]; 1467 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y]; 1468 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X]; 1469 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y]; 1470 dm_info->iqk.done = true; 1471 1472 out: 1473 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg); 1474 1475 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n", 1476 final_candidate); 1477 1478 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++) 1479 rtw_dbg(rtwdev, RTW_DBG_RFK, 1480 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n", 1481 i, 1482 result[i][0], result[i][1], result[i][2], result[i][3], 1483 result[i][4], result[i][5], result[i][6], result[i][7], 1484 final_candidate == i ? "(final candidate)" : ""); 1485 1486 rtw_dbg(rtwdev, RTW_DBG_RFK, 1487 "[IQK]0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", 1488 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE), 1489 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N), 1490 rtw_read32(rtwdev, REG_A_RXIQI), 1491 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N)); 1492 rtw_dbg(rtwdev, RTW_DBG_RFK, 1493 "[IQK]0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", 1494 rtw_read32(rtwdev, REG_TXIQ_AB_S0), 1495 rtw_read32(rtwdev, REG_TXIQ_CD_S0), 1496 rtw_read32(rtwdev, REG_RXIQ_AB_S0)); 1497 1498 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] finished\n"); 1499 } 1500 1501 /* for coex */ 1502 static void rtw8723d_coex_cfg_init(struct rtw_dev *rtwdev) 1503 { 1504 /* enable TBTT nterrupt */ 1505 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1506 1507 /* BT report packet sample rate */ 1508 /* 0x790[5:0]=0x5 */ 1509 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); 1510 1511 /* enable BT counter statistics */ 1512 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 1513 1514 /* enable PTA (3-wire function form BT side) */ 1515 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 1516 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); 1517 1518 /* enable PTA (tx/rx signal form WiFi side) */ 1519 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 1520 } 1521 1522 static void rtw8723d_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1523 { 1524 } 1525 1526 static void rtw8723d_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1527 { 1528 rtw_write8_mask(rtwdev, REG_LEDCFG2, BIT(6), 0); 1529 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(0), 0); 1530 rtw_write8_mask(rtwdev, REG_GPIO_INTM + 2, BIT(4), 0); 1531 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT(1), 0); 1532 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT(1), 0); 1533 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT(7), 0); 1534 rtw_write8_mask(rtwdev, REG_SYS_CLKR + 1, BIT(1), 0); 1535 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT(3), 0); 1536 } 1537 1538 static void rtw8723d_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1539 { 1540 struct rtw_efuse *efuse = &rtwdev->efuse; 1541 struct rtw_coex *coex = &rtwdev->coex; 1542 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1543 bool aux = efuse->bt_setting & BIT(6); 1544 1545 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1546 coex_rfe->ant_switch_polarity = 0; 1547 coex_rfe->ant_switch_exist = false; 1548 coex_rfe->ant_switch_with_bt = false; 1549 coex_rfe->ant_switch_diversity = false; 1550 coex_rfe->wlg_at_btg = true; 1551 1552 /* decide antenna at main or aux */ 1553 if (efuse->share_ant) { 1554 if (aux) 1555 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x80); 1556 else 1557 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x200); 1558 } else { 1559 if (aux) 1560 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x280); 1561 else 1562 rtw_write16(rtwdev, REG_BB_SEL_BTG, 0x0); 1563 } 1564 1565 /* disable LTE coex in wifi side */ 1566 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 1567 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1568 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1569 } 1570 1571 static void rtw8723d_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1572 { 1573 struct rtw_coex *coex = &rtwdev->coex; 1574 struct rtw_coex_dm *coex_dm = &coex->dm; 1575 static const u8 wl_tx_power[] = {0xb2, 0x90}; 1576 u8 pwr; 1577 1578 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 1579 return; 1580 1581 coex_dm->cur_wl_pwr_lvl = wl_pwr; 1582 1583 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) 1584 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; 1585 1586 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; 1587 1588 rtw_write8(rtwdev, REG_ANA_PARAM1 + 3, pwr); 1589 } 1590 1591 static void rtw8723d_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1592 { 1593 struct rtw_coex *coex = &rtwdev->coex; 1594 struct rtw_coex_dm *coex_dm = &coex->dm; 1595 /* WL Rx Low gain on */ 1596 static const u32 wl_rx_low_gain_on[] = { 1597 0xec120101, 0xeb130101, 0xce140101, 0xcd150101, 0xcc160101, 1598 0xcb170101, 0xca180101, 0x8d190101, 0x8c1a0101, 0x8b1b0101, 1599 0x4f1c0101, 0x4e1d0101, 0x4d1e0101, 0x4c1f0101, 0x0e200101, 1600 0x0d210101, 0x0c220101, 0x0b230101, 0xcf240001, 0xce250001, 1601 0xcd260001, 0xcc270001, 0x8f280001 1602 }; 1603 /* WL Rx Low gain off */ 1604 static const u32 wl_rx_low_gain_off[] = { 1605 0xec120101, 0xeb130101, 0xea140101, 0xe9150101, 0xe8160101, 1606 0xe7170101, 0xe6180101, 0xe5190101, 0xe41a0101, 0xe31b0101, 1607 0xe21c0101, 0xe11d0101, 0xe01e0101, 0x861f0101, 0x85200101, 1608 0x84210101, 0x83220101, 0x82230101, 0x81240101, 0x80250101, 1609 0x44260101, 0x43270101, 0x42280101 1610 }; 1611 u8 i; 1612 1613 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 1614 return; 1615 1616 coex_dm->cur_wl_rx_low_gain_en = low_gain; 1617 1618 if (coex_dm->cur_wl_rx_low_gain_en) { 1619 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) 1620 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_on[i]); 1621 } else { 1622 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) 1623 rtw_write32(rtwdev, REG_AGCRSSI, wl_rx_low_gain_off[i]); 1624 } 1625 } 1626 1627 static u8 rtw8723d_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev) 1628 { 1629 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1630 u8 tx_rate = dm_info->tx_rate; 1631 u8 limit_ofdm = 30; 1632 1633 switch (tx_rate) { 1634 case DESC_RATE1M...DESC_RATE5_5M: 1635 case DESC_RATE11M: 1636 break; 1637 case DESC_RATE6M...DESC_RATE48M: 1638 limit_ofdm = 36; 1639 break; 1640 case DESC_RATE54M: 1641 limit_ofdm = 34; 1642 break; 1643 case DESC_RATEMCS0...DESC_RATEMCS2: 1644 limit_ofdm = 38; 1645 break; 1646 case DESC_RATEMCS3...DESC_RATEMCS4: 1647 limit_ofdm = 36; 1648 break; 1649 case DESC_RATEMCS5...DESC_RATEMCS7: 1650 limit_ofdm = 34; 1651 break; 1652 default: 1653 rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate); 1654 break; 1655 } 1656 1657 return limit_ofdm; 1658 } 1659 1660 static void rtw8723d_set_iqk_matrix_by_result(struct rtw_dev *rtwdev, 1661 u32 ofdm_swing, u8 rf_path) 1662 { 1663 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1664 s32 ele_A, ele_D, ele_C; 1665 s32 ele_A_ext, ele_C_ext, ele_D_ext; 1666 s32 iqk_result_x; 1667 s32 iqk_result_y; 1668 s32 value32; 1669 1670 switch (rf_path) { 1671 default: 1672 case RF_PATH_A: 1673 iqk_result_x = dm_info->iqk.result.s1_x; 1674 iqk_result_y = dm_info->iqk.result.s1_y; 1675 break; 1676 case RF_PATH_B: 1677 iqk_result_x = dm_info->iqk.result.s0_x; 1678 iqk_result_y = dm_info->iqk.result.s0_y; 1679 break; 1680 } 1681 1682 /* new element D */ 1683 ele_D = OFDM_SWING_D(ofdm_swing); 1684 iqk_mult(iqk_result_x, ele_D, &ele_D_ext); 1685 /* new element A */ 1686 iqk_result_x = iqkxy_to_s32(iqk_result_x); 1687 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext); 1688 /* new element C */ 1689 iqk_result_y = iqkxy_to_s32(iqk_result_y); 1690 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext); 1691 1692 switch (rf_path) { 1693 case RF_PATH_A: 1694 default: 1695 /* write new elements A, C, D, and element B is always 0 */ 1696 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1697 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32); 1698 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1699 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1700 value32); 1701 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1702 value32 &= ~BIT_MASK_OFDM0_EXTS; 1703 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext); 1704 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1705 break; 1706 1707 case RF_PATH_B: 1708 /* write new elements A, C, D, and element B is always 0 */ 1709 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, ele_D); 1710 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, ele_C); 1711 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, ele_A); 1712 1713 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 1714 ele_D_ext); 1715 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 1716 ele_A_ext); 1717 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 1718 ele_C_ext); 1719 break; 1720 } 1721 } 1722 1723 static void rtw8723d_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index, 1724 u8 rf_path) 1725 { 1726 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1727 s32 value32; 1728 u32 ofdm_swing; 1729 1730 if (ofdm_index >= RTW_OFDM_SWING_TABLE_SIZE) 1731 ofdm_index = RTW_OFDM_SWING_TABLE_SIZE - 1; 1732 else if (ofdm_index < 0) 1733 ofdm_index = 0; 1734 1735 ofdm_swing = rtw8723d_ofdm_swing_table[ofdm_index]; 1736 1737 if (dm_info->iqk.done) { 1738 rtw8723d_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path); 1739 return; 1740 } 1741 1742 switch (rf_path) { 1743 case RF_PATH_A: 1744 default: 1745 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing); 1746 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1747 0x00); 1748 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1749 value32 &= ~BIT_MASK_OFDM0_EXTS; 1750 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1751 break; 1752 1753 case RF_PATH_B: 1754 /* image S1:c80 to S0:Cd0 and Cd4 */ 1755 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_S0, 1756 OFDM_SWING_A(ofdm_swing)); 1757 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_B_S0, 1758 OFDM_SWING_B(ofdm_swing)); 1759 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_S0, 1760 OFDM_SWING_C(ofdm_swing)); 1761 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_S0, 1762 OFDM_SWING_D(ofdm_swing)); 1763 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_D_EXT_S0, 0x0); 1764 rtw_write32_mask(rtwdev, REG_TXIQ_CD_S0, BIT_MASK_TXIQ_C_EXT_S0, 0x0); 1765 rtw_write32_mask(rtwdev, REG_TXIQ_AB_S0, BIT_MASK_TXIQ_A_EXT_S0, 0x0); 1766 break; 1767 } 1768 } 1769 1770 static void rtw8723d_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1771 s8 txagc_idx) 1772 { 1773 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1774 1775 dm_info->txagc_remnant_ofdm = txagc_idx; 1776 1777 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A); 1778 rtw8723d_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_B); 1779 } 1780 1781 static void rtw8723d_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1782 s8 txagc_idx) 1783 { 1784 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1785 1786 dm_info->txagc_remnant_cck = txagc_idx; 1787 1788 rtw_write32_mask(rtwdev, 0xab4, 0x000007FF, 1789 rtw8723d_cck_swing_table[swing_idx]); 1790 } 1791 1792 static void rtw8723d_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1793 { 1794 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1795 struct rtw_hal *hal = &rtwdev->hal; 1796 u8 limit_ofdm; 1797 u8 limit_cck = 40; 1798 s8 final_ofdm_swing_index; 1799 s8 final_cck_swing_index; 1800 1801 limit_ofdm = rtw8723d_pwrtrack_get_limit_ofdm(rtwdev); 1802 1803 final_ofdm_swing_index = RTW_DEF_OFDM_SWING_INDEX + 1804 dm_info->delta_power_index[path]; 1805 final_cck_swing_index = RTW_DEF_CCK_SWING_INDEX + 1806 dm_info->delta_power_index[path]; 1807 1808 if (final_ofdm_swing_index > limit_ofdm) 1809 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm, 1810 final_ofdm_swing_index - limit_ofdm); 1811 else if (final_ofdm_swing_index < 0) 1812 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, 0, 1813 final_ofdm_swing_index); 1814 else 1815 rtw8723d_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0); 1816 1817 if (final_cck_swing_index > limit_cck) 1818 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, limit_cck, 1819 final_cck_swing_index - limit_cck); 1820 else if (final_cck_swing_index < 0) 1821 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, 0, 1822 final_cck_swing_index); 1823 else 1824 rtw8723d_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0); 1825 1826 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); 1827 } 1828 1829 static void rtw8723d_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path, 1830 u8 delta) 1831 { 1832 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1833 const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl; 1834 const s8 *pwrtrk_xtal; 1835 s8 xtal_cap; 1836 1837 if (dm_info->thermal_avg[therm_path] > 1838 rtwdev->efuse.thermal_meter[therm_path]) 1839 pwrtrk_xtal = tbl->pwrtrk_xtal_p; 1840 else 1841 pwrtrk_xtal = tbl->pwrtrk_xtal_n; 1842 1843 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 1844 xtal_cap = clamp_t(s8, xtal_cap + pwrtrk_xtal[delta], 0, 0x3F); 1845 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 1846 xtal_cap | (xtal_cap << 6)); 1847 } 1848 1849 static void rtw8723d_phy_pwrtrack(struct rtw_dev *rtwdev) 1850 { 1851 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1852 struct rtw_swing_table swing_table; 1853 u8 thermal_value, delta, path; 1854 bool do_iqk = false; 1855 1856 rtw_phy_config_swing_table(rtwdev, &swing_table); 1857 1858 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1859 return; 1860 1861 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1862 1863 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1864 1865 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev); 1866 1867 if (do_iqk) 1868 rtw8723d_lck(rtwdev); 1869 1870 if (dm_info->pwr_trk_init_trigger) 1871 dm_info->pwr_trk_init_trigger = false; 1872 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1873 RF_PATH_A)) 1874 goto iqk; 1875 1876 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1877 1878 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1879 1880 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1881 s8 delta_cur, delta_last; 1882 1883 delta_last = dm_info->delta_power_index[path]; 1884 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, 1885 path, RF_PATH_A, delta); 1886 if (delta_last == delta_cur) 1887 continue; 1888 1889 dm_info->delta_power_index[path] = delta_cur; 1890 rtw8723d_pwrtrack_set(rtwdev, path); 1891 } 1892 1893 rtw8723d_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); 1894 1895 iqk: 1896 if (do_iqk) 1897 rtw8723d_phy_calibration(rtwdev); 1898 } 1899 1900 static void rtw8723d_pwr_track(struct rtw_dev *rtwdev) 1901 { 1902 struct rtw_efuse *efuse = &rtwdev->efuse; 1903 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1904 1905 if (efuse->power_track_type != 0) 1906 return; 1907 1908 if (!dm_info->pwr_trk_triggered) { 1909 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1910 GENMASK(17, 16), 0x03); 1911 dm_info->pwr_trk_triggered = true; 1912 return; 1913 } 1914 1915 rtw8723d_phy_pwrtrack(rtwdev); 1916 dm_info->pwr_trk_triggered = false; 1917 } 1918 1919 static struct rtw_chip_ops rtw8723d_ops = { 1920 .phy_set_param = rtw8723d_phy_set_param, 1921 .read_efuse = rtw8723d_read_efuse, 1922 .query_rx_desc = rtw8723d_query_rx_desc, 1923 .set_channel = rtw8723d_set_channel, 1924 .mac_init = rtw8723d_mac_init, 1925 .shutdown = rtw8723d_shutdown, 1926 .read_rf = rtw_phy_read_rf_sipi, 1927 .write_rf = rtw_phy_write_rf_reg_sipi, 1928 .set_tx_power_index = rtw8723d_set_tx_power_index, 1929 .set_antenna = NULL, 1930 .cfg_ldo25 = rtw8723d_cfg_ldo25, 1931 .efuse_grant = rtw8723d_efuse_grant, 1932 .false_alarm_statistics = rtw8723d_false_alarm_statistics, 1933 .phy_calibration = rtw8723d_phy_calibration, 1934 .pwr_track = rtw8723d_pwr_track, 1935 .config_bfee = NULL, 1936 .set_gid_table = NULL, 1937 .cfg_csi_rate = NULL, 1938 1939 .coex_set_init = rtw8723d_coex_cfg_init, 1940 .coex_set_ant_switch = NULL, 1941 .coex_set_gnt_fix = rtw8723d_coex_cfg_gnt_fix, 1942 .coex_set_gnt_debug = rtw8723d_coex_cfg_gnt_debug, 1943 .coex_set_rfe_type = rtw8723d_coex_cfg_rfe_type, 1944 .coex_set_wl_tx_power = rtw8723d_coex_cfg_wl_tx_power, 1945 .coex_set_wl_rx_gain = rtw8723d_coex_cfg_wl_rx_gain, 1946 }; 1947 1948 /* Shared-Antenna Coex Table */ 1949 static const struct coex_table_para table_sant_8723d[] = { 1950 {0xffffffff, 0xffffffff}, /* case-0 */ 1951 {0x55555555, 0x55555555}, 1952 {0x65555555, 0x65555555}, 1953 {0xaaaaaaaa, 0xaaaaaaaa}, 1954 {0x5a5a5a5a, 0x5a5a5a5a}, 1955 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1956 {0xa5555555, 0xaaaa5aaa}, 1957 {0x6a5a5a5a, 0x5a5a5a5a}, 1958 {0x6a5a5a5a, 0x6a5a5a5a}, 1959 {0x65555555, 0x5a5a5a5a}, 1960 {0x65555555, 0x6a5a5a5a}, /* case-10 */ 1961 {0x65555555, 0xfafafafa}, 1962 {0x65555555, 0x6a5a5aaa}, 1963 {0x65555555, 0x5aaa5aaa}, 1964 {0x65555555, 0xaaaa5aaa}, 1965 {0x65555555, 0xaaaaaaaa}, /* case-15 */ 1966 {0xffff55ff, 0xfafafafa}, 1967 {0xffff55ff, 0x6afa5afa}, 1968 {0xaaffffaa, 0xfafafafa}, 1969 {0xaa5555aa, 0x5a5a5a5a}, 1970 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1971 {0xaa5555aa, 0xaaaaaaaa}, 1972 {0xffffffff, 0x5a5a5a5a}, 1973 {0xffffffff, 0x6a5a5a5a}, 1974 {0xffffffff, 0x55555555}, 1975 {0xffffffff, 0x6a5a5aaa}, /* case-25 */ 1976 {0x55555555, 0x5a5a5a5a}, 1977 {0x55555555, 0xaaaaaaaa}, 1978 {0x55555555, 0x6a6a6a6a}, 1979 {0x656a656a, 0x656a656a} 1980 }; 1981 1982 /* Non-Shared-Antenna Coex Table */ 1983 static const struct coex_table_para table_nsant_8723d[] = { 1984 {0xffffffff, 0xffffffff}, /* case-100 */ 1985 {0x55555555, 0x55555555}, 1986 {0x65555555, 0x65555555}, 1987 {0xaaaaaaaa, 0xaaaaaaaa}, 1988 {0x5a5a5a5a, 0x5a5a5a5a}, 1989 {0xfafafafa, 0xfafafafa}, /* case-105 */ 1990 {0x5afa5afa, 0x5afa5afa}, 1991 {0x55555555, 0xfafafafa}, 1992 {0x65555555, 0xfafafafa}, 1993 {0x65555555, 0x5a5a5a5a}, 1994 {0x65555555, 0x6a5a5a5a}, /* case-110 */ 1995 {0x65555555, 0xaaaaaaaa}, 1996 {0xffff55ff, 0xfafafafa}, 1997 {0xffff55ff, 0x5afa5afa}, 1998 {0xffff55ff, 0xaaaaaaaa}, 1999 {0xaaffffaa, 0xfafafafa}, /* case-115 */ 2000 {0xaaffffaa, 0x5afa5afa}, 2001 {0xaaffffaa, 0xaaaaaaaa}, 2002 {0xffffffff, 0xfafafafa}, 2003 {0xffffffff, 0x5afa5afa}, 2004 {0xffffffff, 0xaaaaaaaa},/* case-120 */ 2005 {0x55ff55ff, 0x5afa5afa}, 2006 {0x55ff55ff, 0xaaaaaaaa}, 2007 {0x55ff55ff, 0x55ff55ff} 2008 }; 2009 2010 /* Shared-Antenna TDMA */ 2011 static const struct coex_tdma_para tdma_sant_8723d[] = { 2012 { {0x08, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 2013 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 2014 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2015 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2016 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2017 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 2018 { {0x61, 0x48, 0x03, 0x11, 0x10} }, 2019 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2020 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2021 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2022 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 2023 { {0x61, 0x10, 0x03, 0x11, 0x14} }, 2024 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2025 { {0x51, 0x10, 0x03, 0x10, 0x54} }, 2026 { {0x51, 0x10, 0x03, 0x10, 0x55} }, 2027 { {0x51, 0x10, 0x07, 0x10, 0x54} }, /* case-15 */ 2028 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2029 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2030 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2031 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2032 { {0x51, 0x15, 0x03, 0x10, 0x50} }, /* case-20 */ 2033 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 2034 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 2035 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 2036 { {0x65, 0x10, 0x03, 0x11, 0x11} }, 2037 { {0x51, 0x10, 0x03, 0x10, 0x51} }, 2038 { {0x61, 0x15, 0x03, 0x11, 0x10} } 2039 }; 2040 2041 /* Non-Shared-Antenna TDMA */ 2042 static const struct coex_tdma_para tdma_nsant_8723d[] = { 2043 { {0x00, 0x00, 0x00, 0x40, 0x01} }, /* case-100 */ 2044 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */ 2045 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2046 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2047 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2048 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 2049 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2050 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2051 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2052 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2053 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 2054 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2055 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2056 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2057 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2058 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 2059 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2060 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2061 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2062 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2063 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */ 2064 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 2065 }; 2066 2067 /* rssi in percentage % (dbm = % - 100) */ 2068 static const u8 wl_rssi_step_8723d[] = {60, 50, 44, 30}; 2069 static const u8 bt_rssi_step_8723d[] = {30, 30, 30, 30}; 2070 static const struct coex_5g_afh_map afh_5g_8723d[] = { {0, 0, 0} }; 2071 2072 static const struct rtw_hw_reg btg_reg_8723d = { 2073 .addr = REG_BTG_SEL, .mask = BIT_MASK_BTG_WL, 2074 }; 2075 2076 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 2077 static const struct coex_rf_para rf_para_tx_8723d[] = { 2078 {0, 0, false, 7}, /* for normal */ 2079 {0, 10, false, 7}, /* for WL-CPT */ 2080 {1, 0, true, 4}, 2081 {1, 2, true, 4}, 2082 {1, 10, true, 4}, 2083 {1, 15, true, 4} 2084 }; 2085 2086 static const struct coex_rf_para rf_para_rx_8723d[] = { 2087 {0, 0, false, 7}, /* for normal */ 2088 {0, 10, false, 7}, /* for WL-CPT */ 2089 {1, 0, true, 5}, 2090 {1, 2, true, 5}, 2091 {1, 10, true, 5}, 2092 {1, 15, true, 5} 2093 }; 2094 2095 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8723d[] = { 2096 {0x0005, 2097 RTW_PWR_CUT_ALL_MSK, 2098 RTW_PWR_INTF_ALL_MSK, 2099 RTW_PWR_ADDR_MAC, 2100 RTW_PWR_CMD_WRITE, BIT(3) | BIT(7), 0}, 2101 {0x0086, 2102 RTW_PWR_CUT_ALL_MSK, 2103 RTW_PWR_INTF_SDIO_MSK, 2104 RTW_PWR_ADDR_SDIO, 2105 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2106 {0x0086, 2107 RTW_PWR_CUT_ALL_MSK, 2108 RTW_PWR_INTF_SDIO_MSK, 2109 RTW_PWR_ADDR_SDIO, 2110 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 2111 {0x004A, 2112 RTW_PWR_CUT_ALL_MSK, 2113 RTW_PWR_INTF_USB_MSK, 2114 RTW_PWR_ADDR_MAC, 2115 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2116 {0x0005, 2117 RTW_PWR_CUT_ALL_MSK, 2118 RTW_PWR_INTF_ALL_MSK, 2119 RTW_PWR_ADDR_MAC, 2120 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, 2121 {0x0023, 2122 RTW_PWR_CUT_ALL_MSK, 2123 RTW_PWR_INTF_SDIO_MSK, 2124 RTW_PWR_ADDR_MAC, 2125 RTW_PWR_CMD_WRITE, BIT(4), 0}, 2126 {0x0301, 2127 RTW_PWR_CUT_ALL_MSK, 2128 RTW_PWR_INTF_PCI_MSK, 2129 RTW_PWR_ADDR_MAC, 2130 RTW_PWR_CMD_WRITE, 0xFF, 0}, 2131 {0xFFFF, 2132 RTW_PWR_CUT_ALL_MSK, 2133 RTW_PWR_INTF_ALL_MSK, 2134 0, 2135 RTW_PWR_CMD_END, 0, 0}, 2136 }; 2137 2138 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8723d[] = { 2139 {0x0020, 2140 RTW_PWR_CUT_ALL_MSK, 2141 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2142 RTW_PWR_ADDR_MAC, 2143 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2144 {0x0001, 2145 RTW_PWR_CUT_ALL_MSK, 2146 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2147 RTW_PWR_ADDR_MAC, 2148 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 2149 {0x0000, 2150 RTW_PWR_CUT_ALL_MSK, 2151 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2152 RTW_PWR_ADDR_MAC, 2153 RTW_PWR_CMD_WRITE, BIT(5), 0}, 2154 {0x0005, 2155 RTW_PWR_CUT_ALL_MSK, 2156 RTW_PWR_INTF_ALL_MSK, 2157 RTW_PWR_ADDR_MAC, 2158 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 2159 {0x0075, 2160 RTW_PWR_CUT_ALL_MSK, 2161 RTW_PWR_INTF_PCI_MSK, 2162 RTW_PWR_ADDR_MAC, 2163 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2164 {0x0006, 2165 RTW_PWR_CUT_ALL_MSK, 2166 RTW_PWR_INTF_ALL_MSK, 2167 RTW_PWR_ADDR_MAC, 2168 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 2169 {0x0075, 2170 RTW_PWR_CUT_ALL_MSK, 2171 RTW_PWR_INTF_PCI_MSK, 2172 RTW_PWR_ADDR_MAC, 2173 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2174 {0x0006, 2175 RTW_PWR_CUT_ALL_MSK, 2176 RTW_PWR_INTF_ALL_MSK, 2177 RTW_PWR_ADDR_MAC, 2178 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2179 {0x0005, 2180 RTW_PWR_CUT_ALL_MSK, 2181 RTW_PWR_INTF_ALL_MSK, 2182 RTW_PWR_ADDR_MAC, 2183 RTW_PWR_CMD_POLLING, (BIT(1) | BIT(0)), 0}, 2184 {0x0005, 2185 RTW_PWR_CUT_ALL_MSK, 2186 RTW_PWR_INTF_ALL_MSK, 2187 RTW_PWR_ADDR_MAC, 2188 RTW_PWR_CMD_WRITE, BIT(7), 0}, 2189 {0x0005, 2190 RTW_PWR_CUT_ALL_MSK, 2191 RTW_PWR_INTF_ALL_MSK, 2192 RTW_PWR_ADDR_MAC, 2193 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 2194 {0x0005, 2195 RTW_PWR_CUT_ALL_MSK, 2196 RTW_PWR_INTF_ALL_MSK, 2197 RTW_PWR_ADDR_MAC, 2198 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2199 {0x0005, 2200 RTW_PWR_CUT_ALL_MSK, 2201 RTW_PWR_INTF_ALL_MSK, 2202 RTW_PWR_ADDR_MAC, 2203 RTW_PWR_CMD_POLLING, BIT(0), 0}, 2204 {0x0010, 2205 RTW_PWR_CUT_ALL_MSK, 2206 RTW_PWR_INTF_ALL_MSK, 2207 RTW_PWR_ADDR_MAC, 2208 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 2209 {0x0049, 2210 RTW_PWR_CUT_ALL_MSK, 2211 RTW_PWR_INTF_ALL_MSK, 2212 RTW_PWR_ADDR_MAC, 2213 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2214 {0x0063, 2215 RTW_PWR_CUT_ALL_MSK, 2216 RTW_PWR_INTF_ALL_MSK, 2217 RTW_PWR_ADDR_MAC, 2218 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2219 {0x0062, 2220 RTW_PWR_CUT_ALL_MSK, 2221 RTW_PWR_INTF_ALL_MSK, 2222 RTW_PWR_ADDR_MAC, 2223 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2224 {0x0058, 2225 RTW_PWR_CUT_ALL_MSK, 2226 RTW_PWR_INTF_ALL_MSK, 2227 RTW_PWR_ADDR_MAC, 2228 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2229 {0x005A, 2230 RTW_PWR_CUT_ALL_MSK, 2231 RTW_PWR_INTF_ALL_MSK, 2232 RTW_PWR_ADDR_MAC, 2233 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2234 {0x0068, 2235 RTW_PWR_CUT_TEST_MSK, 2236 RTW_PWR_INTF_ALL_MSK, 2237 RTW_PWR_ADDR_MAC, 2238 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 2239 {0x0069, 2240 RTW_PWR_CUT_ALL_MSK, 2241 RTW_PWR_INTF_ALL_MSK, 2242 RTW_PWR_ADDR_MAC, 2243 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 2244 {0x001f, 2245 RTW_PWR_CUT_ALL_MSK, 2246 RTW_PWR_INTF_ALL_MSK, 2247 RTW_PWR_ADDR_MAC, 2248 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 2249 {0x0077, 2250 RTW_PWR_CUT_ALL_MSK, 2251 RTW_PWR_INTF_ALL_MSK, 2252 RTW_PWR_ADDR_MAC, 2253 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 2254 {0x001f, 2255 RTW_PWR_CUT_ALL_MSK, 2256 RTW_PWR_INTF_ALL_MSK, 2257 RTW_PWR_ADDR_MAC, 2258 RTW_PWR_CMD_WRITE, 0xFF, 0x07}, 2259 {0x0077, 2260 RTW_PWR_CUT_ALL_MSK, 2261 RTW_PWR_INTF_ALL_MSK, 2262 RTW_PWR_ADDR_MAC, 2263 RTW_PWR_CMD_WRITE, 0xFF, 0x07}, 2264 {0xFFFF, 2265 RTW_PWR_CUT_ALL_MSK, 2266 RTW_PWR_INTF_ALL_MSK, 2267 0, 2268 RTW_PWR_CMD_END, 0, 0}, 2269 }; 2270 2271 static const struct rtw_pwr_seq_cmd *card_enable_flow_8723d[] = { 2272 trans_carddis_to_cardemu_8723d, 2273 trans_cardemu_to_act_8723d, 2274 NULL 2275 }; 2276 2277 static const struct rtw_pwr_seq_cmd trans_act_to_lps_8723d[] = { 2278 {0x0301, 2279 RTW_PWR_CUT_ALL_MSK, 2280 RTW_PWR_INTF_PCI_MSK, 2281 RTW_PWR_ADDR_MAC, 2282 RTW_PWR_CMD_WRITE, 0xFF, 0xFF}, 2283 {0x0522, 2284 RTW_PWR_CUT_ALL_MSK, 2285 RTW_PWR_INTF_ALL_MSK, 2286 RTW_PWR_ADDR_MAC, 2287 RTW_PWR_CMD_WRITE, 0xFF, 0xFF}, 2288 {0x05F8, 2289 RTW_PWR_CUT_ALL_MSK, 2290 RTW_PWR_INTF_ALL_MSK, 2291 RTW_PWR_ADDR_MAC, 2292 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2293 {0x05F9, 2294 RTW_PWR_CUT_ALL_MSK, 2295 RTW_PWR_INTF_ALL_MSK, 2296 RTW_PWR_ADDR_MAC, 2297 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2298 {0x05FA, 2299 RTW_PWR_CUT_ALL_MSK, 2300 RTW_PWR_INTF_ALL_MSK, 2301 RTW_PWR_ADDR_MAC, 2302 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2303 {0x05FB, 2304 RTW_PWR_CUT_ALL_MSK, 2305 RTW_PWR_INTF_ALL_MSK, 2306 RTW_PWR_ADDR_MAC, 2307 RTW_PWR_CMD_POLLING, 0xFF, 0}, 2308 {0x0002, 2309 RTW_PWR_CUT_ALL_MSK, 2310 RTW_PWR_INTF_ALL_MSK, 2311 RTW_PWR_ADDR_MAC, 2312 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2313 {0x0002, 2314 RTW_PWR_CUT_ALL_MSK, 2315 RTW_PWR_INTF_ALL_MSK, 2316 RTW_PWR_ADDR_MAC, 2317 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US}, 2318 {0x0002, 2319 RTW_PWR_CUT_ALL_MSK, 2320 RTW_PWR_INTF_ALL_MSK, 2321 RTW_PWR_ADDR_MAC, 2322 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2323 {0x0100, 2324 RTW_PWR_CUT_ALL_MSK, 2325 RTW_PWR_INTF_ALL_MSK, 2326 RTW_PWR_ADDR_MAC, 2327 RTW_PWR_CMD_WRITE, 0xFF, 0x03}, 2328 {0x0101, 2329 RTW_PWR_CUT_ALL_MSK, 2330 RTW_PWR_INTF_ALL_MSK, 2331 RTW_PWR_ADDR_MAC, 2332 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2333 {0x0093, 2334 RTW_PWR_CUT_ALL_MSK, 2335 RTW_PWR_INTF_SDIO_MSK, 2336 RTW_PWR_ADDR_MAC, 2337 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 2338 {0x0553, 2339 RTW_PWR_CUT_ALL_MSK, 2340 RTW_PWR_INTF_ALL_MSK, 2341 RTW_PWR_ADDR_MAC, 2342 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 2343 {0xFFFF, 2344 RTW_PWR_CUT_ALL_MSK, 2345 RTW_PWR_INTF_ALL_MSK, 2346 0, 2347 RTW_PWR_CMD_END, 0, 0}, 2348 }; 2349 2350 static const struct rtw_pwr_seq_cmd trans_act_to_pre_carddis_8723d[] = { 2351 {0x0003, 2352 RTW_PWR_CUT_ALL_MSK, 2353 RTW_PWR_INTF_ALL_MSK, 2354 RTW_PWR_ADDR_MAC, 2355 RTW_PWR_CMD_WRITE, BIT(2), 0}, 2356 {0x0080, 2357 RTW_PWR_CUT_ALL_MSK, 2358 RTW_PWR_INTF_ALL_MSK, 2359 RTW_PWR_ADDR_MAC, 2360 RTW_PWR_CMD_WRITE, 0xFF, 0}, 2361 {0xFFFF, 2362 RTW_PWR_CUT_ALL_MSK, 2363 RTW_PWR_INTF_ALL_MSK, 2364 0, 2365 RTW_PWR_CMD_END, 0, 0}, 2366 }; 2367 2368 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8723d[] = { 2369 {0x0002, 2370 RTW_PWR_CUT_ALL_MSK, 2371 RTW_PWR_INTF_ALL_MSK, 2372 RTW_PWR_ADDR_MAC, 2373 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2374 {0x0049, 2375 RTW_PWR_CUT_ALL_MSK, 2376 RTW_PWR_INTF_ALL_MSK, 2377 RTW_PWR_ADDR_MAC, 2378 RTW_PWR_CMD_WRITE, BIT(1), 0}, 2379 {0x0006, 2380 RTW_PWR_CUT_ALL_MSK, 2381 RTW_PWR_INTF_ALL_MSK, 2382 RTW_PWR_ADDR_MAC, 2383 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2384 {0x0005, 2385 RTW_PWR_CUT_ALL_MSK, 2386 RTW_PWR_INTF_ALL_MSK, 2387 RTW_PWR_ADDR_MAC, 2388 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 2389 {0x0005, 2390 RTW_PWR_CUT_ALL_MSK, 2391 RTW_PWR_INTF_ALL_MSK, 2392 RTW_PWR_ADDR_MAC, 2393 RTW_PWR_CMD_POLLING, BIT(1), 0}, 2394 {0x0010, 2395 RTW_PWR_CUT_ALL_MSK, 2396 RTW_PWR_INTF_ALL_MSK, 2397 RTW_PWR_ADDR_MAC, 2398 RTW_PWR_CMD_WRITE, BIT(6), 0}, 2399 {0x0000, 2400 RTW_PWR_CUT_ALL_MSK, 2401 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2402 RTW_PWR_ADDR_MAC, 2403 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 2404 {0x0020, 2405 RTW_PWR_CUT_ALL_MSK, 2406 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2407 RTW_PWR_ADDR_MAC, 2408 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2409 {0xFFFF, 2410 RTW_PWR_CUT_ALL_MSK, 2411 RTW_PWR_INTF_ALL_MSK, 2412 0, 2413 RTW_PWR_CMD_END, 0, 0}, 2414 }; 2415 2416 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8723d[] = { 2417 {0x0007, 2418 RTW_PWR_CUT_ALL_MSK, 2419 RTW_PWR_INTF_SDIO_MSK, 2420 RTW_PWR_ADDR_MAC, 2421 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 2422 {0x0005, 2423 RTW_PWR_CUT_ALL_MSK, 2424 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 2425 RTW_PWR_ADDR_MAC, 2426 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 2427 {0x0005, 2428 RTW_PWR_CUT_ALL_MSK, 2429 RTW_PWR_INTF_PCI_MSK, 2430 RTW_PWR_ADDR_MAC, 2431 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 2432 {0x0005, 2433 RTW_PWR_CUT_ALL_MSK, 2434 RTW_PWR_INTF_PCI_MSK, 2435 RTW_PWR_ADDR_MAC, 2436 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, 2437 {0x004A, 2438 RTW_PWR_CUT_ALL_MSK, 2439 RTW_PWR_INTF_USB_MSK, 2440 RTW_PWR_ADDR_MAC, 2441 RTW_PWR_CMD_WRITE, BIT(0), 1}, 2442 {0x0023, 2443 RTW_PWR_CUT_ALL_MSK, 2444 RTW_PWR_INTF_SDIO_MSK, 2445 RTW_PWR_ADDR_MAC, 2446 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 2447 {0x0086, 2448 RTW_PWR_CUT_ALL_MSK, 2449 RTW_PWR_INTF_SDIO_MSK, 2450 RTW_PWR_ADDR_SDIO, 2451 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2452 {0x0086, 2453 RTW_PWR_CUT_ALL_MSK, 2454 RTW_PWR_INTF_SDIO_MSK, 2455 RTW_PWR_ADDR_SDIO, 2456 RTW_PWR_CMD_POLLING, BIT(1), 0}, 2457 {0xFFFF, 2458 RTW_PWR_CUT_ALL_MSK, 2459 RTW_PWR_INTF_ALL_MSK, 2460 0, 2461 RTW_PWR_CMD_END, 0, 0}, 2462 }; 2463 2464 static const struct rtw_pwr_seq_cmd trans_act_to_post_carddis_8723d[] = { 2465 {0x001D, 2466 RTW_PWR_CUT_ALL_MSK, 2467 RTW_PWR_INTF_ALL_MSK, 2468 RTW_PWR_ADDR_MAC, 2469 RTW_PWR_CMD_WRITE, BIT(0), 0}, 2470 {0x001D, 2471 RTW_PWR_CUT_ALL_MSK, 2472 RTW_PWR_INTF_ALL_MSK, 2473 RTW_PWR_ADDR_MAC, 2474 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 2475 {0x001C, 2476 RTW_PWR_CUT_ALL_MSK, 2477 RTW_PWR_INTF_ALL_MSK, 2478 RTW_PWR_ADDR_MAC, 2479 RTW_PWR_CMD_WRITE, 0xFF, 0x0E}, 2480 {0xFFFF, 2481 RTW_PWR_CUT_ALL_MSK, 2482 RTW_PWR_INTF_ALL_MSK, 2483 0, 2484 RTW_PWR_CMD_END, 0, 0}, 2485 }; 2486 2487 static const struct rtw_pwr_seq_cmd *card_disable_flow_8723d[] = { 2488 trans_act_to_lps_8723d, 2489 trans_act_to_pre_carddis_8723d, 2490 trans_act_to_cardemu_8723d, 2491 trans_cardemu_to_carddis_8723d, 2492 trans_act_to_post_carddis_8723d, 2493 NULL 2494 }; 2495 2496 static const struct rtw_page_table page_table_8723d[] = { 2497 {12, 2, 2, 0, 1}, 2498 {12, 2, 2, 0, 1}, 2499 {12, 2, 2, 0, 1}, 2500 {12, 2, 2, 0, 1}, 2501 {12, 2, 2, 0, 1}, 2502 }; 2503 2504 static const struct rtw_rqpn rqpn_table_8723d[] = { 2505 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2506 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2507 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2508 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2509 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2510 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2511 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2512 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 2513 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2514 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2515 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2516 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2517 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2518 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2519 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2520 }; 2521 2522 static const struct rtw_prioq_addrs prioq_addrs_8723d = { 2523 .prio[RTW_DMA_MAPPING_EXTRA] = { 2524 .rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3, 2525 }, 2526 .prio[RTW_DMA_MAPPING_LOW] = { 2527 .rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1, 2528 }, 2529 .prio[RTW_DMA_MAPPING_NORMAL] = { 2530 .rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1, 2531 }, 2532 .prio[RTW_DMA_MAPPING_HIGH] = { 2533 .rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2, 2534 }, 2535 .wsize = false, 2536 }; 2537 2538 static const struct rtw_intf_phy_para pcie_gen1_param_8723d[] = { 2539 {0x0008, 0x4a22, 2540 RTW_IP_SEL_PHY, 2541 RTW_INTF_PHY_CUT_ALL, 2542 RTW_INTF_PHY_PLATFORM_ALL}, 2543 {0x0009, 0x1000, 2544 RTW_IP_SEL_PHY, 2545 ~(RTW_INTF_PHY_CUT_A | RTW_INTF_PHY_CUT_B), 2546 RTW_INTF_PHY_PLATFORM_ALL}, 2547 {0xFFFF, 0x0000, 2548 RTW_IP_SEL_PHY, 2549 RTW_INTF_PHY_CUT_ALL, 2550 RTW_INTF_PHY_PLATFORM_ALL}, 2551 }; 2552 2553 static const struct rtw_intf_phy_para_table phy_para_table_8723d = { 2554 .gen1_para = pcie_gen1_param_8723d, 2555 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8723d), 2556 }; 2557 2558 static const struct rtw_hw_reg rtw8723d_dig[] = { 2559 [0] = { .addr = 0xc50, .mask = 0x7f }, 2560 [1] = { .addr = 0xc50, .mask = 0x7f }, 2561 }; 2562 2563 static const struct rtw_hw_reg rtw8723d_dig_cck[] = { 2564 [0] = { .addr = 0xa0c, .mask = 0x3f00 }, 2565 }; 2566 2567 static const struct rtw_rf_sipi_addr rtw8723d_rf_sipi_addr[] = { 2568 [RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0, 2569 .hssi_2 = 0x824, .lssi_read_pi = 0x8b8}, 2570 [RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read = 0x8a4, 2571 .hssi_2 = 0x82c, .lssi_read_pi = 0x8bc}, 2572 }; 2573 2574 static const struct rtw_ltecoex_addr rtw8723d_ltecoex_addr = { 2575 .ctrl = REG_LTECOEX_CTRL, 2576 .wdata = REG_LTECOEX_WRITE_DATA, 2577 .rdata = REG_LTECOEX_READ_DATA, 2578 }; 2579 2580 static const struct rtw_rfe_def rtw8723d_rfe_defs[] = { 2581 [0] = { .phy_pg_tbl = &rtw8723d_bb_pg_tbl, 2582 .txpwr_lmt_tbl = &rtw8723d_txpwr_lmt_tbl,}, 2583 }; 2584 2585 static const u8 rtw8723d_pwrtrk_2gb_n[] = { 2586 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 2587 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10 2588 }; 2589 2590 static const u8 rtw8723d_pwrtrk_2gb_p[] = { 2591 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 2592 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10 2593 }; 2594 2595 static const u8 rtw8723d_pwrtrk_2ga_n[] = { 2596 0, 0, 1, 1, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 5, 2597 6, 6, 7, 7, 8, 8, 8, 9, 9, 9, 10, 10, 10, 10, 10 2598 }; 2599 2600 static const u8 rtw8723d_pwrtrk_2ga_p[] = { 2601 0, 0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 7, 2602 7, 8, 8, 8, 9, 9, 10, 10, 10, 10, 10, 10, 10, 10, 10 2603 }; 2604 2605 static const u8 rtw8723d_pwrtrk_2g_cck_b_n[] = { 2606 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 2607 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11 2608 }; 2609 2610 static const u8 rtw8723d_pwrtrk_2g_cck_b_p[] = { 2611 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 2612 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11 2613 }; 2614 2615 static const u8 rtw8723d_pwrtrk_2g_cck_a_n[] = { 2616 0, 1, 1, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 2617 6, 7, 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11 2618 }; 2619 2620 static const u8 rtw8723d_pwrtrk_2g_cck_a_p[] = { 2621 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 2622 7, 8, 9, 9, 10, 10, 11, 11, 11, 11, 11, 11, 11, 11, 11 2623 }; 2624 2625 static const s8 rtw8723d_pwrtrk_xtal_n[] = { 2626 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2627 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 2628 }; 2629 2630 static const s8 rtw8723d_pwrtrk_xtal_p[] = { 2631 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2632 0, -10, -12, -14, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16, -16 2633 }; 2634 2635 static const struct rtw_pwr_track_tbl rtw8723d_rtw_pwr_track_tbl = { 2636 .pwrtrk_2gb_n = rtw8723d_pwrtrk_2gb_n, 2637 .pwrtrk_2gb_p = rtw8723d_pwrtrk_2gb_p, 2638 .pwrtrk_2ga_n = rtw8723d_pwrtrk_2ga_n, 2639 .pwrtrk_2ga_p = rtw8723d_pwrtrk_2ga_p, 2640 .pwrtrk_2g_cckb_n = rtw8723d_pwrtrk_2g_cck_b_n, 2641 .pwrtrk_2g_cckb_p = rtw8723d_pwrtrk_2g_cck_b_p, 2642 .pwrtrk_2g_ccka_n = rtw8723d_pwrtrk_2g_cck_a_n, 2643 .pwrtrk_2g_ccka_p = rtw8723d_pwrtrk_2g_cck_a_p, 2644 .pwrtrk_xtal_p = rtw8723d_pwrtrk_xtal_p, 2645 .pwrtrk_xtal_n = rtw8723d_pwrtrk_xtal_n, 2646 }; 2647 2648 static const struct rtw_reg_domain coex_info_hw_regs_8723d[] = { 2649 {0x948, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2650 {0x67, BIT(7), RTW_REG_DOMAIN_MAC8}, 2651 {0, 0, RTW_REG_DOMAIN_NL}, 2652 {0x964, BIT(1), RTW_REG_DOMAIN_MAC8}, 2653 {0x864, BIT(0), RTW_REG_DOMAIN_MAC8}, 2654 {0xab7, BIT(5), RTW_REG_DOMAIN_MAC8}, 2655 {0xa01, BIT(7), RTW_REG_DOMAIN_MAC8}, 2656 {0, 0, RTW_REG_DOMAIN_NL}, 2657 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2658 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2659 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2660 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2661 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 2662 {0, 0, RTW_REG_DOMAIN_NL}, 2663 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 2664 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 2665 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2666 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2667 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 2668 }; 2669 2670 struct rtw_chip_info rtw8723d_hw_spec = { 2671 .ops = &rtw8723d_ops, 2672 .id = RTW_CHIP_TYPE_8723D, 2673 .fw_name = "rtw88/rtw8723d_fw.bin", 2674 .wlan_cpu = RTW_WCPU_11N, 2675 .tx_pkt_desc_sz = 40, 2676 .tx_buf_desc_sz = 16, 2677 .rx_pkt_desc_sz = 24, 2678 .rx_buf_desc_sz = 8, 2679 .phy_efuse_size = 512, 2680 .log_efuse_size = 512, 2681 .ptct_efuse_size = 96 + 1, 2682 .txff_size = 32768, 2683 .rxff_size = 16384, 2684 .txgi_factor = 1, 2685 .is_pwr_by_rate_dec = true, 2686 .max_power_index = 0x3f, 2687 .csi_buf_pg_num = 0, 2688 .band = RTW_BAND_2G, 2689 .page_size = 128, 2690 .dig_min = 0x20, 2691 .ht_supported = true, 2692 .vht_supported = false, 2693 .lps_deep_mode_supported = 0, 2694 .sys_func_en = 0xFD, 2695 .pwr_on_seq = card_enable_flow_8723d, 2696 .pwr_off_seq = card_disable_flow_8723d, 2697 .page_table = page_table_8723d, 2698 .rqpn_table = rqpn_table_8723d, 2699 .prioq_addrs = &prioq_addrs_8723d, 2700 .intf_table = &phy_para_table_8723d, 2701 .dig = rtw8723d_dig, 2702 .dig_cck = rtw8723d_dig_cck, 2703 .rf_sipi_addr = {0x840, 0x844}, 2704 .rf_sipi_read_addr = rtw8723d_rf_sipi_addr, 2705 .fix_rf_phy_num = 2, 2706 .ltecoex_addr = &rtw8723d_ltecoex_addr, 2707 .mac_tbl = &rtw8723d_mac_tbl, 2708 .agc_tbl = &rtw8723d_agc_tbl, 2709 .bb_tbl = &rtw8723d_bb_tbl, 2710 .rf_tbl = {&rtw8723d_rf_a_tbl}, 2711 .rfe_defs = rtw8723d_rfe_defs, 2712 .rfe_defs_size = ARRAY_SIZE(rtw8723d_rfe_defs), 2713 .rx_ldpc = false, 2714 .pwr_track_tbl = &rtw8723d_rtw_pwr_track_tbl, 2715 .iqk_threshold = 8, 2716 2717 .coex_para_ver = 0x1905302f, 2718 .bt_desired_ver = 0x2f, 2719 .scbd_support = true, 2720 .new_scbd10_def = true, 2721 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2722 .bt_rssi_type = COEX_BTRSSI_RATIO, 2723 .ant_isolation = 15, 2724 .rssi_tolerance = 2, 2725 .wl_rssi_step = wl_rssi_step_8723d, 2726 .bt_rssi_step = bt_rssi_step_8723d, 2727 .table_sant_num = ARRAY_SIZE(table_sant_8723d), 2728 .table_sant = table_sant_8723d, 2729 .table_nsant_num = ARRAY_SIZE(table_nsant_8723d), 2730 .table_nsant = table_nsant_8723d, 2731 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8723d), 2732 .tdma_sant = tdma_sant_8723d, 2733 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8723d), 2734 .tdma_nsant = tdma_nsant_8723d, 2735 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8723d), 2736 .wl_rf_para_tx = rf_para_tx_8723d, 2737 .wl_rf_para_rx = rf_para_rx_8723d, 2738 .bt_afh_span_bw20 = 0x20, 2739 .bt_afh_span_bw40 = 0x30, 2740 .afh_5g_num = ARRAY_SIZE(afh_5g_8723d), 2741 .afh_5g = afh_5g_8723d, 2742 .btg_reg = &btg_reg_8723d, 2743 2744 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8723d), 2745 .coex_info_hw_regs = coex_info_hw_regs_8723d, 2746 }; 2747 EXPORT_SYMBOL(rtw8723d_hw_spec); 2748 2749 MODULE_FIRMWARE("rtw88/rtw8723d_fw.bin"); 2750 2751 MODULE_AUTHOR("Realtek Corporation"); 2752 MODULE_DESCRIPTION("Realtek 802.11n wireless 8723d driver"); 2753 MODULE_LICENSE("Dual BSD/GPL"); 2754