1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __KVM_X86_LAPIC_H 3 #define __KVM_X86_LAPIC_H 4 5 #include <kvm/iodev.h> 6 7 #include <linux/kvm_host.h> 8 9 #define KVM_APIC_INIT 0 10 #define KVM_APIC_SIPI 1 11 #define KVM_APIC_LVT_NUM 6 12 13 #define APIC_SHORT_MASK 0xc0000 14 #define APIC_DEST_NOSHORT 0x0 15 #define APIC_DEST_MASK 0x800 16 17 #define APIC_BUS_CYCLE_NS 1 18 #define APIC_BUS_FREQUENCY (1000000000ULL / APIC_BUS_CYCLE_NS) 19 20 enum lapic_mode { 21 LAPIC_MODE_DISABLED = 0, 22 LAPIC_MODE_INVALID = X2APIC_ENABLE, 23 LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE, 24 LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE, 25 }; 26 27 struct kvm_timer { 28 struct hrtimer timer; 29 s64 period; /* unit: ns */ 30 ktime_t target_expiration; 31 u32 timer_mode; 32 u32 timer_mode_mask; 33 u64 tscdeadline; 34 u64 expired_tscdeadline; 35 u32 timer_advance_ns; 36 s64 advance_expire_delta; 37 atomic_t pending; /* accumulated triggered timers */ 38 bool hv_timer_in_use; 39 }; 40 41 struct kvm_lapic { 42 unsigned long base_address; 43 struct kvm_io_device dev; 44 struct kvm_timer lapic_timer; 45 u32 divide_count; 46 struct kvm_vcpu *vcpu; 47 bool sw_enabled; 48 bool irr_pending; 49 bool lvt0_in_nmi_mode; 50 /* Number of bits set in ISR. */ 51 s16 isr_count; 52 /* The highest vector set in ISR; if -1 - invalid, must scan ISR. */ 53 int highest_isr_cache; 54 /** 55 * APIC register page. The layout matches the register layout seen by 56 * the guest 1:1, because it is accessed by the vmx microcode. 57 * Note: Only one register, the TPR, is used by the microcode. 58 */ 59 void *regs; 60 gpa_t vapic_addr; 61 struct gfn_to_hva_cache vapic_cache; 62 unsigned long pending_events; 63 unsigned int sipi_vector; 64 }; 65 66 struct dest_map; 67 68 int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns); 69 void kvm_free_lapic(struct kvm_vcpu *vcpu); 70 71 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu); 72 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu); 73 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu); 74 void kvm_apic_accept_events(struct kvm_vcpu *vcpu); 75 void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event); 76 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu); 77 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8); 78 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu); 79 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value); 80 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu); 81 void kvm_apic_set_version(struct kvm_vcpu *vcpu); 82 int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val); 83 int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, 84 void *data); 85 bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, 86 int shorthand, unsigned int dest, int dest_mode); 87 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2); 88 bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr); 89 bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr); 90 void kvm_apic_update_ppr(struct kvm_vcpu *vcpu); 91 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, 92 struct dest_map *dest_map); 93 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type); 94 void kvm_apic_update_apicv(struct kvm_vcpu *vcpu); 95 96 bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, 97 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map); 98 99 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu); 100 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info); 101 int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); 102 int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s); 103 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu); 104 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); 105 106 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu); 107 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data); 108 109 void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset); 110 void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector); 111 112 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); 113 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); 114 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu); 115 116 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 117 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 118 119 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data); 120 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data); 121 122 static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu) 123 { 124 return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE; 125 } 126 127 int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len); 128 void kvm_lapic_init(void); 129 void kvm_lapic_exit(void); 130 131 #define VEC_POS(v) ((v) & (32 - 1)) 132 #define REG_POS(v) (((v) >> 5) << 4) 133 134 static inline void kvm_lapic_clear_vector(int vec, void *bitmap) 135 { 136 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 137 } 138 139 static inline void kvm_lapic_set_vector(int vec, void *bitmap) 140 { 141 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); 142 } 143 144 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) 145 { 146 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR); 147 /* 148 * irr_pending must be true if any interrupt is pending; set it after 149 * APIC_IRR to avoid race with apic_clear_irr 150 */ 151 apic->irr_pending = true; 152 } 153 154 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) 155 { 156 return *((u32 *) (apic->regs + reg_off)); 157 } 158 159 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) 160 { 161 *((u32 *) (apic->regs + reg_off)) = val; 162 } 163 164 extern struct static_key kvm_no_apic_vcpu; 165 166 static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu) 167 { 168 if (static_key_false(&kvm_no_apic_vcpu)) 169 return vcpu->arch.apic; 170 return true; 171 } 172 173 extern struct static_key_deferred apic_hw_disabled; 174 175 static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic) 176 { 177 if (static_key_false(&apic_hw_disabled.key)) 178 return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE; 179 return MSR_IA32_APICBASE_ENABLE; 180 } 181 182 extern struct static_key_deferred apic_sw_disabled; 183 184 static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic) 185 { 186 if (static_key_false(&apic_sw_disabled.key)) 187 return apic->sw_enabled; 188 return true; 189 } 190 191 static inline bool kvm_apic_present(struct kvm_vcpu *vcpu) 192 { 193 return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic); 194 } 195 196 static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu) 197 { 198 return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic); 199 } 200 201 static inline int apic_x2apic_mode(struct kvm_lapic *apic) 202 { 203 return apic->vcpu->arch.apic_base & X2APIC_ENABLE; 204 } 205 206 static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu) 207 { 208 return vcpu->arch.apic && vcpu->arch.apicv_active; 209 } 210 211 static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu) 212 { 213 return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events; 214 } 215 216 static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq) 217 { 218 return (irq->delivery_mode == APIC_DM_LOWEST || 219 irq->msi_redir_hint); 220 } 221 222 static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu) 223 { 224 return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events); 225 } 226 227 bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector); 228 229 void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu); 230 231 void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq, 232 unsigned long *vcpu_bitmap); 233 234 bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, 235 struct kvm_vcpu **dest_vcpu); 236 int kvm_vector_to_index(u32 vector, u32 dest_vcpus, 237 const unsigned long *bitmap, u32 bitmap_size); 238 void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu); 239 void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu); 240 void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu); 241 bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu); 242 void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu); 243 bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu); 244 245 static inline enum lapic_mode kvm_apic_mode(u64 apic_base) 246 { 247 return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE); 248 } 249 250 static inline u8 kvm_xapic_id(struct kvm_lapic *apic) 251 { 252 return kvm_lapic_get_reg(apic, APIC_ID) >> 24; 253 } 254 255 #endif 256