1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Driver for Microsemi VSC85xx PHYs 4 * 5 * Author: Nagaraju Lakkaraju 6 * License: Dual MIT/GPL 7 * Copyright (c) 2016 Microsemi Corporation 8 */ 9 10 #include <linux/firmware.h> 11 #include <linux/jiffies.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mdio.h> 15 #include <linux/mii.h> 16 #include <linux/phy.h> 17 #include <linux/of.h> 18 #include <linux/netdevice.h> 19 #include <dt-bindings/net/mscc-phy-vsc8531.h> 20 21 #include "mscc.h" 22 23 static const struct vsc85xx_hw_stat vsc85xx_hw_stats[] = { 24 { 25 .string = "phy_receive_errors", 26 .reg = MSCC_PHY_ERR_RX_CNT, 27 .page = MSCC_PHY_PAGE_STANDARD, 28 .mask = ERR_CNT_MASK, 29 }, { 30 .string = "phy_false_carrier", 31 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, 32 .page = MSCC_PHY_PAGE_STANDARD, 33 .mask = ERR_CNT_MASK, 34 }, { 35 .string = "phy_cu_media_link_disconnect", 36 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, 37 .page = MSCC_PHY_PAGE_STANDARD, 38 .mask = ERR_CNT_MASK, 39 }, { 40 .string = "phy_cu_media_crc_good_count", 41 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, 42 .page = MSCC_PHY_PAGE_EXTENDED, 43 .mask = VALID_CRC_CNT_CRC_MASK, 44 }, { 45 .string = "phy_cu_media_crc_error_count", 46 .reg = MSCC_PHY_EXT_PHY_CNTL_4, 47 .page = MSCC_PHY_PAGE_EXTENDED, 48 .mask = ERR_CNT_MASK, 49 }, 50 }; 51 52 static const struct vsc85xx_hw_stat vsc8584_hw_stats[] = { 53 { 54 .string = "phy_receive_errors", 55 .reg = MSCC_PHY_ERR_RX_CNT, 56 .page = MSCC_PHY_PAGE_STANDARD, 57 .mask = ERR_CNT_MASK, 58 }, { 59 .string = "phy_false_carrier", 60 .reg = MSCC_PHY_ERR_FALSE_CARRIER_CNT, 61 .page = MSCC_PHY_PAGE_STANDARD, 62 .mask = ERR_CNT_MASK, 63 }, { 64 .string = "phy_cu_media_link_disconnect", 65 .reg = MSCC_PHY_ERR_LINK_DISCONNECT_CNT, 66 .page = MSCC_PHY_PAGE_STANDARD, 67 .mask = ERR_CNT_MASK, 68 }, { 69 .string = "phy_cu_media_crc_good_count", 70 .reg = MSCC_PHY_CU_MEDIA_CRC_VALID_CNT, 71 .page = MSCC_PHY_PAGE_EXTENDED, 72 .mask = VALID_CRC_CNT_CRC_MASK, 73 }, { 74 .string = "phy_cu_media_crc_error_count", 75 .reg = MSCC_PHY_EXT_PHY_CNTL_4, 76 .page = MSCC_PHY_PAGE_EXTENDED, 77 .mask = ERR_CNT_MASK, 78 }, { 79 .string = "phy_serdes_tx_good_pkt_count", 80 .reg = MSCC_PHY_SERDES_TX_VALID_CNT, 81 .page = MSCC_PHY_PAGE_EXTENDED_3, 82 .mask = VALID_CRC_CNT_CRC_MASK, 83 }, { 84 .string = "phy_serdes_tx_bad_crc_count", 85 .reg = MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 86 .page = MSCC_PHY_PAGE_EXTENDED_3, 87 .mask = ERR_CNT_MASK, 88 }, { 89 .string = "phy_serdes_rx_good_pkt_count", 90 .reg = MSCC_PHY_SERDES_RX_VALID_CNT, 91 .page = MSCC_PHY_PAGE_EXTENDED_3, 92 .mask = VALID_CRC_CNT_CRC_MASK, 93 }, { 94 .string = "phy_serdes_rx_bad_crc_count", 95 .reg = MSCC_PHY_SERDES_RX_CRC_ERR_CNT, 96 .page = MSCC_PHY_PAGE_EXTENDED_3, 97 .mask = ERR_CNT_MASK, 98 }, 99 }; 100 101 #ifdef CONFIG_OF_MDIO 102 static const struct vsc8531_edge_rate_table edge_table[] = { 103 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} }, 104 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} }, 105 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} }, 106 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} }, 107 }; 108 #endif 109 110 static int vsc85xx_phy_read_page(struct phy_device *phydev) 111 { 112 return __phy_read(phydev, MSCC_EXT_PAGE_ACCESS); 113 } 114 115 static int vsc85xx_phy_write_page(struct phy_device *phydev, int page) 116 { 117 return __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, page); 118 } 119 120 static int vsc85xx_get_sset_count(struct phy_device *phydev) 121 { 122 struct vsc8531_private *priv = phydev->priv; 123 124 if (!priv) 125 return 0; 126 127 return priv->nstats; 128 } 129 130 static void vsc85xx_get_strings(struct phy_device *phydev, u8 *data) 131 { 132 struct vsc8531_private *priv = phydev->priv; 133 int i; 134 135 if (!priv) 136 return; 137 138 for (i = 0; i < priv->nstats; i++) 139 strlcpy(data + i * ETH_GSTRING_LEN, priv->hw_stats[i].string, 140 ETH_GSTRING_LEN); 141 } 142 143 static u64 vsc85xx_get_stat(struct phy_device *phydev, int i) 144 { 145 struct vsc8531_private *priv = phydev->priv; 146 int val; 147 148 val = phy_read_paged(phydev, priv->hw_stats[i].page, 149 priv->hw_stats[i].reg); 150 if (val < 0) 151 return U64_MAX; 152 153 val = val & priv->hw_stats[i].mask; 154 priv->stats[i] += val; 155 156 return priv->stats[i]; 157 } 158 159 static void vsc85xx_get_stats(struct phy_device *phydev, 160 struct ethtool_stats *stats, u64 *data) 161 { 162 struct vsc8531_private *priv = phydev->priv; 163 int i; 164 165 if (!priv) 166 return; 167 168 for (i = 0; i < priv->nstats; i++) 169 data[i] = vsc85xx_get_stat(phydev, i); 170 } 171 172 static int vsc85xx_led_cntl_set(struct phy_device *phydev, 173 u8 led_num, 174 u8 mode) 175 { 176 int rc; 177 u16 reg_val; 178 179 mutex_lock(&phydev->lock); 180 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL); 181 reg_val &= ~LED_MODE_SEL_MASK(led_num); 182 reg_val |= LED_MODE_SEL(led_num, (u16)mode); 183 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val); 184 mutex_unlock(&phydev->lock); 185 186 return rc; 187 } 188 189 static int vsc85xx_mdix_get(struct phy_device *phydev, u8 *mdix) 190 { 191 u16 reg_val; 192 193 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL); 194 if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK) 195 *mdix = ETH_TP_MDI_X; 196 else 197 *mdix = ETH_TP_MDI; 198 199 return 0; 200 } 201 202 static int vsc85xx_mdix_set(struct phy_device *phydev, u8 mdix) 203 { 204 int rc; 205 u16 reg_val; 206 207 reg_val = phy_read(phydev, MSCC_PHY_BYPASS_CONTROL); 208 if (mdix == ETH_TP_MDI || mdix == ETH_TP_MDI_X) { 209 reg_val |= (DISABLE_PAIR_SWAP_CORR_MASK | 210 DISABLE_POLARITY_CORR_MASK | 211 DISABLE_HP_AUTO_MDIX_MASK); 212 } else { 213 reg_val &= ~(DISABLE_PAIR_SWAP_CORR_MASK | 214 DISABLE_POLARITY_CORR_MASK | 215 DISABLE_HP_AUTO_MDIX_MASK); 216 } 217 rc = phy_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg_val); 218 if (rc) 219 return rc; 220 221 reg_val = 0; 222 223 if (mdix == ETH_TP_MDI) 224 reg_val = FORCE_MDI_CROSSOVER_MDI; 225 else if (mdix == ETH_TP_MDI_X) 226 reg_val = FORCE_MDI_CROSSOVER_MDIX; 227 228 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 229 MSCC_PHY_EXT_MODE_CNTL, FORCE_MDI_CROSSOVER_MASK, 230 reg_val); 231 if (rc < 0) 232 return rc; 233 234 return genphy_restart_aneg(phydev); 235 } 236 237 static int vsc85xx_downshift_get(struct phy_device *phydev, u8 *count) 238 { 239 int reg_val; 240 241 reg_val = phy_read_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 242 MSCC_PHY_ACTIPHY_CNTL); 243 if (reg_val < 0) 244 return reg_val; 245 246 reg_val &= DOWNSHIFT_CNTL_MASK; 247 if (!(reg_val & DOWNSHIFT_EN)) 248 *count = DOWNSHIFT_DEV_DISABLE; 249 else 250 *count = ((reg_val & ~DOWNSHIFT_EN) >> DOWNSHIFT_CNTL_POS) + 2; 251 252 return 0; 253 } 254 255 static int vsc85xx_downshift_set(struct phy_device *phydev, u8 count) 256 { 257 if (count == DOWNSHIFT_DEV_DEFAULT_COUNT) { 258 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */ 259 count = ((1 << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN); 260 } else if (count > DOWNSHIFT_COUNT_MAX || count == 1) { 261 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); 262 return -ERANGE; 263 } else if (count) { 264 /* Downshift count is either 2,3,4 or 5 */ 265 count = (((count - 2) << DOWNSHIFT_CNTL_POS) | DOWNSHIFT_EN); 266 } 267 268 return phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED, 269 MSCC_PHY_ACTIPHY_CNTL, DOWNSHIFT_CNTL_MASK, 270 count); 271 } 272 273 static int vsc85xx_wol_set(struct phy_device *phydev, 274 struct ethtool_wolinfo *wol) 275 { 276 int rc; 277 u16 reg_val; 278 u8 i; 279 u16 pwd[3] = {0, 0, 0}; 280 struct ethtool_wolinfo *wol_conf = wol; 281 u8 *mac_addr = phydev->attached_dev->dev_addr; 282 283 mutex_lock(&phydev->lock); 284 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); 285 if (rc < 0) { 286 rc = phy_restore_page(phydev, rc, rc); 287 goto out_unlock; 288 } 289 290 if (wol->wolopts & WAKE_MAGIC) { 291 /* Store the device address for the magic packet */ 292 for (i = 0; i < ARRAY_SIZE(pwd); i++) 293 pwd[i] = mac_addr[5 - (i * 2 + 1)] << 8 | 294 mac_addr[5 - i * 2]; 295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); 296 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, pwd[1]); 297 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, pwd[2]); 298 } else { 299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); 300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); 301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); 302 } 303 304 if (wol_conf->wolopts & WAKE_MAGICSECURE) { 305 for (i = 0; i < ARRAY_SIZE(pwd); i++) 306 pwd[i] = wol_conf->sopass[5 - (i * 2 + 1)] << 8 | 307 wol_conf->sopass[5 - i * 2]; 308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); 309 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, pwd[1]); 310 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, pwd[2]); 311 } else { 312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); 313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); 314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); 315 } 316 317 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); 318 if (wol_conf->wolopts & WAKE_MAGICSECURE) 319 reg_val |= SECURE_ON_ENABLE; 320 else 321 reg_val &= ~SECURE_ON_ENABLE; 322 __phy_write(phydev, MSCC_PHY_WOL_MAC_CONTROL, reg_val); 323 324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); 325 if (rc < 0) 326 goto out_unlock; 327 328 if (wol->wolopts & WAKE_MAGIC) { 329 /* Enable the WOL interrupt */ 330 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); 331 reg_val |= MII_VSC85XX_INT_MASK_WOL; 332 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); 333 if (rc) 334 goto out_unlock; 335 } else { 336 /* Disable the WOL interrupt */ 337 reg_val = phy_read(phydev, MII_VSC85XX_INT_MASK); 338 reg_val &= (~MII_VSC85XX_INT_MASK_WOL); 339 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, reg_val); 340 if (rc) 341 goto out_unlock; 342 } 343 /* Clear WOL iterrupt status */ 344 reg_val = phy_read(phydev, MII_VSC85XX_INT_STATUS); 345 346 out_unlock: 347 mutex_unlock(&phydev->lock); 348 349 return rc; 350 } 351 352 static void vsc85xx_wol_get(struct phy_device *phydev, 353 struct ethtool_wolinfo *wol) 354 { 355 int rc; 356 u16 reg_val; 357 u8 i; 358 u16 pwd[3] = {0, 0, 0}; 359 struct ethtool_wolinfo *wol_conf = wol; 360 361 mutex_lock(&phydev->lock); 362 rc = phy_select_page(phydev, MSCC_PHY_PAGE_EXTENDED_2); 363 if (rc < 0) 364 goto out_unlock; 365 366 reg_val = __phy_read(phydev, MSCC_PHY_WOL_MAC_CONTROL); 367 if (reg_val & SECURE_ON_ENABLE) 368 wol_conf->wolopts |= WAKE_MAGICSECURE; 369 if (wol_conf->wolopts & WAKE_MAGICSECURE) { 370 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); 371 pwd[1] = __phy_read(phydev, MSCC_PHY_WOL_MID_PASSWD); 372 pwd[2] = __phy_read(phydev, MSCC_PHY_WOL_UPPER_PASSWD); 373 for (i = 0; i < ARRAY_SIZE(pwd); i++) { 374 wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff; 375 wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00) 376 >> 8; 377 } 378 } 379 380 out_unlock: 381 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); 382 mutex_unlock(&phydev->lock); 383 } 384 385 #ifdef CONFIG_OF_MDIO 386 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) 387 { 388 u32 vdd, sd; 389 int i, j; 390 struct device *dev = &phydev->mdio.dev; 391 struct device_node *of_node = dev->of_node; 392 u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown); 393 394 if (!of_node) 395 return -ENODEV; 396 397 if (of_property_read_u32(of_node, "vsc8531,vddmac", &vdd)) 398 vdd = MSCC_VDDMAC_3300; 399 400 if (of_property_read_u32(of_node, "vsc8531,edge-slowdown", &sd)) 401 sd = 0; 402 403 for (i = 0; i < ARRAY_SIZE(edge_table); i++) 404 if (edge_table[i].vddmac == vdd) 405 for (j = 0; j < sd_array_size; j++) 406 if (edge_table[i].slowdown[j] == sd) 407 return (sd_array_size - j - 1); 408 409 return -EINVAL; 410 } 411 412 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, 413 char *led, 414 u32 default_mode) 415 { 416 struct vsc8531_private *priv = phydev->priv; 417 struct device *dev = &phydev->mdio.dev; 418 struct device_node *of_node = dev->of_node; 419 u32 led_mode; 420 int err; 421 422 if (!of_node) 423 return -ENODEV; 424 425 led_mode = default_mode; 426 err = of_property_read_u32(of_node, led, &led_mode); 427 if (!err && !(BIT(led_mode) & priv->supp_led_modes)) { 428 phydev_err(phydev, "DT %s invalid\n", led); 429 return -EINVAL; 430 } 431 432 return led_mode; 433 } 434 435 #else 436 static int vsc85xx_edge_rate_magic_get(struct phy_device *phydev) 437 { 438 return 0; 439 } 440 441 static int vsc85xx_dt_led_mode_get(struct phy_device *phydev, 442 char *led, 443 u8 default_mode) 444 { 445 return default_mode; 446 } 447 #endif /* CONFIG_OF_MDIO */ 448 449 static int vsc85xx_dt_led_modes_get(struct phy_device *phydev, 450 u32 *default_mode) 451 { 452 struct vsc8531_private *priv = phydev->priv; 453 char led_dt_prop[28]; 454 int i, ret; 455 456 for (i = 0; i < priv->nleds; i++) { 457 ret = sprintf(led_dt_prop, "vsc8531,led-%d-mode", i); 458 if (ret < 0) 459 return ret; 460 461 ret = vsc85xx_dt_led_mode_get(phydev, led_dt_prop, 462 default_mode[i]); 463 if (ret < 0) 464 return ret; 465 priv->leds_mode[i] = ret; 466 } 467 468 return 0; 469 } 470 471 static int vsc85xx_edge_rate_cntl_set(struct phy_device *phydev, u8 edge_rate) 472 { 473 int rc; 474 475 mutex_lock(&phydev->lock); 476 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, 477 MSCC_PHY_WOL_MAC_CONTROL, EDGE_RATE_CNTL_MASK, 478 edge_rate << EDGE_RATE_CNTL_POS); 479 mutex_unlock(&phydev->lock); 480 481 return rc; 482 } 483 484 static int vsc85xx_mac_if_set(struct phy_device *phydev, 485 phy_interface_t interface) 486 { 487 int rc; 488 u16 reg_val; 489 490 mutex_lock(&phydev->lock); 491 reg_val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); 492 reg_val &= ~(MAC_IF_SELECTION_MASK); 493 switch (interface) { 494 case PHY_INTERFACE_MODE_RGMII_TXID: 495 case PHY_INTERFACE_MODE_RGMII_RXID: 496 case PHY_INTERFACE_MODE_RGMII_ID: 497 case PHY_INTERFACE_MODE_RGMII: 498 reg_val |= (MAC_IF_SELECTION_RGMII << MAC_IF_SELECTION_POS); 499 break; 500 case PHY_INTERFACE_MODE_RMII: 501 reg_val |= (MAC_IF_SELECTION_RMII << MAC_IF_SELECTION_POS); 502 break; 503 case PHY_INTERFACE_MODE_MII: 504 case PHY_INTERFACE_MODE_GMII: 505 reg_val |= (MAC_IF_SELECTION_GMII << MAC_IF_SELECTION_POS); 506 break; 507 default: 508 rc = -EINVAL; 509 goto out_unlock; 510 } 511 rc = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, reg_val); 512 if (rc) 513 goto out_unlock; 514 515 rc = genphy_soft_reset(phydev); 516 517 out_unlock: 518 mutex_unlock(&phydev->lock); 519 520 return rc; 521 } 522 523 /* Set the RGMII RX and TX clock skews individually, according to the PHY 524 * interface type, to: 525 * * 0.2 ns (their default, and lowest, hardware value) if delays should 526 * not be enabled 527 * * 2.0 ns (which causes the data to be sampled at exactly half way between 528 * clock transitions at 1000 Mbps) if delays should be enabled 529 */ 530 static int vsc85xx_rgmii_set_skews(struct phy_device *phydev, u32 rgmii_cntl, 531 u16 rgmii_rx_delay_mask, 532 u16 rgmii_tx_delay_mask) 533 { 534 u16 rgmii_rx_delay_pos = ffs(rgmii_rx_delay_mask) - 1; 535 u16 rgmii_tx_delay_pos = ffs(rgmii_tx_delay_mask) - 1; 536 u16 reg_val = 0; 537 int rc; 538 539 mutex_lock(&phydev->lock); 540 541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || 542 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 543 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_rx_delay_pos; 544 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || 545 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 546 reg_val |= RGMII_CLK_DELAY_2_0_NS << rgmii_tx_delay_pos; 547 548 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, 549 rgmii_cntl, 550 rgmii_rx_delay_mask | rgmii_tx_delay_mask, 551 reg_val); 552 553 mutex_unlock(&phydev->lock); 554 555 return rc; 556 } 557 558 static int vsc85xx_default_config(struct phy_device *phydev) 559 { 560 int rc; 561 562 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 563 564 if (phy_interface_mode_is_rgmii(phydev->interface)) { 565 rc = vsc85xx_rgmii_set_skews(phydev, VSC8502_RGMII_CNTL, 566 VSC8502_RGMII_RX_DELAY_MASK, 567 VSC8502_RGMII_TX_DELAY_MASK); 568 if (rc) 569 return rc; 570 } 571 572 return 0; 573 } 574 575 static int vsc85xx_get_tunable(struct phy_device *phydev, 576 struct ethtool_tunable *tuna, void *data) 577 { 578 switch (tuna->id) { 579 case ETHTOOL_PHY_DOWNSHIFT: 580 return vsc85xx_downshift_get(phydev, (u8 *)data); 581 default: 582 return -EINVAL; 583 } 584 } 585 586 static int vsc85xx_set_tunable(struct phy_device *phydev, 587 struct ethtool_tunable *tuna, 588 const void *data) 589 { 590 switch (tuna->id) { 591 case ETHTOOL_PHY_DOWNSHIFT: 592 return vsc85xx_downshift_set(phydev, *(u8 *)data); 593 default: 594 return -EINVAL; 595 } 596 } 597 598 /* mdiobus lock should be locked when using this function */ 599 static void vsc85xx_tr_write(struct phy_device *phydev, u16 addr, u32 val) 600 { 601 __phy_write(phydev, MSCC_PHY_TR_MSB, val >> 16); 602 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); 603 __phy_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); 604 } 605 606 static int vsc8531_pre_init_seq_set(struct phy_device *phydev) 607 { 608 int rc; 609 static const struct reg_val init_seq[] = { 610 {0x0f90, 0x00688980}, 611 {0x0696, 0x00000003}, 612 {0x07fa, 0x0050100f}, 613 {0x1686, 0x00000004}, 614 }; 615 unsigned int i; 616 int oldpage; 617 618 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_STANDARD, 619 MSCC_PHY_EXT_CNTL_STATUS, SMI_BROADCAST_WR_EN, 620 SMI_BROADCAST_WR_EN); 621 if (rc < 0) 622 return rc; 623 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 624 MSCC_PHY_TEST_PAGE_24, 0, 0x0400); 625 if (rc < 0) 626 return rc; 627 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 628 MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00); 629 if (rc < 0) 630 return rc; 631 rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_TEST, 632 MSCC_PHY_TEST_PAGE_8, 0x8000, 0x8000); 633 if (rc < 0) 634 return rc; 635 636 mutex_lock(&phydev->lock); 637 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); 638 if (oldpage < 0) 639 goto out_unlock; 640 641 for (i = 0; i < ARRAY_SIZE(init_seq); i++) 642 vsc85xx_tr_write(phydev, init_seq[i].reg, init_seq[i].val); 643 644 out_unlock: 645 oldpage = phy_restore_page(phydev, oldpage, oldpage); 646 mutex_unlock(&phydev->lock); 647 648 return oldpage; 649 } 650 651 static int vsc85xx_eee_init_seq_set(struct phy_device *phydev) 652 { 653 static const struct reg_val init_eee[] = { 654 {0x0f82, 0x0012b00a}, 655 {0x1686, 0x00000004}, 656 {0x168c, 0x00d2c46f}, 657 {0x17a2, 0x00000620}, 658 {0x16a0, 0x00eeffdd}, 659 {0x16a6, 0x00071448}, 660 {0x16a4, 0x0013132f}, 661 {0x16a8, 0x00000000}, 662 {0x0ffc, 0x00c0a028}, 663 {0x0fe8, 0x0091b06c}, 664 {0x0fea, 0x00041600}, 665 {0x0f80, 0x00000af4}, 666 {0x0fec, 0x00901809}, 667 {0x0fee, 0x0000a6a1}, 668 {0x0ffe, 0x00b01007}, 669 {0x16b0, 0x00eeff00}, 670 {0x16b2, 0x00007000}, 671 {0x16b4, 0x00000814}, 672 }; 673 unsigned int i; 674 int oldpage; 675 676 mutex_lock(&phydev->lock); 677 oldpage = phy_select_page(phydev, MSCC_PHY_PAGE_TR); 678 if (oldpage < 0) 679 goto out_unlock; 680 681 for (i = 0; i < ARRAY_SIZE(init_eee); i++) 682 vsc85xx_tr_write(phydev, init_eee[i].reg, init_eee[i].val); 683 684 out_unlock: 685 oldpage = phy_restore_page(phydev, oldpage, oldpage); 686 mutex_unlock(&phydev->lock); 687 688 return oldpage; 689 } 690 691 /* phydev->bus->mdio_lock should be locked when using this function */ 692 static int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val) 693 { 694 struct vsc8531_private *priv = phydev->priv; 695 696 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { 697 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); 698 dump_stack(); 699 } 700 701 return __mdiobus_write(phydev->mdio.bus, priv->base_addr, regnum, val); 702 } 703 704 /* phydev->bus->mdio_lock should be locked when using this function */ 705 static int phy_base_read(struct phy_device *phydev, u32 regnum) 706 { 707 struct vsc8531_private *priv = phydev->priv; 708 709 if (unlikely(!mutex_is_locked(&phydev->mdio.bus->mdio_lock))) { 710 dev_err(&phydev->mdio.dev, "MDIO bus lock not held!\n"); 711 dump_stack(); 712 } 713 714 return __mdiobus_read(phydev->mdio.bus, priv->base_addr, regnum); 715 } 716 717 /* bus->mdio_lock should be locked when using this function */ 718 static void vsc8584_csr_write(struct phy_device *phydev, u16 addr, u32 val) 719 { 720 phy_base_write(phydev, MSCC_PHY_TR_MSB, val >> 16); 721 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); 722 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(addr)); 723 } 724 725 /* bus->mdio_lock should be locked when using this function */ 726 static int vsc8584_cmd(struct phy_device *phydev, u16 val) 727 { 728 unsigned long deadline; 729 u16 reg_val; 730 731 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 732 MSCC_PHY_PAGE_EXTENDED_GPIO); 733 734 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NCOMPLETED | val); 735 736 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 737 do { 738 reg_val = phy_base_read(phydev, MSCC_PHY_PROC_CMD); 739 } while (time_before(jiffies, deadline) && 740 (reg_val & PROC_CMD_NCOMPLETED) && 741 !(reg_val & PROC_CMD_FAILED)); 742 743 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 744 745 if (reg_val & PROC_CMD_FAILED) 746 return -EIO; 747 748 if (reg_val & PROC_CMD_NCOMPLETED) 749 return -ETIMEDOUT; 750 751 return 0; 752 } 753 754 /* bus->mdio_lock should be locked when using this function */ 755 static int vsc8584_micro_deassert_reset(struct phy_device *phydev, 756 bool patch_en) 757 { 758 u32 enable, release; 759 760 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 761 MSCC_PHY_PAGE_EXTENDED_GPIO); 762 763 enable = RUN_FROM_INT_ROM | MICRO_CLK_EN | DW8051_CLK_EN; 764 release = MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | 765 MICRO_CLK_EN; 766 767 if (patch_en) { 768 enable |= MICRO_PATCH_EN; 769 release |= MICRO_PATCH_EN; 770 771 /* Clear all patches */ 772 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); 773 } 774 775 /* Enable 8051 Micro clock; CLEAR/SET patch present; disable PRAM clock 776 * override and addr. auto-incr; operate at 125 MHz 777 */ 778 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, enable); 779 /* Release 8051 Micro SW reset */ 780 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, release); 781 782 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 783 784 return 0; 785 } 786 787 /* bus->mdio_lock should be locked when using this function */ 788 static int vsc8584_micro_assert_reset(struct phy_device *phydev) 789 { 790 int ret; 791 u16 reg; 792 793 ret = vsc8584_cmd(phydev, PROC_CMD_NOP); 794 if (ret) 795 return ret; 796 797 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 798 MSCC_PHY_PAGE_EXTENDED_GPIO); 799 800 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 801 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); 802 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 803 804 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); 805 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); 806 807 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 808 reg |= EN_PATCH_RAM_TRAP_ADDR(4); 809 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 810 811 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_NOP); 812 813 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); 814 reg &= ~MICRO_NSOFT_RESET; 815 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, reg); 816 817 phy_base_write(phydev, MSCC_PHY_PROC_CMD, PROC_CMD_MCB_ACCESS_MAC_CONF | 818 PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF | 819 PROC_CMD_READ); 820 821 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 822 reg &= ~EN_PATCH_RAM_TRAP_ADDR(4); 823 phy_base_write(phydev, MSCC_INT_MEM_CNTL, reg); 824 825 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 826 827 return 0; 828 } 829 830 /* bus->mdio_lock should be locked when using this function */ 831 static int vsc8584_get_fw_crc(struct phy_device *phydev, u16 start, u16 size, 832 u16 *crc) 833 { 834 int ret; 835 836 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 837 838 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_2, start); 839 phy_base_write(phydev, MSCC_PHY_VERIPHY_CNTL_3, size); 840 841 /* Start Micro command */ 842 ret = vsc8584_cmd(phydev, PROC_CMD_CRC16); 843 if (ret) 844 goto out; 845 846 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 847 848 *crc = phy_base_read(phydev, MSCC_PHY_VERIPHY_CNTL_2); 849 850 out: 851 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 852 853 return ret; 854 } 855 856 /* bus->mdio_lock should be locked when using this function */ 857 static int vsc8584_patch_fw(struct phy_device *phydev, 858 const struct firmware *fw) 859 { 860 int i, ret; 861 862 ret = vsc8584_micro_assert_reset(phydev); 863 if (ret) { 864 dev_err(&phydev->mdio.dev, 865 "%s: failed to assert reset of micro\n", __func__); 866 return ret; 867 } 868 869 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 870 MSCC_PHY_PAGE_EXTENDED_GPIO); 871 872 /* Hold 8051 Micro in SW Reset, Enable auto incr address and patch clock 873 * Disable the 8051 Micro clock 874 */ 875 phy_base_write(phydev, MSCC_DW8051_CNTL_STATUS, RUN_FROM_INT_ROM | 876 AUTOINC_ADDR | PATCH_RAM_CLK | MICRO_CLK_EN | 877 MICRO_CLK_DIVIDE(2)); 878 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | INT_MEM_WRITE_EN | 879 INT_MEM_DATA(2)); 880 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); 881 882 for (i = 0; i < fw->size; i++) 883 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_PRAM | 884 INT_MEM_WRITE_EN | fw->data[i]); 885 886 /* Clear internal memory access */ 887 phy_base_write(phydev, MSCC_INT_MEM_CNTL, READ_RAM); 888 889 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 890 891 return 0; 892 } 893 894 /* bus->mdio_lock should be locked when using this function */ 895 static bool vsc8574_is_serdes_init(struct phy_device *phydev) 896 { 897 u16 reg; 898 bool ret; 899 900 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 901 MSCC_PHY_PAGE_EXTENDED_GPIO); 902 903 reg = phy_base_read(phydev, MSCC_TRAP_ROM_ADDR(1)); 904 if (reg != 0x3eb7) { 905 ret = false; 906 goto out; 907 } 908 909 reg = phy_base_read(phydev, MSCC_PATCH_RAM_ADDR(1)); 910 if (reg != 0x4012) { 911 ret = false; 912 goto out; 913 } 914 915 reg = phy_base_read(phydev, MSCC_INT_MEM_CNTL); 916 if (reg != EN_PATCH_RAM_TRAP_ADDR(1)) { 917 ret = false; 918 goto out; 919 } 920 921 reg = phy_base_read(phydev, MSCC_DW8051_CNTL_STATUS); 922 if ((MICRO_NSOFT_RESET | RUN_FROM_INT_ROM | DW8051_CLK_EN | 923 MICRO_CLK_EN) != (reg & MSCC_DW8051_VLD_MASK)) { 924 ret = false; 925 goto out; 926 } 927 928 ret = true; 929 out: 930 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 931 932 return ret; 933 } 934 935 /* bus->mdio_lock should be locked when using this function */ 936 static int vsc8574_config_pre_init(struct phy_device *phydev) 937 { 938 static const struct reg_val pre_init1[] = { 939 {0x0fae, 0x000401bd}, 940 {0x0fac, 0x000f000f}, 941 {0x17a0, 0x00a0f147}, 942 {0x0fe4, 0x00052f54}, 943 {0x1792, 0x0027303d}, 944 {0x07fe, 0x00000704}, 945 {0x0fe0, 0x00060150}, 946 {0x0f82, 0x0012b00a}, 947 {0x0f80, 0x00000d74}, 948 {0x02e0, 0x00000012}, 949 {0x03a2, 0x00050208}, 950 {0x03b2, 0x00009186}, 951 {0x0fb0, 0x000e3700}, 952 {0x1688, 0x00049f81}, 953 {0x0fd2, 0x0000ffff}, 954 {0x168a, 0x00039fa2}, 955 {0x1690, 0x0020640b}, 956 {0x0258, 0x00002220}, 957 {0x025a, 0x00002a20}, 958 {0x025c, 0x00003060}, 959 {0x025e, 0x00003fa0}, 960 {0x03a6, 0x0000e0f0}, 961 {0x0f92, 0x00001489}, 962 {0x16a2, 0x00007000}, 963 {0x16a6, 0x00071448}, 964 {0x16a0, 0x00eeffdd}, 965 {0x0fe8, 0x0091b06c}, 966 {0x0fea, 0x00041600}, 967 {0x16b0, 0x00eeff00}, 968 {0x16b2, 0x00007000}, 969 {0x16b4, 0x00000814}, 970 {0x0f90, 0x00688980}, 971 {0x03a4, 0x0000d8f0}, 972 {0x0fc0, 0x00000400}, 973 {0x07fa, 0x0050100f}, 974 {0x0796, 0x00000003}, 975 {0x07f8, 0x00c3ff98}, 976 {0x0fa4, 0x0018292a}, 977 {0x168c, 0x00d2c46f}, 978 {0x17a2, 0x00000620}, 979 {0x16a4, 0x0013132f}, 980 {0x16a8, 0x00000000}, 981 {0x0ffc, 0x00c0a028}, 982 {0x0fec, 0x00901c09}, 983 {0x0fee, 0x0004a6a1}, 984 {0x0ffe, 0x00b01807}, 985 }; 986 static const struct reg_val pre_init2[] = { 987 {0x0486, 0x0008a518}, 988 {0x0488, 0x006dc696}, 989 {0x048a, 0x00000912}, 990 {0x048e, 0x00000db6}, 991 {0x049c, 0x00596596}, 992 {0x049e, 0x00000514}, 993 {0x04a2, 0x00410280}, 994 {0x04a4, 0x00000000}, 995 {0x04a6, 0x00000000}, 996 {0x04a8, 0x00000000}, 997 {0x04aa, 0x00000000}, 998 {0x04ae, 0x007df7dd}, 999 {0x04b0, 0x006d95d4}, 1000 {0x04b2, 0x00492410}, 1001 }; 1002 struct device *dev = &phydev->mdio.dev; 1003 const struct firmware *fw; 1004 unsigned int i; 1005 u16 crc, reg; 1006 bool serdes_init; 1007 int ret; 1008 1009 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1010 1011 /* all writes below are broadcasted to all PHYs in the same package */ 1012 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1013 reg |= SMI_BROADCAST_WR_EN; 1014 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1015 1016 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); 1017 1018 /* The below register writes are tweaking analog and electrical 1019 * configuration that were determined through characterization by PHY 1020 * engineers. These don't mean anything more than "these are the best 1021 * values". 1022 */ 1023 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); 1024 1025 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1026 1027 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); 1028 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); 1029 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); 1030 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); 1031 1032 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1033 reg |= 0x8000; 1034 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1035 1036 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1037 1038 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1039 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1040 1041 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); 1042 1043 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); 1044 1045 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1046 1047 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) 1048 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); 1049 1050 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1051 1052 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1053 reg &= ~0x8000; 1054 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1055 1056 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1057 1058 /* end of write broadcasting */ 1059 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1060 reg &= ~SMI_BROADCAST_WR_EN; 1061 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1062 1063 ret = request_firmware(&fw, MSCC_VSC8574_REVB_INT8051_FW, dev); 1064 if (ret) { 1065 dev_err(dev, "failed to load firmware %s, ret: %d\n", 1066 MSCC_VSC8574_REVB_INT8051_FW, ret); 1067 return ret; 1068 } 1069 1070 /* Add one byte to size for the one added by the patch_fw function */ 1071 ret = vsc8584_get_fw_crc(phydev, 1072 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, 1073 fw->size + 1, &crc); 1074 if (ret) 1075 goto out; 1076 1077 if (crc == MSCC_VSC8574_REVB_INT8051_FW_CRC) { 1078 serdes_init = vsc8574_is_serdes_init(phydev); 1079 1080 if (!serdes_init) { 1081 ret = vsc8584_micro_assert_reset(phydev); 1082 if (ret) { 1083 dev_err(dev, 1084 "%s: failed to assert reset of micro\n", 1085 __func__); 1086 goto out; 1087 } 1088 } 1089 } else { 1090 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n"); 1091 1092 serdes_init = false; 1093 1094 if (vsc8584_patch_fw(phydev, fw)) 1095 dev_warn(dev, 1096 "failed to patch FW, expect non-optimal device\n"); 1097 } 1098 1099 if (!serdes_init) { 1100 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1101 MSCC_PHY_PAGE_EXTENDED_GPIO); 1102 1103 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); 1104 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); 1105 phy_base_write(phydev, MSCC_INT_MEM_CNTL, 1106 EN_PATCH_RAM_TRAP_ADDR(1)); 1107 1108 vsc8584_micro_deassert_reset(phydev, false); 1109 1110 /* Add one byte to size for the one added by the patch_fw 1111 * function 1112 */ 1113 ret = vsc8584_get_fw_crc(phydev, 1114 MSCC_VSC8574_REVB_INT8051_FW_START_ADDR, 1115 fw->size + 1, &crc); 1116 if (ret) 1117 goto out; 1118 1119 if (crc != MSCC_VSC8574_REVB_INT8051_FW_CRC) 1120 dev_warn(dev, 1121 "FW CRC after patching is not the expected one, expect non-optimal device\n"); 1122 } 1123 1124 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1125 MSCC_PHY_PAGE_EXTENDED_GPIO); 1126 1127 ret = vsc8584_cmd(phydev, PROC_CMD_1588_DEFAULT_INIT | 1128 PROC_CMD_PHY_INIT); 1129 1130 out: 1131 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1132 1133 release_firmware(fw); 1134 1135 return ret; 1136 } 1137 1138 /* bus->mdio_lock should be locked when using this function */ 1139 static int vsc8584_config_pre_init(struct phy_device *phydev) 1140 { 1141 static const struct reg_val pre_init1[] = { 1142 {0x07fa, 0x0050100f}, 1143 {0x1688, 0x00049f81}, 1144 {0x0f90, 0x00688980}, 1145 {0x03a4, 0x0000d8f0}, 1146 {0x0fc0, 0x00000400}, 1147 {0x0f82, 0x0012b002}, 1148 {0x1686, 0x00000004}, 1149 {0x168c, 0x00d2c46f}, 1150 {0x17a2, 0x00000620}, 1151 {0x16a0, 0x00eeffdd}, 1152 {0x16a6, 0x00071448}, 1153 {0x16a4, 0x0013132f}, 1154 {0x16a8, 0x00000000}, 1155 {0x0ffc, 0x00c0a028}, 1156 {0x0fe8, 0x0091b06c}, 1157 {0x0fea, 0x00041600}, 1158 {0x0f80, 0x00fffaff}, 1159 {0x0fec, 0x00901809}, 1160 {0x0ffe, 0x00b01007}, 1161 {0x16b0, 0x00eeff00}, 1162 {0x16b2, 0x00007000}, 1163 {0x16b4, 0x00000814}, 1164 }; 1165 static const struct reg_val pre_init2[] = { 1166 {0x0486, 0x0008a518}, 1167 {0x0488, 0x006dc696}, 1168 {0x048a, 0x00000912}, 1169 }; 1170 const struct firmware *fw; 1171 struct device *dev = &phydev->mdio.dev; 1172 unsigned int i; 1173 u16 crc, reg; 1174 int ret; 1175 1176 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1177 1178 /* all writes below are broadcasted to all PHYs in the same package */ 1179 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1180 reg |= SMI_BROADCAST_WR_EN; 1181 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1182 1183 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); 1184 1185 reg = phy_base_read(phydev, MSCC_PHY_BYPASS_CONTROL); 1186 reg |= PARALLEL_DET_IGNORE_ADVERTISED; 1187 phy_base_write(phydev, MSCC_PHY_BYPASS_CONTROL, reg); 1188 1189 /* The below register writes are tweaking analog and electrical 1190 * configuration that were determined through characterization by PHY 1191 * engineers. These don't mean anything more than "these are the best 1192 * values". 1193 */ 1194 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_3); 1195 1196 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); 1197 1198 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1199 1200 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); 1201 1202 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1203 reg |= 0x8000; 1204 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1205 1206 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1207 1208 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); 1209 1210 reg = phy_base_read(phydev, MSCC_PHY_TR_MSB); 1211 reg &= ~0x007f; 1212 reg |= 0x0019; 1213 phy_base_write(phydev, MSCC_PHY_TR_MSB, reg); 1214 1215 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); 1216 1217 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1218 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1219 1220 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED_2); 1221 1222 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); 1223 1224 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1225 1226 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) 1227 vsc8584_csr_write(phydev, pre_init2[i].reg, pre_init2[i].val); 1228 1229 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1230 1231 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1232 reg &= ~0x8000; 1233 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1234 1235 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1236 1237 /* end of write broadcasting */ 1238 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1239 reg &= ~SMI_BROADCAST_WR_EN; 1240 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1241 1242 ret = request_firmware(&fw, MSCC_VSC8584_REVB_INT8051_FW, dev); 1243 if (ret) { 1244 dev_err(dev, "failed to load firmware %s, ret: %d\n", 1245 MSCC_VSC8584_REVB_INT8051_FW, ret); 1246 return ret; 1247 } 1248 1249 /* Add one byte to size for the one added by the patch_fw function */ 1250 ret = vsc8584_get_fw_crc(phydev, 1251 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, 1252 fw->size + 1, &crc); 1253 if (ret) 1254 goto out; 1255 1256 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) { 1257 dev_dbg(dev, "FW CRC is not the expected one, patching FW\n"); 1258 if (vsc8584_patch_fw(phydev, fw)) 1259 dev_warn(dev, 1260 "failed to patch FW, expect non-optimal device\n"); 1261 } 1262 1263 vsc8584_micro_deassert_reset(phydev, false); 1264 1265 /* Add one byte to size for the one added by the patch_fw function */ 1266 ret = vsc8584_get_fw_crc(phydev, 1267 MSCC_VSC8584_REVB_INT8051_FW_START_ADDR, 1268 fw->size + 1, &crc); 1269 if (ret) 1270 goto out; 1271 1272 if (crc != MSCC_VSC8584_REVB_INT8051_FW_CRC) 1273 dev_warn(dev, 1274 "FW CRC after patching is not the expected one, expect non-optimal device\n"); 1275 1276 ret = vsc8584_micro_assert_reset(phydev); 1277 if (ret) 1278 goto out; 1279 1280 vsc8584_micro_deassert_reset(phydev, true); 1281 1282 out: 1283 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1284 1285 release_firmware(fw); 1286 1287 return ret; 1288 } 1289 1290 /* Check if one PHY has already done the init of the parts common to all PHYs 1291 * in the Quad PHY package. 1292 */ 1293 static bool vsc8584_is_pkg_init(struct phy_device *phydev, bool reversed) 1294 { 1295 struct mdio_device **map = phydev->mdio.bus->mdio_map; 1296 struct vsc8531_private *vsc8531; 1297 struct phy_device *phy; 1298 int i, addr; 1299 1300 /* VSC8584 is a Quad PHY */ 1301 for (i = 0; i < 4; i++) { 1302 vsc8531 = phydev->priv; 1303 1304 if (reversed) 1305 addr = vsc8531->base_addr - i; 1306 else 1307 addr = vsc8531->base_addr + i; 1308 1309 if (!map[addr]) 1310 continue; 1311 1312 phy = container_of(map[addr], struct phy_device, mdio); 1313 1314 if ((phy->phy_id & phydev->drv->phy_id_mask) != 1315 (phydev->drv->phy_id & phydev->drv->phy_id_mask)) 1316 continue; 1317 1318 vsc8531 = phy->priv; 1319 1320 if (vsc8531 && vsc8531->pkg_init) 1321 return true; 1322 } 1323 1324 return false; 1325 } 1326 1327 static int vsc8584_config_init(struct phy_device *phydev) 1328 { 1329 struct vsc8531_private *vsc8531 = phydev->priv; 1330 u16 addr, val; 1331 int ret, i; 1332 1333 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1334 1335 mutex_lock(&phydev->mdio.bus->mdio_lock); 1336 1337 __mdiobus_write(phydev->mdio.bus, phydev->mdio.addr, 1338 MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 1339 addr = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, 1340 MSCC_PHY_EXT_PHY_CNTL_4); 1341 addr >>= PHY_CNTL_4_ADDR_POS; 1342 1343 val = __mdiobus_read(phydev->mdio.bus, phydev->mdio.addr, 1344 MSCC_PHY_ACTIPHY_CNTL); 1345 if (val & PHY_ADDR_REVERSED) 1346 vsc8531->base_addr = phydev->mdio.addr + addr; 1347 else 1348 vsc8531->base_addr = phydev->mdio.addr - addr; 1349 1350 /* Some parts of the init sequence are identical for every PHY in the 1351 * package. Some parts are modifying the GPIO register bank which is a 1352 * set of registers that are affecting all PHYs, a few resetting the 1353 * microprocessor common to all PHYs. The CRC check responsible of the 1354 * checking the firmware within the 8051 microprocessor can only be 1355 * accessed via the PHY whose internal address in the package is 0. 1356 * All PHYs' interrupts mask register has to be zeroed before enabling 1357 * any PHY's interrupt in this register. 1358 * For all these reasons, we need to do the init sequence once and only 1359 * once whatever is the first PHY in the package that is initialized and 1360 * do the correct init sequence for all PHYs that are package-critical 1361 * in this pre-init function. 1362 */ 1363 if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0)) { 1364 /* The following switch statement assumes that the lowest 1365 * nibble of the phy_id_mask is always 0. This works because 1366 * the lowest nibble of the PHY_ID's below are also 0. 1367 */ 1368 WARN_ON(phydev->drv->phy_id_mask & 0xf); 1369 1370 switch (phydev->phy_id & phydev->drv->phy_id_mask) { 1371 case PHY_ID_VSC8504: 1372 case PHY_ID_VSC8552: 1373 case PHY_ID_VSC8572: 1374 case PHY_ID_VSC8574: 1375 ret = vsc8574_config_pre_init(phydev); 1376 break; 1377 case PHY_ID_VSC856X: 1378 case PHY_ID_VSC8575: 1379 case PHY_ID_VSC8582: 1380 case PHY_ID_VSC8584: 1381 ret = vsc8584_config_pre_init(phydev); 1382 break; 1383 default: 1384 ret = -EINVAL; 1385 break; 1386 } 1387 1388 if (ret) 1389 goto err; 1390 } 1391 1392 vsc8531->pkg_init = true; 1393 1394 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1395 MSCC_PHY_PAGE_EXTENDED_GPIO); 1396 1397 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1398 val &= ~MAC_CFG_MASK; 1399 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) { 1400 val |= MAC_CFG_QSGMII; 1401 } else if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { 1402 val |= MAC_CFG_SGMII; 1403 } else if (phy_interface_is_rgmii(phydev)) { 1404 val |= MAC_CFG_RGMII; 1405 } else { 1406 ret = -EINVAL; 1407 goto err; 1408 } 1409 1410 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1411 if (ret) 1412 goto err; 1413 1414 if (!phy_interface_is_rgmii(phydev)) { 1415 val = PROC_CMD_MCB_ACCESS_MAC_CONF | PROC_CMD_RST_CONF_PORT | 1416 PROC_CMD_READ_MOD_WRITE_PORT; 1417 if (phydev->interface == PHY_INTERFACE_MODE_QSGMII) 1418 val |= PROC_CMD_QSGMII_MAC; 1419 else 1420 val |= PROC_CMD_SGMII_MAC; 1421 1422 ret = vsc8584_cmd(phydev, val); 1423 if (ret) 1424 goto err; 1425 1426 usleep_range(10000, 20000); 1427 } 1428 1429 /* Disable SerDes for 100Base-FX */ 1430 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1431 PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE | 1432 PROC_CMD_READ_MOD_WRITE_PORT | 1433 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_100BASE_FX); 1434 if (ret) 1435 goto err; 1436 1437 /* Disable SerDes for 1000Base-X */ 1438 ret = vsc8584_cmd(phydev, PROC_CMD_FIBER_MEDIA_CONF | 1439 PROC_CMD_FIBER_PORT(addr) | PROC_CMD_FIBER_DISABLE | 1440 PROC_CMD_READ_MOD_WRITE_PORT | 1441 PROC_CMD_RST_CONF_PORT | PROC_CMD_FIBER_1000BASE_X); 1442 if (ret) 1443 goto err; 1444 1445 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1446 1447 ret = vsc8584_macsec_init(phydev); 1448 if (ret) 1449 return ret; 1450 1451 phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1452 1453 val = phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_1); 1454 val &= ~(MEDIA_OP_MODE_MASK | VSC8584_MAC_IF_SELECTION_MASK); 1455 val |= (MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS) | 1456 (VSC8584_MAC_IF_SELECTION_SGMII << VSC8584_MAC_IF_SELECTION_POS); 1457 ret = phy_write(phydev, MSCC_PHY_EXT_PHY_CNTL_1, val); 1458 if (ret) 1459 return ret; 1460 1461 if (phy_interface_is_rgmii(phydev)) { 1462 ret = vsc85xx_rgmii_set_skews(phydev, VSC8572_RGMII_CNTL, 1463 VSC8572_RGMII_RX_DELAY_MASK, 1464 VSC8572_RGMII_TX_DELAY_MASK); 1465 if (ret) 1466 return ret; 1467 } 1468 1469 ret = genphy_soft_reset(phydev); 1470 if (ret) 1471 return ret; 1472 1473 for (i = 0; i < vsc8531->nleds; i++) { 1474 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1475 if (ret) 1476 return ret; 1477 } 1478 1479 return 0; 1480 1481 err: 1482 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1483 return ret; 1484 } 1485 1486 static irqreturn_t vsc8584_handle_interrupt(struct phy_device *phydev) 1487 { 1488 int irq_status; 1489 1490 irq_status = phy_read(phydev, MII_VSC85XX_INT_STATUS); 1491 if (irq_status < 0 || !(irq_status & MII_VSC85XX_INT_MASK_MASK)) 1492 return IRQ_NONE; 1493 1494 if (irq_status & MII_VSC85XX_INT_MASK_EXT) 1495 vsc8584_handle_macsec_interrupt(phydev); 1496 1497 if (irq_status & MII_VSC85XX_INT_MASK_LINK_CHG) 1498 phy_mac_interrupt(phydev); 1499 1500 return IRQ_HANDLED; 1501 } 1502 1503 static int vsc85xx_config_init(struct phy_device *phydev) 1504 { 1505 int rc, i, phy_id; 1506 struct vsc8531_private *vsc8531 = phydev->priv; 1507 1508 rc = vsc85xx_default_config(phydev); 1509 if (rc) 1510 return rc; 1511 1512 rc = vsc85xx_mac_if_set(phydev, phydev->interface); 1513 if (rc) 1514 return rc; 1515 1516 rc = vsc85xx_edge_rate_cntl_set(phydev, vsc8531->rate_magic); 1517 if (rc) 1518 return rc; 1519 1520 phy_id = phydev->drv->phy_id & phydev->drv->phy_id_mask; 1521 if (PHY_ID_VSC8531 == phy_id || PHY_ID_VSC8541 == phy_id || 1522 PHY_ID_VSC8530 == phy_id || PHY_ID_VSC8540 == phy_id) { 1523 rc = vsc8531_pre_init_seq_set(phydev); 1524 if (rc) 1525 return rc; 1526 } 1527 1528 rc = vsc85xx_eee_init_seq_set(phydev); 1529 if (rc) 1530 return rc; 1531 1532 for (i = 0; i < vsc8531->nleds; i++) { 1533 rc = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1534 if (rc) 1535 return rc; 1536 } 1537 1538 return 0; 1539 } 1540 1541 static int vsc8584_did_interrupt(struct phy_device *phydev) 1542 { 1543 int rc = 0; 1544 1545 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 1546 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 1547 1548 return (rc < 0) ? 0 : rc & MII_VSC85XX_INT_MASK_MASK; 1549 } 1550 1551 static int vsc8514_config_pre_init(struct phy_device *phydev) 1552 { 1553 /* These are the settings to override the silicon default 1554 * values to handle hardware performance of PHY. They 1555 * are set at Power-On state and remain until PHY Reset. 1556 */ 1557 static const struct reg_val pre_init1[] = { 1558 {0x0f90, 0x00688980}, 1559 {0x0786, 0x00000003}, 1560 {0x07fa, 0x0050100f}, 1561 {0x0f82, 0x0012b002}, 1562 {0x1686, 0x00000004}, 1563 {0x168c, 0x00d2c46f}, 1564 {0x17a2, 0x00000620}, 1565 {0x16a0, 0x00eeffdd}, 1566 {0x16a6, 0x00071448}, 1567 {0x16a4, 0x0013132f}, 1568 {0x16a8, 0x00000000}, 1569 {0x0ffc, 0x00c0a028}, 1570 {0x0fe8, 0x0091b06c}, 1571 {0x0fea, 0x00041600}, 1572 {0x0f80, 0x00fffaff}, 1573 {0x0fec, 0x00901809}, 1574 {0x0ffe, 0x00b01007}, 1575 {0x16b0, 0x00eeff00}, 1576 {0x16b2, 0x00007000}, 1577 {0x16b4, 0x00000814}, 1578 }; 1579 unsigned int i; 1580 u16 reg; 1581 1582 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1583 1584 /* all writes below are broadcasted to all PHYs in the same package */ 1585 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1586 reg |= SMI_BROADCAST_WR_EN; 1587 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1588 1589 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1590 1591 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1592 reg |= BIT(15); 1593 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1594 1595 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TR); 1596 1597 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) 1598 vsc8584_csr_write(phydev, pre_init1[i].reg, pre_init1[i].val); 1599 1600 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_TEST); 1601 1602 reg = phy_base_read(phydev, MSCC_PHY_TEST_PAGE_8); 1603 reg &= ~BIT(15); 1604 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_8, reg); 1605 1606 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1607 1608 reg = phy_base_read(phydev, MSCC_PHY_EXT_CNTL_STATUS); 1609 reg &= ~SMI_BROADCAST_WR_EN; 1610 phy_base_write(phydev, MSCC_PHY_EXT_CNTL_STATUS, reg); 1611 1612 return 0; 1613 } 1614 1615 static u32 vsc85xx_csr_ctrl_phy_read(struct phy_device *phydev, 1616 u32 target, u32 reg) 1617 { 1618 unsigned long deadline; 1619 u32 val, val_l, val_h; 1620 1621 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); 1622 1623 /* CSR registers are grouped under different Target IDs. 1624 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and 1625 * MSCC_EXT_PAGE_CSR_CNTL_19 registers. 1626 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 1627 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. 1628 */ 1629 1630 /* Setup the Target ID */ 1631 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, 1632 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2)); 1633 1634 /* Trigger CSR Action - Read into the CSR's */ 1635 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, 1636 MSCC_PHY_CSR_CNTL_19_CMD | MSCC_PHY_CSR_CNTL_19_READ | 1637 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | 1638 MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3)); 1639 1640 /* Wait for register access*/ 1641 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1642 do { 1643 usleep_range(500, 1000); 1644 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); 1645 } while (time_before(jiffies, deadline) && 1646 !(val & MSCC_PHY_CSR_CNTL_19_CMD)); 1647 1648 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) 1649 return 0xffffffff; 1650 1651 /* Read the Least Significant Word (LSW) (17) */ 1652 val_l = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_17); 1653 1654 /* Read the Most Significant Word (MSW) (18) */ 1655 val_h = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_18); 1656 1657 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1658 MSCC_PHY_PAGE_STANDARD); 1659 1660 return (val_h << 16) | val_l; 1661 } 1662 1663 static int vsc85xx_csr_ctrl_phy_write(struct phy_device *phydev, 1664 u32 target, u32 reg, u32 val) 1665 { 1666 unsigned long deadline; 1667 1668 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_CSR_CNTL); 1669 1670 /* CSR registers are grouped under different Target IDs. 1671 * 6-bit Target_ID is split between MSCC_EXT_PAGE_CSR_CNTL_20 and 1672 * MSCC_EXT_PAGE_CSR_CNTL_19 registers. 1673 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 1674 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. 1675 */ 1676 1677 /* Setup the Target ID */ 1678 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_20, 1679 MSCC_PHY_CSR_CNTL_20_TARGET(target >> 2)); 1680 1681 /* Write the Least Significant Word (LSW) (17) */ 1682 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_17, (u16)val); 1683 1684 /* Write the Most Significant Word (MSW) (18) */ 1685 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_18, (u16)(val >> 16)); 1686 1687 /* Trigger CSR Action - Write into the CSR's */ 1688 phy_base_write(phydev, MSCC_EXT_PAGE_CSR_CNTL_19, 1689 MSCC_PHY_CSR_CNTL_19_CMD | 1690 MSCC_PHY_CSR_CNTL_19_REG_ADDR(reg) | 1691 MSCC_PHY_CSR_CNTL_19_TARGET(target & 0x3)); 1692 1693 /* Wait for register access */ 1694 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1695 do { 1696 usleep_range(500, 1000); 1697 val = phy_base_read(phydev, MSCC_EXT_PAGE_CSR_CNTL_19); 1698 } while (time_before(jiffies, deadline) && 1699 !(val & MSCC_PHY_CSR_CNTL_19_CMD)); 1700 1701 if (!(val & MSCC_PHY_CSR_CNTL_19_CMD)) 1702 return -ETIMEDOUT; 1703 1704 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1705 MSCC_PHY_PAGE_STANDARD); 1706 1707 return 0; 1708 } 1709 1710 static int __phy_write_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb, 1711 u32 op) 1712 { 1713 unsigned long deadline; 1714 u32 val; 1715 int ret; 1716 1717 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, reg, 1718 op | (1 << mcb)); 1719 if (ret) 1720 return -EINVAL; 1721 1722 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1723 do { 1724 usleep_range(500, 1000); 1725 val = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, reg); 1726 1727 if (val == 0xffffffff) 1728 return -EIO; 1729 1730 } while (time_before(jiffies, deadline) && (val & op)); 1731 1732 if (val & op) 1733 return -ETIMEDOUT; 1734 1735 return 0; 1736 } 1737 1738 /* Trigger a read to the spcified MCB */ 1739 static int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) 1740 { 1741 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_READ); 1742 } 1743 1744 /* Trigger a write to the spcified MCB */ 1745 static int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb) 1746 { 1747 return __phy_write_mcb_s6g(phydev, reg, mcb, PHY_MCB_S6G_WRITE); 1748 } 1749 1750 static int vsc8514_config_init(struct phy_device *phydev) 1751 { 1752 struct vsc8531_private *vsc8531 = phydev->priv; 1753 unsigned long deadline; 1754 u16 val, addr; 1755 int ret, i; 1756 u32 reg; 1757 1758 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; 1759 1760 mutex_lock(&phydev->mdio.bus->mdio_lock); 1761 1762 __phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_EXTENDED); 1763 1764 addr = __phy_read(phydev, MSCC_PHY_EXT_PHY_CNTL_4); 1765 addr >>= PHY_CNTL_4_ADDR_POS; 1766 1767 val = __phy_read(phydev, MSCC_PHY_ACTIPHY_CNTL); 1768 1769 if (val & PHY_ADDR_REVERSED) 1770 vsc8531->base_addr = phydev->mdio.addr + addr; 1771 else 1772 vsc8531->base_addr = phydev->mdio.addr - addr; 1773 1774 /* Some parts of the init sequence are identical for every PHY in the 1775 * package. Some parts are modifying the GPIO register bank which is a 1776 * set of registers that are affecting all PHYs, a few resetting the 1777 * microprocessor common to all PHYs. 1778 * All PHYs' interrupts mask register has to be zeroed before enabling 1779 * any PHY's interrupt in this register. 1780 * For all these reasons, we need to do the init sequence once and only 1781 * once whatever is the first PHY in the package that is initialized and 1782 * do the correct init sequence for all PHYs that are package-critical 1783 * in this pre-init function. 1784 */ 1785 if (!vsc8584_is_pkg_init(phydev, val & PHY_ADDR_REVERSED ? 1 : 0)) 1786 vsc8514_config_pre_init(phydev); 1787 1788 vsc8531->pkg_init = true; 1789 1790 phy_base_write(phydev, MSCC_EXT_PAGE_ACCESS, 1791 MSCC_PHY_PAGE_EXTENDED_GPIO); 1792 1793 val = phy_base_read(phydev, MSCC_PHY_MAC_CFG_FASTLINK); 1794 1795 val &= ~MAC_CFG_MASK; 1796 val |= MAC_CFG_QSGMII; 1797 ret = phy_base_write(phydev, MSCC_PHY_MAC_CFG_FASTLINK, val); 1798 1799 if (ret) 1800 goto err; 1801 1802 ret = vsc8584_cmd(phydev, 1803 PROC_CMD_MCB_ACCESS_MAC_CONF | 1804 PROC_CMD_RST_CONF_PORT | 1805 PROC_CMD_READ_MOD_WRITE_PORT | PROC_CMD_QSGMII_MAC); 1806 if (ret) 1807 goto err; 1808 1809 /* 6g mcb */ 1810 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); 1811 /* lcpll mcb */ 1812 phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); 1813 /* pll5gcfg0 */ 1814 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1815 PHY_S6G_PLL5G_CFG0, 0x7036f145); 1816 if (ret) 1817 goto err; 1818 1819 phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); 1820 /* pllcfg */ 1821 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1822 PHY_S6G_PLL_CFG, 1823 (3 << PHY_S6G_PLL_ENA_OFFS_POS) | 1824 (120 << PHY_S6G_PLL_FSM_CTRL_DATA_POS) 1825 | (0 << PHY_S6G_PLL_FSM_ENA_POS)); 1826 if (ret) 1827 goto err; 1828 1829 /* commoncfg */ 1830 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1831 PHY_S6G_COMMON_CFG, 1832 (0 << PHY_S6G_SYS_RST_POS) | 1833 (0 << PHY_S6G_ENA_LANE_POS) | 1834 (0 << PHY_S6G_ENA_LOOP_POS) | 1835 (0 << PHY_S6G_QRATE_POS) | 1836 (3 << PHY_S6G_IF_MODE_POS)); 1837 if (ret) 1838 goto err; 1839 1840 /* misccfg */ 1841 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1842 PHY_S6G_MISC_CFG, 1); 1843 if (ret) 1844 goto err; 1845 1846 /* gpcfg */ 1847 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1848 PHY_S6G_GPC_CFG, 768); 1849 if (ret) 1850 goto err; 1851 1852 phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0); 1853 1854 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1855 do { 1856 usleep_range(500, 1000); 1857 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 1858 0); /* read 6G MCB into CSRs */ 1859 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, 1860 PHY_S6G_PLL_STATUS); 1861 if (reg == 0xffffffff) { 1862 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1863 return -EIO; 1864 } 1865 1866 } while (time_before(jiffies, deadline) && (reg & BIT(12))); 1867 1868 if (reg & BIT(12)) { 1869 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1870 return -ETIMEDOUT; 1871 } 1872 1873 /* misccfg */ 1874 ret = vsc85xx_csr_ctrl_phy_write(phydev, PHY_MCB_TARGET, 1875 PHY_S6G_MISC_CFG, 0); 1876 if (ret) 1877 goto err; 1878 1879 phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); 1880 1881 deadline = jiffies + msecs_to_jiffies(PROC_CMD_NCOMPLETED_TIMEOUT_MS); 1882 do { 1883 usleep_range(500, 1000); 1884 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 1885 0); /* read 6G MCB into CSRs */ 1886 reg = vsc85xx_csr_ctrl_phy_read(phydev, PHY_MCB_TARGET, 1887 PHY_S6G_IB_STATUS0); 1888 if (reg == 0xffffffff) { 1889 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1890 return -EIO; 1891 } 1892 1893 } while (time_before(jiffies, deadline) && !(reg & BIT(8))); 1894 1895 if (!(reg & BIT(8))) { 1896 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1897 return -ETIMEDOUT; 1898 } 1899 1900 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1901 1902 ret = phy_write(phydev, MSCC_EXT_PAGE_ACCESS, MSCC_PHY_PAGE_STANDARD); 1903 1904 if (ret) 1905 return ret; 1906 1907 ret = phy_modify(phydev, MSCC_PHY_EXT_PHY_CNTL_1, MEDIA_OP_MODE_MASK, 1908 MEDIA_OP_MODE_COPPER << MEDIA_OP_MODE_POS); 1909 1910 if (ret) 1911 return ret; 1912 1913 ret = genphy_soft_reset(phydev); 1914 1915 if (ret) 1916 return ret; 1917 1918 for (i = 0; i < vsc8531->nleds; i++) { 1919 ret = vsc85xx_led_cntl_set(phydev, i, vsc8531->leds_mode[i]); 1920 if (ret) 1921 return ret; 1922 } 1923 1924 return ret; 1925 1926 err: 1927 mutex_unlock(&phydev->mdio.bus->mdio_lock); 1928 return ret; 1929 } 1930 1931 static int vsc85xx_ack_interrupt(struct phy_device *phydev) 1932 { 1933 int rc = 0; 1934 1935 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) 1936 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 1937 1938 return (rc < 0) ? rc : 0; 1939 } 1940 1941 static int vsc85xx_config_intr(struct phy_device *phydev) 1942 { 1943 int rc; 1944 1945 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { 1946 vsc8584_config_macsec_intr(phydev); 1947 1948 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 1949 MII_VSC85XX_INT_MASK_MASK); 1950 } else { 1951 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); 1952 if (rc < 0) 1953 return rc; 1954 rc = phy_read(phydev, MII_VSC85XX_INT_STATUS); 1955 } 1956 1957 return rc; 1958 } 1959 1960 static int vsc85xx_config_aneg(struct phy_device *phydev) 1961 { 1962 int rc; 1963 1964 rc = vsc85xx_mdix_set(phydev, phydev->mdix_ctrl); 1965 if (rc < 0) 1966 return rc; 1967 1968 return genphy_config_aneg(phydev); 1969 } 1970 1971 static int vsc85xx_read_status(struct phy_device *phydev) 1972 { 1973 int rc; 1974 1975 rc = vsc85xx_mdix_get(phydev, &phydev->mdix); 1976 if (rc < 0) 1977 return rc; 1978 1979 return genphy_read_status(phydev); 1980 } 1981 1982 static int vsc8514_probe(struct phy_device *phydev) 1983 { 1984 struct vsc8531_private *vsc8531; 1985 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 1986 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 1987 VSC8531_DUPLEX_COLLISION}; 1988 1989 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 1990 if (!vsc8531) 1991 return -ENOMEM; 1992 1993 phydev->priv = vsc8531; 1994 1995 vsc8531->nleds = 4; 1996 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES; 1997 vsc8531->hw_stats = vsc85xx_hw_stats; 1998 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats); 1999 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2000 sizeof(u64), GFP_KERNEL); 2001 if (!vsc8531->stats) 2002 return -ENOMEM; 2003 2004 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2005 } 2006 2007 static int vsc8574_probe(struct phy_device *phydev) 2008 { 2009 struct vsc8531_private *vsc8531; 2010 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 2011 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 2012 VSC8531_DUPLEX_COLLISION}; 2013 2014 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2015 if (!vsc8531) 2016 return -ENOMEM; 2017 2018 phydev->priv = vsc8531; 2019 2020 vsc8531->nleds = 4; 2021 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES; 2022 vsc8531->hw_stats = vsc8584_hw_stats; 2023 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats); 2024 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2025 sizeof(u64), GFP_KERNEL); 2026 if (!vsc8531->stats) 2027 return -ENOMEM; 2028 2029 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2030 } 2031 2032 static int vsc8584_probe(struct phy_device *phydev) 2033 { 2034 struct vsc8531_private *vsc8531; 2035 u32 default_mode[4] = {VSC8531_LINK_1000_ACTIVITY, 2036 VSC8531_LINK_100_ACTIVITY, VSC8531_LINK_ACTIVITY, 2037 VSC8531_DUPLEX_COLLISION}; 2038 2039 if ((phydev->phy_id & MSCC_DEV_REV_MASK) != VSC8584_REVB) { 2040 dev_err(&phydev->mdio.dev, "Only VSC8584 revB is supported.\n"); 2041 return -ENOTSUPP; 2042 } 2043 2044 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2045 if (!vsc8531) 2046 return -ENOMEM; 2047 2048 phydev->priv = vsc8531; 2049 2050 vsc8531->nleds = 4; 2051 vsc8531->supp_led_modes = VSC8584_SUPP_LED_MODES; 2052 vsc8531->hw_stats = vsc8584_hw_stats; 2053 vsc8531->nstats = ARRAY_SIZE(vsc8584_hw_stats); 2054 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2055 sizeof(u64), GFP_KERNEL); 2056 if (!vsc8531->stats) 2057 return -ENOMEM; 2058 2059 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2060 } 2061 2062 static int vsc85xx_probe(struct phy_device *phydev) 2063 { 2064 struct vsc8531_private *vsc8531; 2065 int rate_magic; 2066 u32 default_mode[2] = {VSC8531_LINK_1000_ACTIVITY, 2067 VSC8531_LINK_100_ACTIVITY}; 2068 2069 rate_magic = vsc85xx_edge_rate_magic_get(phydev); 2070 if (rate_magic < 0) 2071 return rate_magic; 2072 2073 vsc8531 = devm_kzalloc(&phydev->mdio.dev, sizeof(*vsc8531), GFP_KERNEL); 2074 if (!vsc8531) 2075 return -ENOMEM; 2076 2077 phydev->priv = vsc8531; 2078 2079 vsc8531->rate_magic = rate_magic; 2080 vsc8531->nleds = 2; 2081 vsc8531->supp_led_modes = VSC85XX_SUPP_LED_MODES; 2082 vsc8531->hw_stats = vsc85xx_hw_stats; 2083 vsc8531->nstats = ARRAY_SIZE(vsc85xx_hw_stats); 2084 vsc8531->stats = devm_kcalloc(&phydev->mdio.dev, vsc8531->nstats, 2085 sizeof(u64), GFP_KERNEL); 2086 if (!vsc8531->stats) 2087 return -ENOMEM; 2088 2089 return vsc85xx_dt_led_modes_get(phydev, default_mode); 2090 } 2091 2092 /* Microsemi VSC85xx PHYs */ 2093 static struct phy_driver vsc85xx_driver[] = { 2094 { 2095 .phy_id = PHY_ID_VSC8502, 2096 .name = "Microsemi GE VSC8502 SyncE", 2097 .phy_id_mask = 0xfffffff0, 2098 /* PHY_BASIC_FEATURES */ 2099 .soft_reset = &genphy_soft_reset, 2100 .config_init = &vsc85xx_config_init, 2101 .config_aneg = &vsc85xx_config_aneg, 2102 .read_status = &vsc85xx_read_status, 2103 .ack_interrupt = &vsc85xx_ack_interrupt, 2104 .config_intr = &vsc85xx_config_intr, 2105 .suspend = &genphy_suspend, 2106 .resume = &genphy_resume, 2107 .probe = &vsc85xx_probe, 2108 .set_wol = &vsc85xx_wol_set, 2109 .get_wol = &vsc85xx_wol_get, 2110 .get_tunable = &vsc85xx_get_tunable, 2111 .set_tunable = &vsc85xx_set_tunable, 2112 .read_page = &vsc85xx_phy_read_page, 2113 .write_page = &vsc85xx_phy_write_page, 2114 .get_sset_count = &vsc85xx_get_sset_count, 2115 .get_strings = &vsc85xx_get_strings, 2116 .get_stats = &vsc85xx_get_stats, 2117 }, 2118 { 2119 .phy_id = PHY_ID_VSC8504, 2120 .name = "Microsemi GE VSC8504 SyncE", 2121 .phy_id_mask = 0xfffffff0, 2122 /* PHY_GBIT_FEATURES */ 2123 .soft_reset = &genphy_soft_reset, 2124 .config_init = &vsc8584_config_init, 2125 .config_aneg = &vsc85xx_config_aneg, 2126 .aneg_done = &genphy_aneg_done, 2127 .read_status = &vsc85xx_read_status, 2128 .ack_interrupt = &vsc85xx_ack_interrupt, 2129 .config_intr = &vsc85xx_config_intr, 2130 .did_interrupt = &vsc8584_did_interrupt, 2131 .suspend = &genphy_suspend, 2132 .resume = &genphy_resume, 2133 .probe = &vsc8574_probe, 2134 .set_wol = &vsc85xx_wol_set, 2135 .get_wol = &vsc85xx_wol_get, 2136 .get_tunable = &vsc85xx_get_tunable, 2137 .set_tunable = &vsc85xx_set_tunable, 2138 .read_page = &vsc85xx_phy_read_page, 2139 .write_page = &vsc85xx_phy_write_page, 2140 .get_sset_count = &vsc85xx_get_sset_count, 2141 .get_strings = &vsc85xx_get_strings, 2142 .get_stats = &vsc85xx_get_stats, 2143 }, 2144 { 2145 .phy_id = PHY_ID_VSC8514, 2146 .name = "Microsemi GE VSC8514 SyncE", 2147 .phy_id_mask = 0xfffffff0, 2148 .soft_reset = &genphy_soft_reset, 2149 .config_init = &vsc8514_config_init, 2150 .config_aneg = &vsc85xx_config_aneg, 2151 .read_status = &vsc85xx_read_status, 2152 .ack_interrupt = &vsc85xx_ack_interrupt, 2153 .config_intr = &vsc85xx_config_intr, 2154 .suspend = &genphy_suspend, 2155 .resume = &genphy_resume, 2156 .probe = &vsc8514_probe, 2157 .set_wol = &vsc85xx_wol_set, 2158 .get_wol = &vsc85xx_wol_get, 2159 .get_tunable = &vsc85xx_get_tunable, 2160 .set_tunable = &vsc85xx_set_tunable, 2161 .read_page = &vsc85xx_phy_read_page, 2162 .write_page = &vsc85xx_phy_write_page, 2163 .get_sset_count = &vsc85xx_get_sset_count, 2164 .get_strings = &vsc85xx_get_strings, 2165 .get_stats = &vsc85xx_get_stats, 2166 }, 2167 { 2168 .phy_id = PHY_ID_VSC8530, 2169 .name = "Microsemi FE VSC8530", 2170 .phy_id_mask = 0xfffffff0, 2171 /* PHY_BASIC_FEATURES */ 2172 .soft_reset = &genphy_soft_reset, 2173 .config_init = &vsc85xx_config_init, 2174 .config_aneg = &vsc85xx_config_aneg, 2175 .read_status = &vsc85xx_read_status, 2176 .ack_interrupt = &vsc85xx_ack_interrupt, 2177 .config_intr = &vsc85xx_config_intr, 2178 .suspend = &genphy_suspend, 2179 .resume = &genphy_resume, 2180 .probe = &vsc85xx_probe, 2181 .set_wol = &vsc85xx_wol_set, 2182 .get_wol = &vsc85xx_wol_get, 2183 .get_tunable = &vsc85xx_get_tunable, 2184 .set_tunable = &vsc85xx_set_tunable, 2185 .read_page = &vsc85xx_phy_read_page, 2186 .write_page = &vsc85xx_phy_write_page, 2187 .get_sset_count = &vsc85xx_get_sset_count, 2188 .get_strings = &vsc85xx_get_strings, 2189 .get_stats = &vsc85xx_get_stats, 2190 }, 2191 { 2192 .phy_id = PHY_ID_VSC8531, 2193 .name = "Microsemi VSC8531", 2194 .phy_id_mask = 0xfffffff0, 2195 /* PHY_GBIT_FEATURES */ 2196 .soft_reset = &genphy_soft_reset, 2197 .config_init = &vsc85xx_config_init, 2198 .config_aneg = &vsc85xx_config_aneg, 2199 .read_status = &vsc85xx_read_status, 2200 .ack_interrupt = &vsc85xx_ack_interrupt, 2201 .config_intr = &vsc85xx_config_intr, 2202 .suspend = &genphy_suspend, 2203 .resume = &genphy_resume, 2204 .probe = &vsc85xx_probe, 2205 .set_wol = &vsc85xx_wol_set, 2206 .get_wol = &vsc85xx_wol_get, 2207 .get_tunable = &vsc85xx_get_tunable, 2208 .set_tunable = &vsc85xx_set_tunable, 2209 .read_page = &vsc85xx_phy_read_page, 2210 .write_page = &vsc85xx_phy_write_page, 2211 .get_sset_count = &vsc85xx_get_sset_count, 2212 .get_strings = &vsc85xx_get_strings, 2213 .get_stats = &vsc85xx_get_stats, 2214 }, 2215 { 2216 .phy_id = PHY_ID_VSC8540, 2217 .name = "Microsemi FE VSC8540 SyncE", 2218 .phy_id_mask = 0xfffffff0, 2219 /* PHY_BASIC_FEATURES */ 2220 .soft_reset = &genphy_soft_reset, 2221 .config_init = &vsc85xx_config_init, 2222 .config_aneg = &vsc85xx_config_aneg, 2223 .read_status = &vsc85xx_read_status, 2224 .ack_interrupt = &vsc85xx_ack_interrupt, 2225 .config_intr = &vsc85xx_config_intr, 2226 .suspend = &genphy_suspend, 2227 .resume = &genphy_resume, 2228 .probe = &vsc85xx_probe, 2229 .set_wol = &vsc85xx_wol_set, 2230 .get_wol = &vsc85xx_wol_get, 2231 .get_tunable = &vsc85xx_get_tunable, 2232 .set_tunable = &vsc85xx_set_tunable, 2233 .read_page = &vsc85xx_phy_read_page, 2234 .write_page = &vsc85xx_phy_write_page, 2235 .get_sset_count = &vsc85xx_get_sset_count, 2236 .get_strings = &vsc85xx_get_strings, 2237 .get_stats = &vsc85xx_get_stats, 2238 }, 2239 { 2240 .phy_id = PHY_ID_VSC8541, 2241 .name = "Microsemi VSC8541 SyncE", 2242 .phy_id_mask = 0xfffffff0, 2243 /* PHY_GBIT_FEATURES */ 2244 .soft_reset = &genphy_soft_reset, 2245 .config_init = &vsc85xx_config_init, 2246 .config_aneg = &vsc85xx_config_aneg, 2247 .read_status = &vsc85xx_read_status, 2248 .ack_interrupt = &vsc85xx_ack_interrupt, 2249 .config_intr = &vsc85xx_config_intr, 2250 .suspend = &genphy_suspend, 2251 .resume = &genphy_resume, 2252 .probe = &vsc85xx_probe, 2253 .set_wol = &vsc85xx_wol_set, 2254 .get_wol = &vsc85xx_wol_get, 2255 .get_tunable = &vsc85xx_get_tunable, 2256 .set_tunable = &vsc85xx_set_tunable, 2257 .read_page = &vsc85xx_phy_read_page, 2258 .write_page = &vsc85xx_phy_write_page, 2259 .get_sset_count = &vsc85xx_get_sset_count, 2260 .get_strings = &vsc85xx_get_strings, 2261 .get_stats = &vsc85xx_get_stats, 2262 }, 2263 { 2264 .phy_id = PHY_ID_VSC8552, 2265 .name = "Microsemi GE VSC8552 SyncE", 2266 .phy_id_mask = 0xfffffff0, 2267 /* PHY_GBIT_FEATURES */ 2268 .soft_reset = &genphy_soft_reset, 2269 .config_init = &vsc8584_config_init, 2270 .config_aneg = &vsc85xx_config_aneg, 2271 .read_status = &vsc85xx_read_status, 2272 .ack_interrupt = &vsc85xx_ack_interrupt, 2273 .config_intr = &vsc85xx_config_intr, 2274 .did_interrupt = &vsc8584_did_interrupt, 2275 .suspend = &genphy_suspend, 2276 .resume = &genphy_resume, 2277 .probe = &vsc8574_probe, 2278 .set_wol = &vsc85xx_wol_set, 2279 .get_wol = &vsc85xx_wol_get, 2280 .get_tunable = &vsc85xx_get_tunable, 2281 .set_tunable = &vsc85xx_set_tunable, 2282 .read_page = &vsc85xx_phy_read_page, 2283 .write_page = &vsc85xx_phy_write_page, 2284 .get_sset_count = &vsc85xx_get_sset_count, 2285 .get_strings = &vsc85xx_get_strings, 2286 .get_stats = &vsc85xx_get_stats, 2287 }, 2288 { 2289 .phy_id = PHY_ID_VSC856X, 2290 .name = "Microsemi GE VSC856X SyncE", 2291 .phy_id_mask = 0xfffffff0, 2292 /* PHY_GBIT_FEATURES */ 2293 .soft_reset = &genphy_soft_reset, 2294 .config_init = &vsc8584_config_init, 2295 .config_aneg = &vsc85xx_config_aneg, 2296 .read_status = &vsc85xx_read_status, 2297 .ack_interrupt = &vsc85xx_ack_interrupt, 2298 .config_intr = &vsc85xx_config_intr, 2299 .did_interrupt = &vsc8584_did_interrupt, 2300 .suspend = &genphy_suspend, 2301 .resume = &genphy_resume, 2302 .probe = &vsc8584_probe, 2303 .get_tunable = &vsc85xx_get_tunable, 2304 .set_tunable = &vsc85xx_set_tunable, 2305 .read_page = &vsc85xx_phy_read_page, 2306 .write_page = &vsc85xx_phy_write_page, 2307 .get_sset_count = &vsc85xx_get_sset_count, 2308 .get_strings = &vsc85xx_get_strings, 2309 .get_stats = &vsc85xx_get_stats, 2310 }, 2311 { 2312 .phy_id = PHY_ID_VSC8572, 2313 .name = "Microsemi GE VSC8572 SyncE", 2314 .phy_id_mask = 0xfffffff0, 2315 /* PHY_GBIT_FEATURES */ 2316 .soft_reset = &genphy_soft_reset, 2317 .config_init = &vsc8584_config_init, 2318 .config_aneg = &vsc85xx_config_aneg, 2319 .aneg_done = &genphy_aneg_done, 2320 .read_status = &vsc85xx_read_status, 2321 .handle_interrupt = &vsc8584_handle_interrupt, 2322 .ack_interrupt = &vsc85xx_ack_interrupt, 2323 .config_intr = &vsc85xx_config_intr, 2324 .did_interrupt = &vsc8584_did_interrupt, 2325 .suspend = &genphy_suspend, 2326 .resume = &genphy_resume, 2327 .probe = &vsc8574_probe, 2328 .set_wol = &vsc85xx_wol_set, 2329 .get_wol = &vsc85xx_wol_get, 2330 .get_tunable = &vsc85xx_get_tunable, 2331 .set_tunable = &vsc85xx_set_tunable, 2332 .read_page = &vsc85xx_phy_read_page, 2333 .write_page = &vsc85xx_phy_write_page, 2334 .get_sset_count = &vsc85xx_get_sset_count, 2335 .get_strings = &vsc85xx_get_strings, 2336 .get_stats = &vsc85xx_get_stats, 2337 }, 2338 { 2339 .phy_id = PHY_ID_VSC8574, 2340 .name = "Microsemi GE VSC8574 SyncE", 2341 .phy_id_mask = 0xfffffff0, 2342 /* PHY_GBIT_FEATURES */ 2343 .soft_reset = &genphy_soft_reset, 2344 .config_init = &vsc8584_config_init, 2345 .config_aneg = &vsc85xx_config_aneg, 2346 .aneg_done = &genphy_aneg_done, 2347 .read_status = &vsc85xx_read_status, 2348 .ack_interrupt = &vsc85xx_ack_interrupt, 2349 .config_intr = &vsc85xx_config_intr, 2350 .did_interrupt = &vsc8584_did_interrupt, 2351 .suspend = &genphy_suspend, 2352 .resume = &genphy_resume, 2353 .probe = &vsc8574_probe, 2354 .set_wol = &vsc85xx_wol_set, 2355 .get_wol = &vsc85xx_wol_get, 2356 .get_tunable = &vsc85xx_get_tunable, 2357 .set_tunable = &vsc85xx_set_tunable, 2358 .read_page = &vsc85xx_phy_read_page, 2359 .write_page = &vsc85xx_phy_write_page, 2360 .get_sset_count = &vsc85xx_get_sset_count, 2361 .get_strings = &vsc85xx_get_strings, 2362 .get_stats = &vsc85xx_get_stats, 2363 }, 2364 { 2365 .phy_id = PHY_ID_VSC8575, 2366 .name = "Microsemi GE VSC8575 SyncE", 2367 .phy_id_mask = 0xfffffff0, 2368 /* PHY_GBIT_FEATURES */ 2369 .soft_reset = &genphy_soft_reset, 2370 .config_init = &vsc8584_config_init, 2371 .config_aneg = &vsc85xx_config_aneg, 2372 .aneg_done = &genphy_aneg_done, 2373 .read_status = &vsc85xx_read_status, 2374 .handle_interrupt = &vsc8584_handle_interrupt, 2375 .ack_interrupt = &vsc85xx_ack_interrupt, 2376 .config_intr = &vsc85xx_config_intr, 2377 .did_interrupt = &vsc8584_did_interrupt, 2378 .suspend = &genphy_suspend, 2379 .resume = &genphy_resume, 2380 .probe = &vsc8584_probe, 2381 .get_tunable = &vsc85xx_get_tunable, 2382 .set_tunable = &vsc85xx_set_tunable, 2383 .read_page = &vsc85xx_phy_read_page, 2384 .write_page = &vsc85xx_phy_write_page, 2385 .get_sset_count = &vsc85xx_get_sset_count, 2386 .get_strings = &vsc85xx_get_strings, 2387 .get_stats = &vsc85xx_get_stats, 2388 }, 2389 { 2390 .phy_id = PHY_ID_VSC8582, 2391 .name = "Microsemi GE VSC8582 SyncE", 2392 .phy_id_mask = 0xfffffff0, 2393 /* PHY_GBIT_FEATURES */ 2394 .soft_reset = &genphy_soft_reset, 2395 .config_init = &vsc8584_config_init, 2396 .config_aneg = &vsc85xx_config_aneg, 2397 .aneg_done = &genphy_aneg_done, 2398 .read_status = &vsc85xx_read_status, 2399 .handle_interrupt = &vsc8584_handle_interrupt, 2400 .ack_interrupt = &vsc85xx_ack_interrupt, 2401 .config_intr = &vsc85xx_config_intr, 2402 .did_interrupt = &vsc8584_did_interrupt, 2403 .suspend = &genphy_suspend, 2404 .resume = &genphy_resume, 2405 .probe = &vsc8584_probe, 2406 .get_tunable = &vsc85xx_get_tunable, 2407 .set_tunable = &vsc85xx_set_tunable, 2408 .read_page = &vsc85xx_phy_read_page, 2409 .write_page = &vsc85xx_phy_write_page, 2410 .get_sset_count = &vsc85xx_get_sset_count, 2411 .get_strings = &vsc85xx_get_strings, 2412 .get_stats = &vsc85xx_get_stats, 2413 }, 2414 { 2415 .phy_id = PHY_ID_VSC8584, 2416 .name = "Microsemi GE VSC8584 SyncE", 2417 .phy_id_mask = 0xfffffff0, 2418 /* PHY_GBIT_FEATURES */ 2419 .soft_reset = &genphy_soft_reset, 2420 .config_init = &vsc8584_config_init, 2421 .config_aneg = &vsc85xx_config_aneg, 2422 .aneg_done = &genphy_aneg_done, 2423 .read_status = &vsc85xx_read_status, 2424 .handle_interrupt = &vsc8584_handle_interrupt, 2425 .ack_interrupt = &vsc85xx_ack_interrupt, 2426 .config_intr = &vsc85xx_config_intr, 2427 .did_interrupt = &vsc8584_did_interrupt, 2428 .suspend = &genphy_suspend, 2429 .resume = &genphy_resume, 2430 .probe = &vsc8584_probe, 2431 .get_tunable = &vsc85xx_get_tunable, 2432 .set_tunable = &vsc85xx_set_tunable, 2433 .read_page = &vsc85xx_phy_read_page, 2434 .write_page = &vsc85xx_phy_write_page, 2435 .get_sset_count = &vsc85xx_get_sset_count, 2436 .get_strings = &vsc85xx_get_strings, 2437 .get_stats = &vsc85xx_get_stats, 2438 } 2439 2440 }; 2441 2442 module_phy_driver(vsc85xx_driver); 2443 2444 static struct mdio_device_id __maybe_unused vsc85xx_tbl[] = { 2445 { PHY_ID_VSC8504, 0xfffffff0, }, 2446 { PHY_ID_VSC8514, 0xfffffff0, }, 2447 { PHY_ID_VSC8530, 0xfffffff0, }, 2448 { PHY_ID_VSC8531, 0xfffffff0, }, 2449 { PHY_ID_VSC8540, 0xfffffff0, }, 2450 { PHY_ID_VSC8541, 0xfffffff0, }, 2451 { PHY_ID_VSC8552, 0xfffffff0, }, 2452 { PHY_ID_VSC856X, 0xfffffff0, }, 2453 { PHY_ID_VSC8572, 0xfffffff0, }, 2454 { PHY_ID_VSC8574, 0xfffffff0, }, 2455 { PHY_ID_VSC8575, 0xfffffff0, }, 2456 { PHY_ID_VSC8582, 0xfffffff0, }, 2457 { PHY_ID_VSC8584, 0xfffffff0, }, 2458 { } 2459 }; 2460 2461 MODULE_DEVICE_TABLE(mdio, vsc85xx_tbl); 2462 2463 MODULE_DESCRIPTION("Microsemi VSC85xx PHY driver"); 2464 MODULE_AUTHOR("Nagaraju Lakkaraju"); 2465 MODULE_LICENSE("Dual MIT/GPL"); 2466