1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car PWM Timer Controller 8 9maintainers: 10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - renesas,pwm-r8a7743 # RZ/G1M 17 - renesas,pwm-r8a7744 # RZ/G1N 18 - renesas,pwm-r8a7745 # RZ/G1E 19 - renesas,pwm-r8a77470 # RZ/G1C 20 - renesas,pwm-r8a774a1 # RZ/G2M 21 - renesas,pwm-r8a774b1 # RZ/G2N 22 - renesas,pwm-r8a774c0 # RZ/G2E 23 - renesas,pwm-r8a7778 # R-Car M1A 24 - renesas,pwm-r8a7779 # R-Car H1 25 - renesas,pwm-r8a7790 # R-Car H2 26 - renesas,pwm-r8a7791 # R-Car M2-W 27 - renesas,pwm-r8a7794 # R-Car E2 28 - renesas,pwm-r8a7795 # R-Car H3 29 - renesas,pwm-r8a7796 # R-Car M3-W 30 - renesas,pwm-r8a77965 # R-Car M3-N 31 - renesas,pwm-r8a77970 # R-Car V3M 32 - renesas,pwm-r8a77980 # R-Car V3H 33 - renesas,pwm-r8a77990 # R-Car E3 34 - renesas,pwm-r8a77995 # R-Car D3 35 - const: renesas,pwm-rcar 36 37 reg: 38 # base address and length of the registers block for the PWM. 39 maxItems: 1 40 41 '#pwm-cells': 42 # should be 2. See pwm.yaml in this directory for a description of 43 # the cells format. 44 const: 2 45 46 clocks: 47 # clock phandle and specifier pair. 48 maxItems: 1 49 50 power-domains: 51 maxItems: 1 52 53 resets: 54 maxItems: 1 55 56required: 57 - compatible 58 - reg 59 - '#pwm-cells' 60 - clocks 61 62additionalProperties: false 63 64examples: 65 - | 66 #include <dt-bindings/clock/r8a7743-cpg-mssr.h> 67 #include <dt-bindings/power/r8a7743-sysc.h> 68 69 pwm0: pwm@e6e30000 { 70 compatible = "renesas,pwm-r8a7743", "renesas,pwm-rcar"; 71 reg = <0 0xe6e30000 0 0x8>; 72 clocks = <&cpg CPG_MOD 523>; 73 power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; 74 resets = <&cpg 523>; 75 #pwm-cells = <2>; 76 pinctrl-0 = <&pwm0_pins>; 77 pinctrl-names = "default"; 78 }; 79