1 /* 2 * Copyright 2012-16 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 27 #ifndef _DCE_DMCU_H_ 28 #define _DCE_DMCU_H_ 29 30 #include "dmcu.h" 31 32 #define DMCU_COMMON_REG_LIST_DCE_BASE() \ 33 SR(DMCU_CTRL), \ 34 SR(DMCU_STATUS), \ 35 SR(DMCU_RAM_ACCESS_CTRL), \ 36 SR(DMCU_IRAM_WR_CTRL), \ 37 SR(DMCU_IRAM_WR_DATA), \ 38 SR(MASTER_COMM_DATA_REG1), \ 39 SR(MASTER_COMM_DATA_REG2), \ 40 SR(MASTER_COMM_DATA_REG3), \ 41 SR(MASTER_COMM_CMD_REG), \ 42 SR(MASTER_COMM_CNTL_REG), \ 43 SR(DMCU_IRAM_RD_CTRL), \ 44 SR(DMCU_IRAM_RD_DATA), \ 45 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 46 SR(SMU_INTERRUPT_CONTROL), \ 47 SR(DC_DMCU_SCRATCH) 48 49 #define DMCU_DCE80_REG_LIST() \ 50 SR(DMCU_CTRL), \ 51 SR(DMCU_STATUS), \ 52 SR(DMCU_RAM_ACCESS_CTRL), \ 53 SR(DMCU_IRAM_WR_CTRL), \ 54 SR(DMCU_IRAM_WR_DATA), \ 55 SR(MASTER_COMM_DATA_REG1), \ 56 SR(MASTER_COMM_DATA_REG2), \ 57 SR(MASTER_COMM_DATA_REG3), \ 58 SR(MASTER_COMM_CMD_REG), \ 59 SR(MASTER_COMM_CNTL_REG), \ 60 SR(DMCU_IRAM_RD_CTRL), \ 61 SR(DMCU_IRAM_RD_DATA), \ 62 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 63 SR(SMU_INTERRUPT_CONTROL), \ 64 SR(DC_DMCU_SCRATCH) 65 66 #define DMCU_DCE110_COMMON_REG_LIST() \ 67 DMCU_COMMON_REG_LIST_DCE_BASE(), \ 68 SR(DCI_MEM_PWR_STATUS) 69 70 #define DMCU_DCN10_REG_LIST()\ 71 DMCU_COMMON_REG_LIST_DCE_BASE(), \ 72 SR(DMU_MEM_PWR_CNTL) 73 74 #define DMCU_DCN20_REG_LIST()\ 75 DMCU_DCN10_REG_LIST(), \ 76 SR(DMCUB_SCRATCH15) 77 78 #define DMCU_SF(reg_name, field_name, post_fix)\ 79 .field_name = reg_name ## __ ## field_name ## post_fix 80 81 #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 82 DMCU_SF(DMCU_CTRL, \ 83 DMCU_ENABLE, mask_sh), \ 84 DMCU_SF(DMCU_STATUS, \ 85 UC_IN_STOP_MODE, mask_sh), \ 86 DMCU_SF(DMCU_STATUS, \ 87 UC_IN_RESET, mask_sh), \ 88 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 89 IRAM_HOST_ACCESS_EN, mask_sh), \ 90 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 91 IRAM_WR_ADDR_AUTO_INC, mask_sh), \ 92 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 93 IRAM_RD_ADDR_AUTO_INC, mask_sh), \ 94 DMCU_SF(MASTER_COMM_CMD_REG, \ 95 MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 96 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 97 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 98 STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \ 99 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 100 STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \ 101 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 102 STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \ 103 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 104 STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \ 105 DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh) 106 107 #define DMCU_MASK_SH_LIST_DCE80(mask_sh) \ 108 DMCU_SF(DMCU_CTRL, \ 109 DMCU_ENABLE, mask_sh), \ 110 DMCU_SF(DMCU_STATUS, \ 111 UC_IN_STOP_MODE, mask_sh), \ 112 DMCU_SF(DMCU_STATUS, \ 113 UC_IN_RESET, mask_sh), \ 114 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 115 IRAM_HOST_ACCESS_EN, mask_sh), \ 116 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 117 IRAM_WR_ADDR_AUTO_INC, mask_sh), \ 118 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 119 IRAM_RD_ADDR_AUTO_INC, mask_sh), \ 120 DMCU_SF(MASTER_COMM_CMD_REG, \ 121 MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 122 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 123 DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh) 124 125 #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \ 126 DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 127 DMCU_SF(DCI_MEM_PWR_STATUS, \ 128 DMCU_IRAM_MEM_PWR_STATE, mask_sh) 129 130 #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \ 131 DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 132 DMCU_SF(DMU_MEM_PWR_CNTL, \ 133 DMCU_IRAM_MEM_PWR_STATE, mask_sh) 134 135 #define DMCU_REG_FIELD_LIST(type) \ 136 type DMCU_IRAM_MEM_PWR_STATE; \ 137 type IRAM_HOST_ACCESS_EN; \ 138 type IRAM_WR_ADDR_AUTO_INC; \ 139 type IRAM_RD_ADDR_AUTO_INC; \ 140 type DMCU_ENABLE; \ 141 type UC_IN_STOP_MODE; \ 142 type UC_IN_RESET; \ 143 type MASTER_COMM_CMD_REG_BYTE0; \ 144 type MASTER_COMM_INTERRUPT; \ 145 type DPHY_RX_FAST_TRAINING_CAPABLE; \ 146 type DPHY_LOAD_BS_COUNT; \ 147 type STATIC_SCREEN1_INT_TO_UC_EN; \ 148 type STATIC_SCREEN2_INT_TO_UC_EN; \ 149 type STATIC_SCREEN3_INT_TO_UC_EN; \ 150 type STATIC_SCREEN4_INT_TO_UC_EN; \ 151 type DP_SEC_GSP0_LINE_NUM; \ 152 type DP_SEC_GSP0_PRIORITY; \ 153 type DC_SMU_INT_ENABLE 154 155 struct dce_dmcu_shift { 156 DMCU_REG_FIELD_LIST(uint8_t); 157 }; 158 159 struct dce_dmcu_mask { 160 DMCU_REG_FIELD_LIST(uint32_t); 161 }; 162 163 struct dce_dmcu_registers { 164 uint32_t DMCU_CTRL; 165 uint32_t DMCU_STATUS; 166 uint32_t DMCU_RAM_ACCESS_CTRL; 167 uint32_t DCI_MEM_PWR_STATUS; 168 uint32_t DMU_MEM_PWR_CNTL; 169 uint32_t DMCU_IRAM_WR_CTRL; 170 uint32_t DMCU_IRAM_WR_DATA; 171 172 uint32_t MASTER_COMM_DATA_REG1; 173 uint32_t MASTER_COMM_DATA_REG2; 174 uint32_t MASTER_COMM_DATA_REG3; 175 uint32_t MASTER_COMM_CMD_REG; 176 uint32_t MASTER_COMM_CNTL_REG; 177 uint32_t DMCU_IRAM_RD_CTRL; 178 uint32_t DMCU_IRAM_RD_DATA; 179 uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; 180 uint32_t SMU_INTERRUPT_CONTROL; 181 uint32_t DC_DMCU_SCRATCH; 182 uint32_t DMCUB_SCRATCH15; 183 }; 184 185 struct dce_dmcu { 186 struct dmcu base; 187 const struct dce_dmcu_registers *regs; 188 const struct dce_dmcu_shift *dmcu_shift; 189 const struct dce_dmcu_mask *dmcu_mask; 190 }; 191 192 /******************************************************************* 193 * MASTER_COMM_DATA_REG1 Bit position Data 194 * 7:0 hyst_frames[7:0] 195 * 14:8 hyst_lines[6:0] 196 * 15 RFB_UPDATE_AUTO_EN 197 * 18:16 phy_num[2:0] 198 * 21:19 dcp_sel[2:0] 199 * 22 phy_type 200 * 23 frame_cap_ind 201 * 26:24 aux_chan[2:0] 202 * 30:27 aux_repeat[3:0] 203 * 31:31 reserved[31:31] 204 ******************************************************************/ 205 union dce_dmcu_psr_config_data_reg1 { 206 struct { 207 unsigned int timehyst_frames:8; /*[7:0]*/ 208 unsigned int hyst_lines:7; /*[14:8]*/ 209 unsigned int rfb_update_auto_en:1; /*[15:15]*/ 210 unsigned int dp_port_num:3; /*[18:16]*/ 211 unsigned int dcp_sel:3; /*[21:19]*/ 212 unsigned int phy_type:1; /*[22:22]*/ 213 unsigned int frame_cap_ind:1; /*[23:23]*/ 214 unsigned int aux_chan:3; /*[26:24]*/ 215 unsigned int aux_repeat:4; /*[30:27]*/ 216 unsigned int allow_smu_optimizations:1; /*[31:31]*/ 217 } bits; 218 unsigned int u32All; 219 }; 220 221 /******************************************************************* 222 * MASTER_COMM_DATA_REG2 223 *******************************************************************/ 224 union dce_dmcu_psr_config_data_reg2 { 225 struct { 226 unsigned int dig_fe:3; /*[2:0]*/ 227 unsigned int dig_be:3; /*[5:3]*/ 228 unsigned int skip_wait_for_pll_lock:1; /*[6:6]*/ 229 unsigned int reserved:9; /*[15:7]*/ 230 unsigned int frame_delay:8; /*[23:16]*/ 231 unsigned int smu_phy_id:4; /*[27:24]*/ 232 unsigned int num_of_controllers:4; /*[31:28]*/ 233 } bits; 234 unsigned int u32All; 235 }; 236 237 /******************************************************************* 238 * MASTER_COMM_DATA_REG3 239 *******************************************************************/ 240 union dce_dmcu_psr_config_data_reg3 { 241 struct { 242 unsigned int psr_level:16; /*[15:0]*/ 243 unsigned int link_rate:4; /*[19:16]*/ 244 unsigned int reserved:12; /*[31:20]*/ 245 } bits; 246 unsigned int u32All; 247 }; 248 249 union dce_dmcu_psr_config_data_wait_loop_reg1 { 250 struct { 251 unsigned int wait_loop:16; /* [15:0] */ 252 unsigned int reserved:16; /* [31:16] */ 253 } bits; 254 unsigned int u32; 255 }; 256 257 struct dmcu *dce_dmcu_create( 258 struct dc_context *ctx, 259 const struct dce_dmcu_registers *regs, 260 const struct dce_dmcu_shift *dmcu_shift, 261 const struct dce_dmcu_mask *dmcu_mask); 262 263 struct dmcu *dcn10_dmcu_create( 264 struct dc_context *ctx, 265 const struct dce_dmcu_registers *regs, 266 const struct dce_dmcu_shift *dmcu_shift, 267 const struct dce_dmcu_mask *dmcu_mask); 268 269 struct dmcu *dcn20_dmcu_create( 270 struct dc_context *ctx, 271 const struct dce_dmcu_registers *regs, 272 const struct dce_dmcu_shift *dmcu_shift, 273 const struct dce_dmcu_mask *dmcu_mask); 274 275 struct dmcu *dcn21_dmcu_create( 276 struct dc_context *ctx, 277 const struct dce_dmcu_registers *regs, 278 const struct dce_dmcu_shift *dmcu_shift, 279 const struct dce_dmcu_mask *dmcu_mask); 280 281 void dce_dmcu_destroy(struct dmcu **dmcu); 282 283 static const uint32_t abm_gain_stepsize = 0x0060; 284 285 #endif /* _DCE_ABM_H_ */ 286