1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DCE_HWSEQ_H__ 26 #define __DCE_HWSEQ_H__ 27 28 #include "dc_types.h" 29 30 #define HWSEQ_DCEF_REG_LIST_DCE8() \ 31 .DCFE_CLOCK_CONTROL[0] = mmCRTC0_CRTC_DCFE_CLOCK_CONTROL, \ 32 .DCFE_CLOCK_CONTROL[1] = mmCRTC1_CRTC_DCFE_CLOCK_CONTROL, \ 33 .DCFE_CLOCK_CONTROL[2] = mmCRTC2_CRTC_DCFE_CLOCK_CONTROL, \ 34 .DCFE_CLOCK_CONTROL[3] = mmCRTC3_CRTC_DCFE_CLOCK_CONTROL, \ 35 .DCFE_CLOCK_CONTROL[4] = mmCRTC4_CRTC_DCFE_CLOCK_CONTROL, \ 36 .DCFE_CLOCK_CONTROL[5] = mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 37 38 #define HWSEQ_DCEF_REG_LIST() \ 39 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 40 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 41 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 42 SRII(DCFE_CLOCK_CONTROL, DCFE, 3), \ 43 SRII(DCFE_CLOCK_CONTROL, DCFE, 4), \ 44 SRII(DCFE_CLOCK_CONTROL, DCFE, 5), \ 45 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 46 47 #define HWSEQ_BLND_REG_LIST() \ 48 SRII(BLND_V_UPDATE_LOCK, BLND, 0), \ 49 SRII(BLND_V_UPDATE_LOCK, BLND, 1), \ 50 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 51 SRII(BLND_V_UPDATE_LOCK, BLND, 3), \ 52 SRII(BLND_V_UPDATE_LOCK, BLND, 4), \ 53 SRII(BLND_V_UPDATE_LOCK, BLND, 5), \ 54 SRII(BLND_CONTROL, BLND, 0), \ 55 SRII(BLND_CONTROL, BLND, 1), \ 56 SRII(BLND_CONTROL, BLND, 2), \ 57 SRII(BLND_CONTROL, BLND, 3), \ 58 SRII(BLND_CONTROL, BLND, 4), \ 59 SRII(BLND_CONTROL, BLND, 5) 60 61 #define HSWEQ_DCN_PIXEL_RATE_REG_LIST(blk, inst) \ 62 SRII(PIXEL_RATE_CNTL, blk, inst), \ 63 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, inst) 64 65 #define HWSEQ_PIXEL_RATE_REG_LIST(blk) \ 66 SRII(PIXEL_RATE_CNTL, blk, 0), \ 67 SRII(PIXEL_RATE_CNTL, blk, 1), \ 68 SRII(PIXEL_RATE_CNTL, blk, 2), \ 69 SRII(PIXEL_RATE_CNTL, blk, 3), \ 70 SRII(PIXEL_RATE_CNTL, blk, 4), \ 71 SRII(PIXEL_RATE_CNTL, blk, 5) 72 73 #define HWSEQ_PHYPLL_REG_LIST(blk) \ 74 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 75 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1), \ 76 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2), \ 77 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 78 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 79 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 80 81 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 82 #define HWSEQ_PIXEL_RATE_REG_LIST_3(blk) \ 83 SRII(PIXEL_RATE_CNTL, blk, 0), \ 84 SRII(PIXEL_RATE_CNTL, blk, 1),\ 85 SRII(PIXEL_RATE_CNTL, blk, 2),\ 86 SRII(PIXEL_RATE_CNTL, blk, 3), \ 87 SRII(PIXEL_RATE_CNTL, blk, 4), \ 88 SRII(PIXEL_RATE_CNTL, blk, 5) 89 90 #define HWSEQ_PHYPLL_REG_LIST_3(blk) \ 91 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 0), \ 92 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 1),\ 93 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 2),\ 94 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 3), \ 95 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 4), \ 96 SRII(PHYPLL_PIXEL_RATE_CNTL, blk, 5) 97 #endif 98 99 #define HWSEQ_DCE11_REG_LIST_BASE() \ 100 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \ 101 SR(DCFEV_CLOCK_CONTROL), \ 102 SRII(DCFE_CLOCK_CONTROL, DCFE, 0), \ 103 SRII(DCFE_CLOCK_CONTROL, DCFE, 1), \ 104 SRII(CRTC_H_BLANK_START_END, CRTC, 0),\ 105 SRII(CRTC_H_BLANK_START_END, CRTC, 1),\ 106 SRII(BLND_V_UPDATE_LOCK, BLND, 0),\ 107 SRII(BLND_V_UPDATE_LOCK, BLND, 1),\ 108 SRII(BLND_CONTROL, BLND, 0),\ 109 SRII(BLND_CONTROL, BLND, 1),\ 110 SR(BLNDV_CONTROL),\ 111 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 112 113 #define HWSEQ_DCE8_REG_LIST() \ 114 HWSEQ_DCEF_REG_LIST_DCE8(), \ 115 HWSEQ_BLND_REG_LIST(), \ 116 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 117 118 #define HWSEQ_DCE10_REG_LIST() \ 119 HWSEQ_DCEF_REG_LIST(), \ 120 HWSEQ_BLND_REG_LIST(), \ 121 HWSEQ_PIXEL_RATE_REG_LIST(CRTC) 122 123 #define HWSEQ_ST_REG_LIST() \ 124 HWSEQ_DCE11_REG_LIST_BASE(), \ 125 .DCFE_CLOCK_CONTROL[2] = mmDCFEV_CLOCK_CONTROL, \ 126 .CRTC_H_BLANK_START_END[2] = mmCRTCV_H_BLANK_START_END, \ 127 .BLND_V_UPDATE_LOCK[2] = mmBLNDV_V_UPDATE_LOCK, \ 128 .BLND_CONTROL[2] = mmBLNDV_CONTROL 129 130 #define HWSEQ_CZ_REG_LIST() \ 131 HWSEQ_DCE11_REG_LIST_BASE(), \ 132 SRII(DCFE_CLOCK_CONTROL, DCFE, 2), \ 133 SRII(CRTC_H_BLANK_START_END, CRTC, 2), \ 134 SRII(BLND_V_UPDATE_LOCK, BLND, 2), \ 135 SRII(BLND_CONTROL, BLND, 2), \ 136 .DCFE_CLOCK_CONTROL[3] = mmDCFEV_CLOCK_CONTROL, \ 137 .CRTC_H_BLANK_START_END[3] = mmCRTCV_H_BLANK_START_END, \ 138 .BLND_V_UPDATE_LOCK[3] = mmBLNDV_V_UPDATE_LOCK, \ 139 .BLND_CONTROL[3] = mmBLNDV_CONTROL 140 141 #define HWSEQ_DCE120_REG_LIST() \ 142 HWSEQ_DCE10_REG_LIST(), \ 143 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 144 HWSEQ_PHYPLL_REG_LIST(CRTC), \ 145 SR(DCHUB_FB_LOCATION),\ 146 SR(DCHUB_AGP_BASE),\ 147 SR(DCHUB_AGP_BOT),\ 148 SR(DCHUB_AGP_TOP) 149 150 #define HWSEQ_VG20_REG_LIST() \ 151 HWSEQ_DCE120_REG_LIST(),\ 152 MMHUB_SR(MC_VM_XGMI_LFB_CNTL) 153 154 #define HWSEQ_DCE112_REG_LIST() \ 155 HWSEQ_DCE10_REG_LIST(), \ 156 HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ 157 HWSEQ_PHYPLL_REG_LIST(CRTC) 158 159 #define HWSEQ_DCN_REG_LIST()\ 160 SR(REFCLK_CNTL), \ 161 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \ 162 SR(DIO_MEM_PWR_CTRL), \ 163 SR(DCCG_GATE_DISABLE_CNTL), \ 164 SR(DCCG_GATE_DISABLE_CNTL2), \ 165 SR(DCFCLK_CNTL),\ 166 SR(DCFCLK_CNTL), \ 167 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL) 168 169 170 #define MMHUB_DCN_REG_LIST()\ 171 /* todo: get these from GVM instead of reading registers ourselves */\ 172 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32),\ 173 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32),\ 174 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32),\ 175 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32),\ 176 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32),\ 177 MMHUB_SR(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32),\ 178 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32),\ 179 MMHUB_SR(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32),\ 180 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB),\ 181 MMHUB_SR(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB),\ 182 MMHUB_SR(MC_VM_SYSTEM_APERTURE_LOW_ADDR),\ 183 MMHUB_SR(MC_VM_SYSTEM_APERTURE_HIGH_ADDR) 184 185 186 #define HWSEQ_DCN1_REG_LIST()\ 187 HWSEQ_DCN_REG_LIST(), \ 188 MMHUB_DCN_REG_LIST(), \ 189 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 190 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 191 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 192 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 193 SR(DCHUBBUB_SDPIF_FB_BASE),\ 194 SR(DCHUBBUB_SDPIF_FB_OFFSET),\ 195 SR(DCHUBBUB_SDPIF_AGP_BASE),\ 196 SR(DCHUBBUB_SDPIF_AGP_BOT),\ 197 SR(DCHUBBUB_SDPIF_AGP_TOP),\ 198 SR(DOMAIN0_PG_CONFIG), \ 199 SR(DOMAIN1_PG_CONFIG), \ 200 SR(DOMAIN2_PG_CONFIG), \ 201 SR(DOMAIN3_PG_CONFIG), \ 202 SR(DOMAIN4_PG_CONFIG), \ 203 SR(DOMAIN5_PG_CONFIG), \ 204 SR(DOMAIN6_PG_CONFIG), \ 205 SR(DOMAIN7_PG_CONFIG), \ 206 SR(DOMAIN0_PG_STATUS), \ 207 SR(DOMAIN1_PG_STATUS), \ 208 SR(DOMAIN2_PG_STATUS), \ 209 SR(DOMAIN3_PG_STATUS), \ 210 SR(DOMAIN4_PG_STATUS), \ 211 SR(DOMAIN5_PG_STATUS), \ 212 SR(DOMAIN6_PG_STATUS), \ 213 SR(DOMAIN7_PG_STATUS), \ 214 SR(D1VGA_CONTROL), \ 215 SR(D2VGA_CONTROL), \ 216 SR(D3VGA_CONTROL), \ 217 SR(D4VGA_CONTROL), \ 218 SR(VGA_TEST_CONTROL), \ 219 SR(DC_IP_REQUEST_CNTL) 220 221 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 222 #define HWSEQ_DCN30_REG_LIST()\ 223 HWSEQ_DCN2_REG_LIST(),\ 224 HWSEQ_DCN_REG_LIST(), \ 225 HWSEQ_PIXEL_RATE_REG_LIST_3(OTG), \ 226 HWSEQ_PHYPLL_REG_LIST_3(OTG), \ 227 SR(MICROSECOND_TIME_BASE_DIV), \ 228 SR(MILLISECOND_TIME_BASE_DIV), \ 229 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 230 SR(RBBMIF_TIMEOUT_DIS), \ 231 SR(RBBMIF_TIMEOUT_DIS_2), \ 232 SR(DCHUBBUB_CRC_CTRL), \ 233 SR(DPP_TOP0_DPP_CRC_CTRL), \ 234 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 235 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 236 SR(MPC_CRC_CTRL), \ 237 SR(MPC_CRC_RESULT_GB), \ 238 SR(MPC_CRC_RESULT_C), \ 239 SR(MPC_CRC_RESULT_AR), \ 240 SR(AZALIA_AUDIO_DTO), \ 241 SR(AZALIA_CONTROLLER_CLOCK_GATING) 242 #endif 243 #define HWSEQ_DCN2_REG_LIST()\ 244 HWSEQ_DCN_REG_LIST(), \ 245 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 246 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 247 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 248 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 249 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 4), \ 250 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 5), \ 251 SR(MICROSECOND_TIME_BASE_DIV), \ 252 SR(MILLISECOND_TIME_BASE_DIV), \ 253 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 254 SR(RBBMIF_TIMEOUT_DIS), \ 255 SR(RBBMIF_TIMEOUT_DIS_2), \ 256 SR(DCHUBBUB_CRC_CTRL), \ 257 SR(DPP_TOP0_DPP_CRC_CTRL), \ 258 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 259 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 260 SR(MPC_CRC_CTRL), \ 261 SR(MPC_CRC_RESULT_GB), \ 262 SR(MPC_CRC_RESULT_C), \ 263 SR(MPC_CRC_RESULT_AR), \ 264 SR(DOMAIN0_PG_CONFIG), \ 265 SR(DOMAIN1_PG_CONFIG), \ 266 SR(DOMAIN2_PG_CONFIG), \ 267 SR(DOMAIN3_PG_CONFIG), \ 268 SR(DOMAIN4_PG_CONFIG), \ 269 SR(DOMAIN5_PG_CONFIG), \ 270 SR(DOMAIN6_PG_CONFIG), \ 271 SR(DOMAIN7_PG_CONFIG), \ 272 SR(DOMAIN8_PG_CONFIG), \ 273 SR(DOMAIN9_PG_CONFIG), \ 274 /* SR(DOMAIN10_PG_CONFIG), Navi1x HUBP5 not powergate-able*/\ 275 /* SR(DOMAIN11_PG_CONFIG), Navi1x DPP5 is not powergate-able */\ 276 SR(DOMAIN16_PG_CONFIG), \ 277 SR(DOMAIN17_PG_CONFIG), \ 278 SR(DOMAIN18_PG_CONFIG), \ 279 SR(DOMAIN19_PG_CONFIG), \ 280 SR(DOMAIN20_PG_CONFIG), \ 281 SR(DOMAIN21_PG_CONFIG), \ 282 SR(DOMAIN0_PG_STATUS), \ 283 SR(DOMAIN1_PG_STATUS), \ 284 SR(DOMAIN2_PG_STATUS), \ 285 SR(DOMAIN3_PG_STATUS), \ 286 SR(DOMAIN4_PG_STATUS), \ 287 SR(DOMAIN5_PG_STATUS), \ 288 SR(DOMAIN6_PG_STATUS), \ 289 SR(DOMAIN7_PG_STATUS), \ 290 SR(DOMAIN8_PG_STATUS), \ 291 SR(DOMAIN9_PG_STATUS), \ 292 SR(DOMAIN10_PG_STATUS), \ 293 SR(DOMAIN11_PG_STATUS), \ 294 SR(DOMAIN16_PG_STATUS), \ 295 SR(DOMAIN17_PG_STATUS), \ 296 SR(DOMAIN18_PG_STATUS), \ 297 SR(DOMAIN19_PG_STATUS), \ 298 SR(DOMAIN20_PG_STATUS), \ 299 SR(DOMAIN21_PG_STATUS), \ 300 SR(D1VGA_CONTROL), \ 301 SR(D2VGA_CONTROL), \ 302 SR(D3VGA_CONTROL), \ 303 SR(D4VGA_CONTROL), \ 304 SR(D5VGA_CONTROL), \ 305 SR(D6VGA_CONTROL), \ 306 SR(DC_IP_REQUEST_CNTL) 307 308 #define HWSEQ_DCN21_REG_LIST()\ 309 HWSEQ_DCN_REG_LIST(), \ 310 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 0), \ 311 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 1), \ 312 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 2), \ 313 HSWEQ_DCN_PIXEL_RATE_REG_LIST(OTG, 3), \ 314 MMHUB_DCN_REG_LIST(), \ 315 SR(MICROSECOND_TIME_BASE_DIV), \ 316 SR(MILLISECOND_TIME_BASE_DIV), \ 317 SR(DISPCLK_FREQ_CHANGE_CNTL), \ 318 SR(RBBMIF_TIMEOUT_DIS), \ 319 SR(RBBMIF_TIMEOUT_DIS_2), \ 320 SR(DCHUBBUB_CRC_CTRL), \ 321 SR(DPP_TOP0_DPP_CRC_CTRL), \ 322 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \ 323 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \ 324 SR(MPC_CRC_CTRL), \ 325 SR(MPC_CRC_RESULT_GB), \ 326 SR(MPC_CRC_RESULT_C), \ 327 SR(MPC_CRC_RESULT_AR), \ 328 SR(DOMAIN0_PG_CONFIG), \ 329 SR(DOMAIN1_PG_CONFIG), \ 330 SR(DOMAIN2_PG_CONFIG), \ 331 SR(DOMAIN3_PG_CONFIG), \ 332 SR(DOMAIN4_PG_CONFIG), \ 333 SR(DOMAIN5_PG_CONFIG), \ 334 SR(DOMAIN6_PG_CONFIG), \ 335 SR(DOMAIN7_PG_CONFIG), \ 336 SR(DOMAIN16_PG_CONFIG), \ 337 SR(DOMAIN17_PG_CONFIG), \ 338 SR(DOMAIN18_PG_CONFIG), \ 339 SR(DOMAIN0_PG_STATUS), \ 340 SR(DOMAIN1_PG_STATUS), \ 341 SR(DOMAIN2_PG_STATUS), \ 342 SR(DOMAIN3_PG_STATUS), \ 343 SR(DOMAIN4_PG_STATUS), \ 344 SR(DOMAIN5_PG_STATUS), \ 345 SR(DOMAIN6_PG_STATUS), \ 346 SR(DOMAIN7_PG_STATUS), \ 347 SR(DOMAIN16_PG_STATUS), \ 348 SR(DOMAIN17_PG_STATUS), \ 349 SR(DOMAIN18_PG_STATUS), \ 350 SR(D1VGA_CONTROL), \ 351 SR(D2VGA_CONTROL), \ 352 SR(D3VGA_CONTROL), \ 353 SR(D4VGA_CONTROL), \ 354 SR(D5VGA_CONTROL), \ 355 SR(D6VGA_CONTROL), \ 356 SR(DC_IP_REQUEST_CNTL) 357 358 struct dce_hwseq_registers { 359 uint32_t DCFE_CLOCK_CONTROL[6]; 360 uint32_t DCFEV_CLOCK_CONTROL; 361 uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; 362 uint32_t BLND_V_UPDATE_LOCK[6]; 363 uint32_t BLND_CONTROL[6]; 364 uint32_t BLNDV_CONTROL; 365 uint32_t CRTC_H_BLANK_START_END[6]; 366 uint32_t PIXEL_RATE_CNTL[6]; 367 uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; 368 /*DCHUB*/ 369 uint32_t DCHUB_FB_LOCATION; 370 uint32_t DCHUB_AGP_BASE; 371 uint32_t DCHUB_AGP_BOT; 372 uint32_t DCHUB_AGP_TOP; 373 374 uint32_t REFCLK_CNTL; 375 376 uint32_t DCHUBBUB_GLOBAL_TIMER_CNTL; 377 uint32_t DCHUBBUB_SDPIF_FB_BASE; 378 uint32_t DCHUBBUB_SDPIF_FB_OFFSET; 379 uint32_t DCHUBBUB_SDPIF_AGP_BASE; 380 uint32_t DCHUBBUB_SDPIF_AGP_BOT; 381 uint32_t DCHUBBUB_SDPIF_AGP_TOP; 382 uint32_t DC_IP_REQUEST_CNTL; 383 uint32_t DOMAIN0_PG_CONFIG; 384 uint32_t DOMAIN1_PG_CONFIG; 385 uint32_t DOMAIN2_PG_CONFIG; 386 uint32_t DOMAIN3_PG_CONFIG; 387 uint32_t DOMAIN4_PG_CONFIG; 388 uint32_t DOMAIN5_PG_CONFIG; 389 uint32_t DOMAIN6_PG_CONFIG; 390 uint32_t DOMAIN7_PG_CONFIG; 391 uint32_t DOMAIN8_PG_CONFIG; 392 uint32_t DOMAIN9_PG_CONFIG; 393 uint32_t DOMAIN10_PG_CONFIG; 394 uint32_t DOMAIN11_PG_CONFIG; 395 uint32_t DOMAIN16_PG_CONFIG; 396 uint32_t DOMAIN17_PG_CONFIG; 397 uint32_t DOMAIN18_PG_CONFIG; 398 uint32_t DOMAIN19_PG_CONFIG; 399 uint32_t DOMAIN20_PG_CONFIG; 400 uint32_t DOMAIN21_PG_CONFIG; 401 uint32_t DOMAIN0_PG_STATUS; 402 uint32_t DOMAIN1_PG_STATUS; 403 uint32_t DOMAIN2_PG_STATUS; 404 uint32_t DOMAIN3_PG_STATUS; 405 uint32_t DOMAIN4_PG_STATUS; 406 uint32_t DOMAIN5_PG_STATUS; 407 uint32_t DOMAIN6_PG_STATUS; 408 uint32_t DOMAIN7_PG_STATUS; 409 uint32_t DOMAIN8_PG_STATUS; 410 uint32_t DOMAIN9_PG_STATUS; 411 uint32_t DOMAIN10_PG_STATUS; 412 uint32_t DOMAIN11_PG_STATUS; 413 uint32_t DOMAIN16_PG_STATUS; 414 uint32_t DOMAIN17_PG_STATUS; 415 uint32_t DOMAIN18_PG_STATUS; 416 uint32_t DOMAIN19_PG_STATUS; 417 uint32_t DOMAIN20_PG_STATUS; 418 uint32_t DOMAIN21_PG_STATUS; 419 uint32_t DIO_MEM_PWR_CTRL; 420 uint32_t DCCG_GATE_DISABLE_CNTL; 421 uint32_t DCCG_GATE_DISABLE_CNTL2; 422 uint32_t DCFCLK_CNTL; 423 uint32_t MICROSECOND_TIME_BASE_DIV; 424 uint32_t MILLISECOND_TIME_BASE_DIV; 425 uint32_t DISPCLK_FREQ_CHANGE_CNTL; 426 uint32_t RBBMIF_TIMEOUT_DIS; 427 uint32_t RBBMIF_TIMEOUT_DIS_2; 428 uint32_t DCHUBBUB_CRC_CTRL; 429 uint32_t DPP_TOP0_DPP_CRC_CTRL; 430 uint32_t DPP_TOP0_DPP_CRC_VAL_R_G; 431 uint32_t DPP_TOP0_DPP_CRC_VAL_B_A; 432 uint32_t MPC_CRC_CTRL; 433 uint32_t MPC_CRC_RESULT_GB; 434 uint32_t MPC_CRC_RESULT_C; 435 uint32_t MPC_CRC_RESULT_AR; 436 uint32_t D1VGA_CONTROL; 437 uint32_t D2VGA_CONTROL; 438 uint32_t D3VGA_CONTROL; 439 uint32_t D4VGA_CONTROL; 440 uint32_t D5VGA_CONTROL; 441 uint32_t D6VGA_CONTROL; 442 uint32_t VGA_TEST_CONTROL; 443 /* MMHUB registers. read only. temporary hack */ 444 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32; 445 uint32_t VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32; 446 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32; 447 uint32_t VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32; 448 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32; 449 uint32_t VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32; 450 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32; 451 uint32_t VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32; 452 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB; 453 uint32_t MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB; 454 uint32_t MC_VM_SYSTEM_APERTURE_LOW_ADDR; 455 uint32_t MC_VM_SYSTEM_APERTURE_HIGH_ADDR; 456 uint32_t MC_VM_XGMI_LFB_CNTL; 457 uint32_t AZALIA_AUDIO_DTO; 458 uint32_t AZALIA_CONTROLLER_CLOCK_GATING; 459 }; 460 /* set field name */ 461 #define HWS_SF(blk_name, reg_name, field_name, post_fix)\ 462 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 463 464 #define HWS_SF1(blk_name, reg_name, field_name, post_fix)\ 465 .field_name = blk_name ## reg_name ## __ ## blk_name ## field_name ## post_fix 466 467 468 #define HWSEQ_DCEF_MASK_SH_LIST(mask_sh, blk)\ 469 HWS_SF(blk, CLOCK_CONTROL, DCFE_CLOCK_ENABLE, mask_sh),\ 470 SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 471 472 #define HWSEQ_BLND_MASK_SH_LIST(mask_sh, blk)\ 473 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 474 HWS_SF(blk, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 475 HWS_SF(blk, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 476 HWS_SF(blk, V_UPDATE_LOCK, BLND_BLND_V_UPDATE_LOCK, mask_sh),\ 477 HWS_SF(blk, V_UPDATE_LOCK, BLND_V_UPDATE_LOCK_MODE, mask_sh),\ 478 HWS_SF(blk, CONTROL, BLND_FEEDTHROUGH_EN, mask_sh),\ 479 HWS_SF(blk, CONTROL, BLND_ALPHA_MODE, mask_sh),\ 480 HWS_SF(blk, CONTROL, BLND_MODE, mask_sh),\ 481 HWS_SF(blk, CONTROL, BLND_MULTIPLIED_MODE, mask_sh) 482 483 #define HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, blk)\ 484 HWS_SF1(blk, PIXEL_RATE_CNTL, PIXEL_RATE_SOURCE, mask_sh),\ 485 HWS_SF(blk, PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 486 487 #define HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, blk)\ 488 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh),\ 489 HWS_SF1(blk, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh) 490 491 #define HWSEQ_DCE8_MASK_SH_LIST(mask_sh)\ 492 .DCFE_CLOCK_ENABLE = CRTC_DCFE_CLOCK_CONTROL__CRTC_DCFE_CLOCK_ENABLE ## mask_sh, \ 493 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_V_UPDATE_LOCK, mask_sh),\ 494 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_SCL_V_UPDATE_LOCK, mask_sh),\ 495 HWS_SF(BLND_, V_UPDATE_LOCK, BLND_DCP_GRPH_SURF_V_UPDATE_LOCK, mask_sh),\ 496 HWS_SF(BLND_, CONTROL, BLND_MODE, mask_sh),\ 497 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 498 499 #define HWSEQ_DCE10_MASK_SH_LIST(mask_sh)\ 500 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE_),\ 501 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND_),\ 502 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 503 504 #define HWSEQ_DCE11_MASK_SH_LIST(mask_sh)\ 505 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 506 SF(DCFEV_CLOCK_CONTROL, DCFEV_CLOCK_ENABLE, mask_sh),\ 507 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_) 508 509 #define HWSEQ_DCE112_MASK_SH_LIST(mask_sh)\ 510 HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ 511 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) 512 513 #define HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 514 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 515 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 516 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 517 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 518 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) 519 520 #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ 521 HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ 522 HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ 523 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ 524 HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_),\ 525 HWSEQ_GFX9_DCHUB_MASK_SH_LIST(mask_sh) 526 527 #define HWSEQ_VG20_MASK_SH_LIST(mask_sh)\ 528 HWSEQ_DCE12_MASK_SH_LIST(mask_sh),\ 529 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_LFB_REGION, mask_sh),\ 530 HWS_SF(, MC_VM_XGMI_LFB_CNTL, PF_MAX_REGION, mask_sh) 531 532 #define HWSEQ_DCN_MASK_SH_LIST(mask_sh)\ 533 HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ 534 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PHYPLL_PIXEL_RATE_SOURCE, mask_sh), \ 535 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, mask_sh), \ 536 HWS_SF(, DCFCLK_CNTL, DCFCLK_GATE_DIS, mask_sh), \ 537 HWS_SF(, DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh) 538 539 #define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ 540 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 541 HWS_SF1(OTG0_, PHYPLL_PIXEL_RATE_CNTL, PIXEL_RATE_PLL_SOURCE, mask_sh), \ 542 HWS_SF(, DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, mask_sh), \ 543 HWS_SF(, DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, mask_sh), \ 544 HWS_SF(, DCHUBBUB_SDPIF_AGP_BASE, SDPIF_AGP_BASE, mask_sh), \ 545 HWS_SF(, DCHUBBUB_SDPIF_AGP_BOT, SDPIF_AGP_BOT, mask_sh), \ 546 HWS_SF(, DCHUBBUB_SDPIF_AGP_TOP, SDPIF_AGP_TOP, mask_sh), \ 547 /* todo: get these from GVM instead of reading registers ourselves */\ 548 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 549 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 550 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, LOGICAL_PAGE_NUMBER_HI4, mask_sh),\ 551 HWS_SF(, VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, LOGICAL_PAGE_NUMBER_LO32, mask_sh),\ 552 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, PHYSICAL_PAGE_ADDR_HI4, mask_sh),\ 553 HWS_SF(, VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, PHYSICAL_PAGE_ADDR_LO32, mask_sh),\ 554 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, PHYSICAL_PAGE_NUMBER_MSB, mask_sh),\ 555 HWS_SF(, MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, PHYSICAL_PAGE_NUMBER_LSB, mask_sh),\ 556 HWS_SF(, MC_VM_SYSTEM_APERTURE_LOW_ADDR, LOGICAL_ADDR, mask_sh),\ 557 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 558 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 559 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 560 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 561 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 562 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 563 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 564 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 565 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 566 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 567 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 568 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 569 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 570 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 571 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 572 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 573 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 574 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 575 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 576 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 577 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 578 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 579 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 580 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 581 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \ 582 HWS_SF(, D1VGA_CONTROL, D1VGA_MODE_ENABLE, mask_sh),\ 583 HWS_SF(, D2VGA_CONTROL, D2VGA_MODE_ENABLE, mask_sh),\ 584 HWS_SF(, D3VGA_CONTROL, D3VGA_MODE_ENABLE, mask_sh),\ 585 HWS_SF(, D4VGA_CONTROL, D4VGA_MODE_ENABLE, mask_sh),\ 586 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_ENABLE, mask_sh),\ 587 HWS_SF(, VGA_TEST_CONTROL, VGA_TEST_RENDER_START, mask_sh) 588 589 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 590 #define HWSEQ_DCN30_MASK_SH_LIST(mask_sh)\ 591 HWSEQ_DCN2_MASK_SH_LIST(mask_sh), \ 592 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh) 593 #endif 594 595 #define HWSEQ_DCN2_MASK_SH_LIST(mask_sh)\ 596 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 597 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 598 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 599 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 600 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 601 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 602 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 603 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 604 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 605 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 606 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 607 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 608 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 609 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 610 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 611 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 612 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 613 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 614 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, mask_sh), \ 615 HWS_SF(, DOMAIN8_PG_CONFIG, DOMAIN8_POWER_GATE, mask_sh), \ 616 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, mask_sh), \ 617 HWS_SF(, DOMAIN9_PG_CONFIG, DOMAIN9_POWER_GATE, mask_sh), \ 618 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_FORCEON, mask_sh), \ 619 HWS_SF(, DOMAIN10_PG_CONFIG, DOMAIN10_POWER_GATE, mask_sh), \ 620 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_FORCEON, mask_sh), \ 621 HWS_SF(, DOMAIN11_PG_CONFIG, DOMAIN11_POWER_GATE, mask_sh), \ 622 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 623 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 624 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 625 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 626 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 627 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 628 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, mask_sh), \ 629 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN19_POWER_GATE, mask_sh), \ 630 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, mask_sh), \ 631 HWS_SF(, DOMAIN20_PG_CONFIG, DOMAIN20_POWER_GATE, mask_sh), \ 632 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, mask_sh), \ 633 HWS_SF(, DOMAIN21_PG_CONFIG, DOMAIN21_POWER_GATE, mask_sh), \ 634 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 635 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 636 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 637 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 638 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 639 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 640 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 641 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 642 HWS_SF(, DOMAIN8_PG_STATUS, DOMAIN8_PGFSM_PWR_STATUS, mask_sh), \ 643 HWS_SF(, DOMAIN9_PG_STATUS, DOMAIN9_PGFSM_PWR_STATUS, mask_sh), \ 644 HWS_SF(, DOMAIN10_PG_STATUS, DOMAIN10_PGFSM_PWR_STATUS, mask_sh), \ 645 HWS_SF(, DOMAIN11_PG_STATUS, DOMAIN11_PGFSM_PWR_STATUS, mask_sh), \ 646 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 647 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 648 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 649 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN19_PGFSM_PWR_STATUS, mask_sh), \ 650 HWS_SF(, DOMAIN20_PG_STATUS, DOMAIN20_PGFSM_PWR_STATUS, mask_sh), \ 651 HWS_SF(, DOMAIN21_PG_STATUS, DOMAIN21_PGFSM_PWR_STATUS, mask_sh), \ 652 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 653 654 #define HWSEQ_DCN21_MASK_SH_LIST(mask_sh)\ 655 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 656 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 657 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, PAGE_DIRECTORY_ENTRY_HI32, mask_sh),\ 658 HWS_SF(, MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, PAGE_DIRECTORY_ENTRY_LO32, mask_sh),\ 659 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, mask_sh), \ 660 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN0_POWER_GATE, mask_sh), \ 661 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, mask_sh), \ 662 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN1_POWER_GATE, mask_sh), \ 663 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, mask_sh), \ 664 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN2_POWER_GATE, mask_sh), \ 665 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, mask_sh), \ 666 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN3_POWER_GATE, mask_sh), \ 667 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, mask_sh), \ 668 HWS_SF(, DOMAIN4_PG_CONFIG, DOMAIN4_POWER_GATE, mask_sh), \ 669 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, mask_sh), \ 670 HWS_SF(, DOMAIN5_PG_CONFIG, DOMAIN5_POWER_GATE, mask_sh), \ 671 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, mask_sh), \ 672 HWS_SF(, DOMAIN6_PG_CONFIG, DOMAIN6_POWER_GATE, mask_sh), \ 673 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, mask_sh), \ 674 HWS_SF(, DOMAIN7_PG_CONFIG, DOMAIN7_POWER_GATE, mask_sh), \ 675 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, mask_sh), \ 676 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN16_POWER_GATE, mask_sh), \ 677 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, mask_sh), \ 678 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN17_POWER_GATE, mask_sh), \ 679 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, mask_sh), \ 680 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN18_POWER_GATE, mask_sh), \ 681 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN0_PGFSM_PWR_STATUS, mask_sh), \ 682 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN1_PGFSM_PWR_STATUS, mask_sh), \ 683 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN2_PGFSM_PWR_STATUS, mask_sh), \ 684 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN3_PGFSM_PWR_STATUS, mask_sh), \ 685 HWS_SF(, DOMAIN4_PG_STATUS, DOMAIN4_PGFSM_PWR_STATUS, mask_sh), \ 686 HWS_SF(, DOMAIN5_PG_STATUS, DOMAIN5_PGFSM_PWR_STATUS, mask_sh), \ 687 HWS_SF(, DOMAIN6_PG_STATUS, DOMAIN6_PGFSM_PWR_STATUS, mask_sh), \ 688 HWS_SF(, DOMAIN7_PG_STATUS, DOMAIN7_PGFSM_PWR_STATUS, mask_sh), \ 689 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN16_PGFSM_PWR_STATUS, mask_sh), \ 690 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \ 691 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \ 692 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh) 693 694 #define HWSEQ_REG_FIELD_LIST(type) \ 695 type DCFE_CLOCK_ENABLE; \ 696 type DCFEV_CLOCK_ENABLE; \ 697 type DC_MEM_GLOBAL_PWR_REQ_DIS; \ 698 type BLND_DCP_GRPH_V_UPDATE_LOCK; \ 699 type BLND_SCL_V_UPDATE_LOCK; \ 700 type BLND_DCP_GRPH_SURF_V_UPDATE_LOCK; \ 701 type BLND_BLND_V_UPDATE_LOCK; \ 702 type BLND_V_UPDATE_LOCK_MODE; \ 703 type BLND_FEEDTHROUGH_EN; \ 704 type BLND_ALPHA_MODE; \ 705 type BLND_MODE; \ 706 type BLND_MULTIPLIED_MODE; \ 707 type DP_DTO0_ENABLE; \ 708 type PIXEL_RATE_SOURCE; \ 709 type PHYPLL_PIXEL_RATE_SOURCE; \ 710 type PIXEL_RATE_PLL_SOURCE; \ 711 /* todo: get these from GVM instead of reading registers ourselves */\ 712 type PAGE_DIRECTORY_ENTRY_HI32;\ 713 type PAGE_DIRECTORY_ENTRY_LO32;\ 714 type LOGICAL_PAGE_NUMBER_HI4;\ 715 type LOGICAL_PAGE_NUMBER_LO32;\ 716 type PHYSICAL_PAGE_ADDR_HI4;\ 717 type PHYSICAL_PAGE_ADDR_LO32;\ 718 type PHYSICAL_PAGE_NUMBER_MSB;\ 719 type PHYSICAL_PAGE_NUMBER_LSB;\ 720 type LOGICAL_ADDR; \ 721 type PF_LFB_REGION;\ 722 type PF_MAX_REGION;\ 723 type ENABLE_L1_TLB;\ 724 type SYSTEM_ACCESS_MODE; 725 726 #define HWSEQ_DCN_REG_FIELD_LIST(type) \ 727 type HUBP_VTG_SEL; \ 728 type HUBP_CLOCK_ENABLE; \ 729 type DPP_CLOCK_ENABLE; \ 730 type SDPIF_FB_BASE;\ 731 type SDPIF_FB_OFFSET;\ 732 type SDPIF_AGP_BASE;\ 733 type SDPIF_AGP_BOT;\ 734 type SDPIF_AGP_TOP;\ 735 type FB_TOP;\ 736 type FB_BASE;\ 737 type FB_OFFSET;\ 738 type AGP_BASE;\ 739 type AGP_BOT;\ 740 type AGP_TOP;\ 741 type DCHUBBUB_GLOBAL_TIMER_ENABLE; \ 742 type OPP_PIPE_CLOCK_EN;\ 743 type IP_REQUEST_EN; \ 744 type DOMAIN0_POWER_FORCEON; \ 745 type DOMAIN0_POWER_GATE; \ 746 type DOMAIN1_POWER_FORCEON; \ 747 type DOMAIN1_POWER_GATE; \ 748 type DOMAIN2_POWER_FORCEON; \ 749 type DOMAIN2_POWER_GATE; \ 750 type DOMAIN3_POWER_FORCEON; \ 751 type DOMAIN3_POWER_GATE; \ 752 type DOMAIN4_POWER_FORCEON; \ 753 type DOMAIN4_POWER_GATE; \ 754 type DOMAIN5_POWER_FORCEON; \ 755 type DOMAIN5_POWER_GATE; \ 756 type DOMAIN6_POWER_FORCEON; \ 757 type DOMAIN6_POWER_GATE; \ 758 type DOMAIN7_POWER_FORCEON; \ 759 type DOMAIN7_POWER_GATE; \ 760 type DOMAIN8_POWER_FORCEON; \ 761 type DOMAIN8_POWER_GATE; \ 762 type DOMAIN9_POWER_FORCEON; \ 763 type DOMAIN9_POWER_GATE; \ 764 type DOMAIN10_POWER_FORCEON; \ 765 type DOMAIN10_POWER_GATE; \ 766 type DOMAIN11_POWER_FORCEON; \ 767 type DOMAIN11_POWER_GATE; \ 768 type DOMAIN16_POWER_FORCEON; \ 769 type DOMAIN16_POWER_GATE; \ 770 type DOMAIN17_POWER_FORCEON; \ 771 type DOMAIN17_POWER_GATE; \ 772 type DOMAIN18_POWER_FORCEON; \ 773 type DOMAIN18_POWER_GATE; \ 774 type DOMAIN19_POWER_FORCEON; \ 775 type DOMAIN19_POWER_GATE; \ 776 type DOMAIN20_POWER_FORCEON; \ 777 type DOMAIN20_POWER_GATE; \ 778 type DOMAIN21_POWER_FORCEON; \ 779 type DOMAIN21_POWER_GATE; \ 780 type DOMAIN0_PGFSM_PWR_STATUS; \ 781 type DOMAIN1_PGFSM_PWR_STATUS; \ 782 type DOMAIN2_PGFSM_PWR_STATUS; \ 783 type DOMAIN3_PGFSM_PWR_STATUS; \ 784 type DOMAIN4_PGFSM_PWR_STATUS; \ 785 type DOMAIN5_PGFSM_PWR_STATUS; \ 786 type DOMAIN6_PGFSM_PWR_STATUS; \ 787 type DOMAIN7_PGFSM_PWR_STATUS; \ 788 type DOMAIN8_PGFSM_PWR_STATUS; \ 789 type DOMAIN9_PGFSM_PWR_STATUS; \ 790 type DOMAIN10_PGFSM_PWR_STATUS; \ 791 type DOMAIN11_PGFSM_PWR_STATUS; \ 792 type DOMAIN16_PGFSM_PWR_STATUS; \ 793 type DOMAIN17_PGFSM_PWR_STATUS; \ 794 type DOMAIN18_PGFSM_PWR_STATUS; \ 795 type DOMAIN19_PGFSM_PWR_STATUS; \ 796 type DOMAIN20_PGFSM_PWR_STATUS; \ 797 type DOMAIN21_PGFSM_PWR_STATUS; \ 798 type DCFCLK_GATE_DIS; \ 799 type DCHUBBUB_GLOBAL_TIMER_REFDIV; \ 800 type VGA_TEST_ENABLE; \ 801 type VGA_TEST_RENDER_START; \ 802 type D1VGA_MODE_ENABLE; \ 803 type D2VGA_MODE_ENABLE; \ 804 type D3VGA_MODE_ENABLE; \ 805 type D4VGA_MODE_ENABLE; \ 806 type AZALIA_AUDIO_DTO_MODULE; 807 808 struct dce_hwseq_shift { 809 HWSEQ_REG_FIELD_LIST(uint8_t) 810 HWSEQ_DCN_REG_FIELD_LIST(uint8_t) 811 }; 812 813 struct dce_hwseq_mask { 814 HWSEQ_REG_FIELD_LIST(uint32_t) 815 HWSEQ_DCN_REG_FIELD_LIST(uint32_t) 816 }; 817 818 819 enum blnd_mode { 820 BLND_MODE_CURRENT_PIPE = 0,/* Data from current pipe only */ 821 BLND_MODE_OTHER_PIPE, /* Data from other pipe only */ 822 BLND_MODE_BLENDING,/* Alpha blending - blend 'current' and 'other' */ 823 }; 824 825 struct dce_hwseq; 826 struct pipe_ctx; 827 struct clock_source; 828 829 void dce_enable_fe_clock(struct dce_hwseq *hwss, 830 unsigned int inst, bool enable); 831 832 void dce_pipe_control_lock(struct dc *dc, 833 struct pipe_ctx *pipe, 834 bool lock); 835 836 void dce_set_blender_mode(struct dce_hwseq *hws, 837 unsigned int blnd_inst, enum blnd_mode mode); 838 839 void dce_clock_gating_power_up(struct dce_hwseq *hws, 840 bool enable); 841 842 void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, 843 struct clock_source *clk_src, 844 unsigned int tg_inst); 845 846 bool dce_use_lut(enum surface_pixel_format format); 847 #endif /*__DCE_HWSEQ_H__*/ 848