1 /* 2 * Copyright © 2006-2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric@anholt.net> 25 */ 26 27 #include <linux/dmi.h> 28 #include <linux/i2c.h> 29 #include <linux/slab.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc.h> 33 #include <drm/drm_edid.h> 34 #include <drm/drm_probe_helper.h> 35 #include <drm/i915_drm.h> 36 37 #include "i915_drv.h" 38 #include "intel_connector.h" 39 #include "intel_crt.h" 40 #include "intel_ddi.h" 41 #include "intel_display_types.h" 42 #include "intel_fifo_underrun.h" 43 #include "intel_gmbus.h" 44 #include "intel_hotplug.h" 45 46 /* Here's the desired hotplug mode */ 47 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ 48 ADPA_CRT_HOTPLUG_WARMUP_10MS | \ 49 ADPA_CRT_HOTPLUG_SAMPLE_4S | \ 50 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ 51 ADPA_CRT_HOTPLUG_VOLREF_325MV | \ 52 ADPA_CRT_HOTPLUG_ENABLE) 53 54 struct intel_crt { 55 struct intel_encoder base; 56 /* DPMS state is stored in the connector, which we need in the 57 * encoder's enable/disable callbacks */ 58 struct intel_connector *connector; 59 bool force_hotplug_required; 60 i915_reg_t adpa_reg; 61 }; 62 63 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) 64 { 65 return container_of(encoder, struct intel_crt, base); 66 } 67 68 static struct intel_crt *intel_attached_crt(struct intel_connector *connector) 69 { 70 return intel_encoder_to_crt(intel_attached_encoder(connector)); 71 } 72 73 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, 74 i915_reg_t adpa_reg, enum pipe *pipe) 75 { 76 u32 val; 77 78 val = I915_READ(adpa_reg); 79 80 /* asserts want to know the pipe even if the port is disabled */ 81 if (HAS_PCH_CPT(dev_priv)) 82 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; 83 else 84 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; 85 86 return val & ADPA_DAC_ENABLE; 87 } 88 89 static bool intel_crt_get_hw_state(struct intel_encoder *encoder, 90 enum pipe *pipe) 91 { 92 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 93 struct intel_crt *crt = intel_encoder_to_crt(encoder); 94 intel_wakeref_t wakeref; 95 bool ret; 96 97 wakeref = intel_display_power_get_if_enabled(dev_priv, 98 encoder->power_domain); 99 if (!wakeref) 100 return false; 101 102 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); 103 104 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 105 106 return ret; 107 } 108 109 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) 110 { 111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 112 struct intel_crt *crt = intel_encoder_to_crt(encoder); 113 u32 tmp, flags = 0; 114 115 tmp = I915_READ(crt->adpa_reg); 116 117 if (tmp & ADPA_HSYNC_ACTIVE_HIGH) 118 flags |= DRM_MODE_FLAG_PHSYNC; 119 else 120 flags |= DRM_MODE_FLAG_NHSYNC; 121 122 if (tmp & ADPA_VSYNC_ACTIVE_HIGH) 123 flags |= DRM_MODE_FLAG_PVSYNC; 124 else 125 flags |= DRM_MODE_FLAG_NVSYNC; 126 127 return flags; 128 } 129 130 static void intel_crt_get_config(struct intel_encoder *encoder, 131 struct intel_crtc_state *pipe_config) 132 { 133 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); 134 135 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 136 137 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; 138 } 139 140 static void hsw_crt_get_config(struct intel_encoder *encoder, 141 struct intel_crtc_state *pipe_config) 142 { 143 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 144 145 intel_ddi_get_config(encoder, pipe_config); 146 147 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | 148 DRM_MODE_FLAG_NHSYNC | 149 DRM_MODE_FLAG_PVSYNC | 150 DRM_MODE_FLAG_NVSYNC); 151 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); 152 153 pipe_config->hw.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); 154 } 155 156 /* Note: The caller is required to filter out dpms modes not supported by the 157 * platform. */ 158 static void intel_crt_set_dpms(struct intel_encoder *encoder, 159 const struct intel_crtc_state *crtc_state, 160 int mode) 161 { 162 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 163 struct intel_crt *crt = intel_encoder_to_crt(encoder); 164 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 165 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 166 u32 adpa; 167 168 if (INTEL_GEN(dev_priv) >= 5) 169 adpa = ADPA_HOTPLUG_BITS; 170 else 171 adpa = 0; 172 173 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 174 adpa |= ADPA_HSYNC_ACTIVE_HIGH; 175 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 176 adpa |= ADPA_VSYNC_ACTIVE_HIGH; 177 178 /* For CPT allow 3 pipe config, for others just use A or B */ 179 if (HAS_PCH_LPT(dev_priv)) 180 ; /* Those bits don't exist here */ 181 else if (HAS_PCH_CPT(dev_priv)) 182 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); 183 else 184 adpa |= ADPA_PIPE_SEL(crtc->pipe); 185 186 if (!HAS_PCH_SPLIT(dev_priv)) 187 I915_WRITE(BCLRPAT(crtc->pipe), 0); 188 189 switch (mode) { 190 case DRM_MODE_DPMS_ON: 191 adpa |= ADPA_DAC_ENABLE; 192 break; 193 case DRM_MODE_DPMS_STANDBY: 194 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; 195 break; 196 case DRM_MODE_DPMS_SUSPEND: 197 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; 198 break; 199 case DRM_MODE_DPMS_OFF: 200 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; 201 break; 202 } 203 204 I915_WRITE(crt->adpa_reg, adpa); 205 } 206 207 static void intel_disable_crt(struct intel_encoder *encoder, 208 const struct intel_crtc_state *old_crtc_state, 209 const struct drm_connector_state *old_conn_state) 210 { 211 intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); 212 } 213 214 static void pch_disable_crt(struct intel_encoder *encoder, 215 const struct intel_crtc_state *old_crtc_state, 216 const struct drm_connector_state *old_conn_state) 217 { 218 } 219 220 static void pch_post_disable_crt(struct intel_encoder *encoder, 221 const struct intel_crtc_state *old_crtc_state, 222 const struct drm_connector_state *old_conn_state) 223 { 224 intel_disable_crt(encoder, old_crtc_state, old_conn_state); 225 } 226 227 static void hsw_disable_crt(struct intel_encoder *encoder, 228 const struct intel_crtc_state *old_crtc_state, 229 const struct drm_connector_state *old_conn_state) 230 { 231 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 232 233 WARN_ON(!old_crtc_state->has_pch_encoder); 234 235 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 236 } 237 238 static void hsw_post_disable_crt(struct intel_encoder *encoder, 239 const struct intel_crtc_state *old_crtc_state, 240 const struct drm_connector_state *old_conn_state) 241 { 242 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 243 244 intel_crtc_vblank_off(old_crtc_state); 245 246 intel_disable_pipe(old_crtc_state); 247 248 intel_ddi_disable_transcoder_func(old_crtc_state); 249 250 ilk_pfit_disable(old_crtc_state); 251 252 intel_ddi_disable_pipe_clock(old_crtc_state); 253 254 pch_post_disable_crt(encoder, old_crtc_state, old_conn_state); 255 256 lpt_disable_pch_transcoder(dev_priv); 257 lpt_disable_iclkip(dev_priv); 258 259 intel_ddi_fdi_post_disable(encoder, old_crtc_state, old_conn_state); 260 261 WARN_ON(!old_crtc_state->has_pch_encoder); 262 263 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 264 } 265 266 static void hsw_pre_pll_enable_crt(struct intel_encoder *encoder, 267 const struct intel_crtc_state *crtc_state, 268 const struct drm_connector_state *conn_state) 269 { 270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 271 272 WARN_ON(!crtc_state->has_pch_encoder); 273 274 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 275 } 276 277 static void hsw_pre_enable_crt(struct intel_encoder *encoder, 278 const struct intel_crtc_state *crtc_state, 279 const struct drm_connector_state *conn_state) 280 { 281 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 282 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 283 enum pipe pipe = crtc->pipe; 284 285 WARN_ON(!crtc_state->has_pch_encoder); 286 287 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); 288 289 hsw_fdi_link_train(encoder, crtc_state); 290 291 intel_ddi_enable_pipe_clock(crtc_state); 292 } 293 294 static void hsw_enable_crt(struct intel_encoder *encoder, 295 const struct intel_crtc_state *crtc_state, 296 const struct drm_connector_state *conn_state) 297 { 298 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 299 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 300 enum pipe pipe = crtc->pipe; 301 302 WARN_ON(!crtc_state->has_pch_encoder); 303 304 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 305 306 intel_wait_for_vblank(dev_priv, pipe); 307 intel_wait_for_vblank(dev_priv, pipe); 308 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); 309 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 310 } 311 312 static void intel_enable_crt(struct intel_encoder *encoder, 313 const struct intel_crtc_state *crtc_state, 314 const struct drm_connector_state *conn_state) 315 { 316 intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); 317 } 318 319 static enum drm_mode_status 320 intel_crt_mode_valid(struct drm_connector *connector, 321 struct drm_display_mode *mode) 322 { 323 struct drm_device *dev = connector->dev; 324 struct drm_i915_private *dev_priv = to_i915(dev); 325 int max_dotclk = dev_priv->max_dotclk_freq; 326 int max_clock; 327 328 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 329 return MODE_NO_DBLESCAN; 330 331 if (mode->clock < 25000) 332 return MODE_CLOCK_LOW; 333 334 if (HAS_PCH_LPT(dev_priv)) 335 max_clock = 180000; 336 else if (IS_VALLEYVIEW(dev_priv)) 337 /* 338 * 270 MHz due to current DPLL limits, 339 * DAC limit supposedly 355 MHz. 340 */ 341 max_clock = 270000; 342 else if (IS_GEN_RANGE(dev_priv, 3, 4)) 343 max_clock = 400000; 344 else 345 max_clock = 350000; 346 if (mode->clock > max_clock) 347 return MODE_CLOCK_HIGH; 348 349 if (mode->clock > max_dotclk) 350 return MODE_CLOCK_HIGH; 351 352 /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ 353 if (HAS_PCH_LPT(dev_priv) && 354 ilk_get_lanes_required(mode->clock, 270000, 24) > 2) 355 return MODE_CLOCK_HIGH; 356 357 /* HSW/BDW FDI limited to 4k */ 358 if (mode->hdisplay > 4096) 359 return MODE_H_ILLEGAL; 360 361 return MODE_OK; 362 } 363 364 static int intel_crt_compute_config(struct intel_encoder *encoder, 365 struct intel_crtc_state *pipe_config, 366 struct drm_connector_state *conn_state) 367 { 368 struct drm_display_mode *adjusted_mode = 369 &pipe_config->hw.adjusted_mode; 370 371 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 372 return -EINVAL; 373 374 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 375 376 return 0; 377 } 378 379 static int pch_crt_compute_config(struct intel_encoder *encoder, 380 struct intel_crtc_state *pipe_config, 381 struct drm_connector_state *conn_state) 382 { 383 struct drm_display_mode *adjusted_mode = 384 &pipe_config->hw.adjusted_mode; 385 386 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 387 return -EINVAL; 388 389 pipe_config->has_pch_encoder = true; 390 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 391 392 return 0; 393 } 394 395 static int hsw_crt_compute_config(struct intel_encoder *encoder, 396 struct intel_crtc_state *pipe_config, 397 struct drm_connector_state *conn_state) 398 { 399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 400 struct drm_display_mode *adjusted_mode = 401 &pipe_config->hw.adjusted_mode; 402 403 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 404 return -EINVAL; 405 406 /* HSW/BDW FDI limited to 4k */ 407 if (adjusted_mode->crtc_hdisplay > 4096 || 408 adjusted_mode->crtc_hblank_start > 4096) 409 return -EINVAL; 410 411 pipe_config->has_pch_encoder = true; 412 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 413 414 /* LPT FDI RX only supports 8bpc. */ 415 if (HAS_PCH_LPT(dev_priv)) { 416 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { 417 DRM_DEBUG_KMS("LPT only supports 24bpp\n"); 418 return -EINVAL; 419 } 420 421 pipe_config->pipe_bpp = 24; 422 } 423 424 /* FDI must always be 2.7 GHz */ 425 pipe_config->port_clock = 135000 * 2; 426 427 return 0; 428 } 429 430 static bool ilk_crt_detect_hotplug(struct drm_connector *connector) 431 { 432 struct drm_device *dev = connector->dev; 433 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 434 struct drm_i915_private *dev_priv = to_i915(dev); 435 u32 adpa; 436 bool ret; 437 438 /* The first time through, trigger an explicit detection cycle */ 439 if (crt->force_hotplug_required) { 440 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); 441 u32 save_adpa; 442 443 crt->force_hotplug_required = false; 444 445 save_adpa = adpa = I915_READ(crt->adpa_reg); 446 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 447 448 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 449 if (turn_off_dac) 450 adpa &= ~ADPA_DAC_ENABLE; 451 452 I915_WRITE(crt->adpa_reg, adpa); 453 454 if (intel_de_wait_for_clear(dev_priv, 455 crt->adpa_reg, 456 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 457 1000)) 458 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 459 460 if (turn_off_dac) { 461 I915_WRITE(crt->adpa_reg, save_adpa); 462 POSTING_READ(crt->adpa_reg); 463 } 464 } 465 466 /* Check the status to see if both blue and green are on now */ 467 adpa = I915_READ(crt->adpa_reg); 468 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 469 ret = true; 470 else 471 ret = false; 472 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); 473 474 return ret; 475 } 476 477 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) 478 { 479 struct drm_device *dev = connector->dev; 480 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 481 struct drm_i915_private *dev_priv = to_i915(dev); 482 bool reenable_hpd; 483 u32 adpa; 484 bool ret; 485 u32 save_adpa; 486 487 /* 488 * Doing a force trigger causes a hpd interrupt to get sent, which can 489 * get us stuck in a loop if we're polling: 490 * - We enable power wells and reset the ADPA 491 * - output_poll_exec does force probe on VGA, triggering a hpd 492 * - HPD handler waits for poll to unlock dev->mode_config.mutex 493 * - output_poll_exec shuts off the ADPA, unlocks 494 * dev->mode_config.mutex 495 * - HPD handler runs, resets ADPA and brings us back to the start 496 * 497 * Just disable HPD interrupts here to prevent this 498 */ 499 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); 500 501 save_adpa = adpa = I915_READ(crt->adpa_reg); 502 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); 503 504 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; 505 506 I915_WRITE(crt->adpa_reg, adpa); 507 508 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, 509 ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) { 510 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); 511 I915_WRITE(crt->adpa_reg, save_adpa); 512 } 513 514 /* Check the status to see if both blue and green are on now */ 515 adpa = I915_READ(crt->adpa_reg); 516 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) 517 ret = true; 518 else 519 ret = false; 520 521 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); 522 523 if (reenable_hpd) 524 intel_hpd_enable(dev_priv, crt->base.hpd_pin); 525 526 return ret; 527 } 528 529 static bool intel_crt_detect_hotplug(struct drm_connector *connector) 530 { 531 struct drm_device *dev = connector->dev; 532 struct drm_i915_private *dev_priv = to_i915(dev); 533 u32 stat; 534 bool ret = false; 535 int i, tries = 0; 536 537 if (HAS_PCH_SPLIT(dev_priv)) 538 return ilk_crt_detect_hotplug(connector); 539 540 if (IS_VALLEYVIEW(dev_priv)) 541 return valleyview_crt_detect_hotplug(connector); 542 543 /* 544 * On 4 series desktop, CRT detect sequence need to be done twice 545 * to get a reliable result. 546 */ 547 548 if (IS_G45(dev_priv)) 549 tries = 2; 550 else 551 tries = 1; 552 553 for (i = 0; i < tries ; i++) { 554 /* turn on the FORCE_DETECT */ 555 i915_hotplug_interrupt_update(dev_priv, 556 CRT_HOTPLUG_FORCE_DETECT, 557 CRT_HOTPLUG_FORCE_DETECT); 558 /* wait for FORCE_DETECT to go off */ 559 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN, 560 CRT_HOTPLUG_FORCE_DETECT, 1000)) 561 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); 562 } 563 564 stat = I915_READ(PORT_HOTPLUG_STAT); 565 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) 566 ret = true; 567 568 /* clear the interrupt we just generated, if any */ 569 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); 570 571 i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); 572 573 return ret; 574 } 575 576 static struct edid *intel_crt_get_edid(struct drm_connector *connector, 577 struct i2c_adapter *i2c) 578 { 579 struct edid *edid; 580 581 edid = drm_get_edid(connector, i2c); 582 583 if (!edid && !intel_gmbus_is_forced_bit(i2c)) { 584 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); 585 intel_gmbus_force_bit(i2c, true); 586 edid = drm_get_edid(connector, i2c); 587 intel_gmbus_force_bit(i2c, false); 588 } 589 590 return edid; 591 } 592 593 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ 594 static int intel_crt_ddc_get_modes(struct drm_connector *connector, 595 struct i2c_adapter *adapter) 596 { 597 struct edid *edid; 598 int ret; 599 600 edid = intel_crt_get_edid(connector, adapter); 601 if (!edid) 602 return 0; 603 604 ret = intel_connector_update_modes(connector, edid); 605 kfree(edid); 606 607 return ret; 608 } 609 610 static bool intel_crt_detect_ddc(struct drm_connector *connector) 611 { 612 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 613 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); 614 struct edid *edid; 615 struct i2c_adapter *i2c; 616 bool ret = false; 617 618 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); 619 620 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 621 edid = intel_crt_get_edid(connector, i2c); 622 623 if (edid) { 624 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; 625 626 /* 627 * This may be a DVI-I connector with a shared DDC 628 * link between analog and digital outputs, so we 629 * have to check the EDID input spec of the attached device. 630 */ 631 if (!is_digital) { 632 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); 633 ret = true; 634 } else { 635 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); 636 } 637 } else { 638 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); 639 } 640 641 kfree(edid); 642 643 return ret; 644 } 645 646 static enum drm_connector_status 647 intel_crt_load_detect(struct intel_crt *crt, u32 pipe) 648 { 649 struct drm_device *dev = crt->base.base.dev; 650 struct drm_i915_private *dev_priv = to_i915(dev); 651 struct intel_uncore *uncore = &dev_priv->uncore; 652 u32 save_bclrpat; 653 u32 save_vtotal; 654 u32 vtotal, vactive; 655 u32 vsample; 656 u32 vblank, vblank_start, vblank_end; 657 u32 dsl; 658 i915_reg_t bclrpat_reg, vtotal_reg, 659 vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; 660 u8 st00; 661 enum drm_connector_status status; 662 663 DRM_DEBUG_KMS("starting load-detect on CRT\n"); 664 665 bclrpat_reg = BCLRPAT(pipe); 666 vtotal_reg = VTOTAL(pipe); 667 vblank_reg = VBLANK(pipe); 668 vsync_reg = VSYNC(pipe); 669 pipeconf_reg = PIPECONF(pipe); 670 pipe_dsl_reg = PIPEDSL(pipe); 671 672 save_bclrpat = intel_uncore_read(uncore, bclrpat_reg); 673 save_vtotal = intel_uncore_read(uncore, vtotal_reg); 674 vblank = intel_uncore_read(uncore, vblank_reg); 675 676 vtotal = ((save_vtotal >> 16) & 0xfff) + 1; 677 vactive = (save_vtotal & 0x7ff) + 1; 678 679 vblank_start = (vblank & 0xfff) + 1; 680 vblank_end = ((vblank >> 16) & 0xfff) + 1; 681 682 /* Set the border color to purple. */ 683 intel_uncore_write(uncore, bclrpat_reg, 0x500050); 684 685 if (!IS_GEN(dev_priv, 2)) { 686 u32 pipeconf = intel_uncore_read(uncore, pipeconf_reg); 687 intel_uncore_write(uncore, 688 pipeconf_reg, 689 pipeconf | PIPECONF_FORCE_BORDER); 690 intel_uncore_posting_read(uncore, pipeconf_reg); 691 /* Wait for next Vblank to substitue 692 * border color for Color info */ 693 intel_wait_for_vblank(dev_priv, pipe); 694 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE); 695 status = ((st00 & (1 << 4)) != 0) ? 696 connector_status_connected : 697 connector_status_disconnected; 698 699 intel_uncore_write(uncore, pipeconf_reg, pipeconf); 700 } else { 701 bool restore_vblank = false; 702 int count, detect; 703 704 /* 705 * If there isn't any border, add some. 706 * Yes, this will flicker 707 */ 708 if (vblank_start <= vactive && vblank_end >= vtotal) { 709 u32 vsync = I915_READ(vsync_reg); 710 u32 vsync_start = (vsync & 0xffff) + 1; 711 712 vblank_start = vsync_start; 713 intel_uncore_write(uncore, 714 vblank_reg, 715 (vblank_start - 1) | 716 ((vblank_end - 1) << 16)); 717 restore_vblank = true; 718 } 719 /* sample in the vertical border, selecting the larger one */ 720 if (vblank_start - vactive >= vtotal - vblank_end) 721 vsample = (vblank_start + vactive) >> 1; 722 else 723 vsample = (vtotal + vblank_end) >> 1; 724 725 /* 726 * Wait for the border to be displayed 727 */ 728 while (intel_uncore_read(uncore, pipe_dsl_reg) >= vactive) 729 ; 730 while ((dsl = intel_uncore_read(uncore, pipe_dsl_reg)) <= 731 vsample) 732 ; 733 /* 734 * Watch ST00 for an entire scanline 735 */ 736 detect = 0; 737 count = 0; 738 do { 739 count++; 740 /* Read the ST00 VGA status register */ 741 st00 = intel_uncore_read8(uncore, _VGA_MSR_WRITE); 742 if (st00 & (1 << 4)) 743 detect++; 744 } while ((intel_uncore_read(uncore, pipe_dsl_reg) == dsl)); 745 746 /* restore vblank if necessary */ 747 if (restore_vblank) 748 intel_uncore_write(uncore, vblank_reg, vblank); 749 /* 750 * If more than 3/4 of the scanline detected a monitor, 751 * then it is assumed to be present. This works even on i830, 752 * where there isn't any way to force the border color across 753 * the screen 754 */ 755 status = detect * 4 > count * 3 ? 756 connector_status_connected : 757 connector_status_disconnected; 758 } 759 760 /* Restore previous settings */ 761 intel_uncore_write(uncore, bclrpat_reg, save_bclrpat); 762 763 return status; 764 } 765 766 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) 767 { 768 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); 769 return 1; 770 } 771 772 static const struct dmi_system_id intel_spurious_crt_detect[] = { 773 { 774 .callback = intel_spurious_crt_detect_dmi_callback, 775 .ident = "ACER ZGB", 776 .matches = { 777 DMI_MATCH(DMI_SYS_VENDOR, "ACER"), 778 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), 779 }, 780 }, 781 { 782 .callback = intel_spurious_crt_detect_dmi_callback, 783 .ident = "Intel DZ77BH-55K", 784 .matches = { 785 DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), 786 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), 787 }, 788 }, 789 { } 790 }; 791 792 static int 793 intel_crt_detect(struct drm_connector *connector, 794 struct drm_modeset_acquire_ctx *ctx, 795 bool force) 796 { 797 struct drm_i915_private *dev_priv = to_i915(connector->dev); 798 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 799 struct intel_encoder *intel_encoder = &crt->base; 800 intel_wakeref_t wakeref; 801 int status, ret; 802 struct intel_load_detect_pipe tmp; 803 804 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", 805 connector->base.id, connector->name, 806 force); 807 808 if (i915_modparams.load_detect_test) { 809 wakeref = intel_display_power_get(dev_priv, 810 intel_encoder->power_domain); 811 goto load_detect; 812 } 813 814 /* Skip machines without VGA that falsely report hotplug events */ 815 if (dmi_check_system(intel_spurious_crt_detect)) 816 return connector_status_disconnected; 817 818 wakeref = intel_display_power_get(dev_priv, 819 intel_encoder->power_domain); 820 821 if (I915_HAS_HOTPLUG(dev_priv)) { 822 /* We can not rely on the HPD pin always being correctly wired 823 * up, for example many KVM do not pass it through, and so 824 * only trust an assertion that the monitor is connected. 825 */ 826 if (intel_crt_detect_hotplug(connector)) { 827 DRM_DEBUG_KMS("CRT detected via hotplug\n"); 828 status = connector_status_connected; 829 goto out; 830 } else 831 DRM_DEBUG_KMS("CRT not detected via hotplug\n"); 832 } 833 834 if (intel_crt_detect_ddc(connector)) { 835 status = connector_status_connected; 836 goto out; 837 } 838 839 /* Load detection is broken on HPD capable machines. Whoever wants a 840 * broken monitor (without edid) to work behind a broken kvm (that fails 841 * to have the right resistors for HP detection) needs to fix this up. 842 * For now just bail out. */ 843 if (I915_HAS_HOTPLUG(dev_priv)) { 844 status = connector_status_disconnected; 845 goto out; 846 } 847 848 load_detect: 849 if (!force) { 850 status = connector->status; 851 goto out; 852 } 853 854 /* for pre-945g platforms use load detect */ 855 ret = intel_get_load_detect_pipe(connector, &tmp, ctx); 856 if (ret > 0) { 857 if (intel_crt_detect_ddc(connector)) 858 status = connector_status_connected; 859 else if (INTEL_GEN(dev_priv) < 4) 860 status = intel_crt_load_detect(crt, 861 to_intel_crtc(connector->state->crtc)->pipe); 862 else if (i915_modparams.load_detect_test) 863 status = connector_status_disconnected; 864 else 865 status = connector_status_unknown; 866 intel_release_load_detect_pipe(connector, &tmp, ctx); 867 } else if (ret == 0) { 868 status = connector_status_unknown; 869 } else { 870 status = ret; 871 } 872 873 out: 874 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 875 876 /* 877 * Make sure the refs for power wells enabled during detect are 878 * dropped to avoid a new detect cycle triggered by HPD polling. 879 */ 880 intel_display_power_flush_work(dev_priv); 881 882 return status; 883 } 884 885 static int intel_crt_get_modes(struct drm_connector *connector) 886 { 887 struct drm_device *dev = connector->dev; 888 struct drm_i915_private *dev_priv = to_i915(dev); 889 struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); 890 struct intel_encoder *intel_encoder = &crt->base; 891 intel_wakeref_t wakeref; 892 struct i2c_adapter *i2c; 893 int ret; 894 895 wakeref = intel_display_power_get(dev_priv, 896 intel_encoder->power_domain); 897 898 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); 899 ret = intel_crt_ddc_get_modes(connector, i2c); 900 if (ret || !IS_G4X(dev_priv)) 901 goto out; 902 903 /* Try to probe digital port for output in DVI-I -> VGA mode. */ 904 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); 905 ret = intel_crt_ddc_get_modes(connector, i2c); 906 907 out: 908 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); 909 910 return ret; 911 } 912 913 void intel_crt_reset(struct drm_encoder *encoder) 914 { 915 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 916 struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); 917 918 if (INTEL_GEN(dev_priv) >= 5) { 919 u32 adpa; 920 921 adpa = I915_READ(crt->adpa_reg); 922 adpa &= ~ADPA_CRT_HOTPLUG_MASK; 923 adpa |= ADPA_HOTPLUG_BITS; 924 I915_WRITE(crt->adpa_reg, adpa); 925 POSTING_READ(crt->adpa_reg); 926 927 DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); 928 crt->force_hotplug_required = true; 929 } 930 931 } 932 933 /* 934 * Routines for controlling stuff on the analog port 935 */ 936 937 static const struct drm_connector_funcs intel_crt_connector_funcs = { 938 .fill_modes = drm_helper_probe_single_connector_modes, 939 .late_register = intel_connector_register, 940 .early_unregister = intel_connector_unregister, 941 .destroy = intel_connector_destroy, 942 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 943 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 944 }; 945 946 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { 947 .detect_ctx = intel_crt_detect, 948 .mode_valid = intel_crt_mode_valid, 949 .get_modes = intel_crt_get_modes, 950 }; 951 952 static const struct drm_encoder_funcs intel_crt_enc_funcs = { 953 .reset = intel_crt_reset, 954 .destroy = intel_encoder_destroy, 955 }; 956 957 void intel_crt_init(struct drm_i915_private *dev_priv) 958 { 959 struct drm_connector *connector; 960 struct intel_crt *crt; 961 struct intel_connector *intel_connector; 962 i915_reg_t adpa_reg; 963 u32 adpa; 964 965 if (HAS_PCH_SPLIT(dev_priv)) 966 adpa_reg = PCH_ADPA; 967 else if (IS_VALLEYVIEW(dev_priv)) 968 adpa_reg = VLV_ADPA; 969 else 970 adpa_reg = ADPA; 971 972 adpa = I915_READ(adpa_reg); 973 if ((adpa & ADPA_DAC_ENABLE) == 0) { 974 /* 975 * On some machines (some IVB at least) CRT can be 976 * fused off, but there's no known fuse bit to 977 * indicate that. On these machine the ADPA register 978 * works normally, except the DAC enable bit won't 979 * take. So the only way to tell is attempt to enable 980 * it and see what happens. 981 */ 982 I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | 983 ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); 984 if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) 985 return; 986 I915_WRITE(adpa_reg, adpa); 987 } 988 989 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); 990 if (!crt) 991 return; 992 993 intel_connector = intel_connector_alloc(); 994 if (!intel_connector) { 995 kfree(crt); 996 return; 997 } 998 999 connector = &intel_connector->base; 1000 crt->connector = intel_connector; 1001 drm_connector_init(&dev_priv->drm, &intel_connector->base, 1002 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); 1003 1004 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, 1005 DRM_MODE_ENCODER_DAC, "CRT"); 1006 1007 intel_connector_attach_encoder(intel_connector, &crt->base); 1008 1009 crt->base.type = INTEL_OUTPUT_ANALOG; 1010 crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); 1011 if (IS_I830(dev_priv)) 1012 crt->base.pipe_mask = BIT(PIPE_A); 1013 else 1014 crt->base.pipe_mask = ~0; 1015 1016 if (IS_GEN(dev_priv, 2)) 1017 connector->interlace_allowed = 0; 1018 else 1019 connector->interlace_allowed = 1; 1020 connector->doublescan_allowed = 0; 1021 1022 crt->adpa_reg = adpa_reg; 1023 1024 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; 1025 1026 if (I915_HAS_HOTPLUG(dev_priv) && 1027 !dmi_check_system(intel_spurious_crt_detect)) { 1028 crt->base.hpd_pin = HPD_CRT; 1029 crt->base.hotplug = intel_encoder_hotplug; 1030 } 1031 1032 if (HAS_DDI(dev_priv)) { 1033 crt->base.port = PORT_E; 1034 crt->base.get_config = hsw_crt_get_config; 1035 crt->base.get_hw_state = intel_ddi_get_hw_state; 1036 crt->base.compute_config = hsw_crt_compute_config; 1037 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; 1038 crt->base.pre_enable = hsw_pre_enable_crt; 1039 crt->base.enable = hsw_enable_crt; 1040 crt->base.disable = hsw_disable_crt; 1041 crt->base.post_disable = hsw_post_disable_crt; 1042 } else { 1043 if (HAS_PCH_SPLIT(dev_priv)) { 1044 crt->base.compute_config = pch_crt_compute_config; 1045 crt->base.disable = pch_disable_crt; 1046 crt->base.post_disable = pch_post_disable_crt; 1047 } else { 1048 crt->base.compute_config = intel_crt_compute_config; 1049 crt->base.disable = intel_disable_crt; 1050 } 1051 crt->base.port = PORT_NONE; 1052 crt->base.get_config = intel_crt_get_config; 1053 crt->base.get_hw_state = intel_crt_get_hw_state; 1054 crt->base.enable = intel_enable_crt; 1055 } 1056 intel_connector->get_hw_state = intel_connector_get_hw_state; 1057 1058 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); 1059 1060 if (!I915_HAS_HOTPLUG(dev_priv)) 1061 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 1062 1063 /* 1064 * Configure the automatic hotplug detection stuff 1065 */ 1066 crt->force_hotplug_required = false; 1067 1068 /* 1069 * TODO: find a proper way to discover whether we need to set the the 1070 * polarity and link reversal bits or not, instead of relying on the 1071 * BIOS. 1072 */ 1073 if (HAS_PCH_LPT(dev_priv)) { 1074 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | 1075 FDI_RX_LINK_REVERSAL_OVERRIDE; 1076 1077 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; 1078 } 1079 1080 intel_crt_reset(&crt->base.base); 1081 } 1082