1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2020, Intel Corporation 3 */ 4 5 #include <linux/clk-provider.h> 6 #include <linux/pci.h> 7 #include <linux/dmi.h> 8 #include "stmmac.h" 9 10 /* This struct is used to associate PCI Function of MAC controller on a board, 11 * discovered via DMI, with the address of PHY connected to the MAC. The 12 * negative value of the address means that MAC controller is not connected 13 * with PHY. 14 */ 15 struct stmmac_pci_func_data { 16 unsigned int func; 17 int phy_addr; 18 }; 19 20 struct stmmac_pci_dmi_data { 21 const struct stmmac_pci_func_data *func; 22 size_t nfuncs; 23 }; 24 25 struct stmmac_pci_info { 26 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat); 27 }; 28 29 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev, 30 const struct dmi_system_id *dmi_list) 31 { 32 const struct stmmac_pci_func_data *func_data; 33 const struct stmmac_pci_dmi_data *dmi_data; 34 const struct dmi_system_id *dmi_id; 35 int func = PCI_FUNC(pdev->devfn); 36 size_t n; 37 38 dmi_id = dmi_first_match(dmi_list); 39 if (!dmi_id) 40 return -ENODEV; 41 42 dmi_data = dmi_id->driver_data; 43 func_data = dmi_data->func; 44 45 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) 46 if (func_data->func == func) 47 return func_data->phy_addr; 48 49 return -ENODEV; 50 } 51 52 static void common_default_data(struct plat_stmmacenet_data *plat) 53 { 54 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ 55 plat->has_gmac = 1; 56 plat->force_sf_dma_mode = 1; 57 58 plat->mdio_bus_data->needs_reset = true; 59 60 /* Set default value for multicast hash bins */ 61 plat->multicast_filter_bins = HASH_TABLE_SIZE; 62 63 /* Set default value for unicast filter entries */ 64 plat->unicast_filter_entries = 1; 65 66 /* Set the maxmtu to a default of JUMBO_LEN */ 67 plat->maxmtu = JUMBO_LEN; 68 69 /* Set default number of RX and TX queues to use */ 70 plat->tx_queues_to_use = 1; 71 plat->rx_queues_to_use = 1; 72 73 /* Disable Priority config by default */ 74 plat->tx_queues_cfg[0].use_prio = false; 75 plat->rx_queues_cfg[0].use_prio = false; 76 77 /* Disable RX queues routing by default */ 78 plat->rx_queues_cfg[0].pkt_route = 0x0; 79 } 80 81 static int intel_mgbe_common_data(struct pci_dev *pdev, 82 struct plat_stmmacenet_data *plat) 83 { 84 int i; 85 86 plat->clk_csr = 5; 87 plat->has_gmac = 0; 88 plat->has_gmac4 = 1; 89 plat->force_sf_dma_mode = 0; 90 plat->tso_en = 1; 91 92 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; 93 94 for (i = 0; i < plat->rx_queues_to_use; i++) { 95 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 96 plat->rx_queues_cfg[i].chan = i; 97 98 /* Disable Priority config by default */ 99 plat->rx_queues_cfg[i].use_prio = false; 100 101 /* Disable RX queues routing by default */ 102 plat->rx_queues_cfg[i].pkt_route = 0x0; 103 } 104 105 for (i = 0; i < plat->tx_queues_to_use; i++) { 106 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; 107 108 /* Disable Priority config by default */ 109 plat->tx_queues_cfg[i].use_prio = false; 110 } 111 112 /* FIFO size is 4096 bytes for 1 tx/rx queue */ 113 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; 114 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; 115 116 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; 117 plat->tx_queues_cfg[0].weight = 0x09; 118 plat->tx_queues_cfg[1].weight = 0x0A; 119 plat->tx_queues_cfg[2].weight = 0x0B; 120 plat->tx_queues_cfg[3].weight = 0x0C; 121 plat->tx_queues_cfg[4].weight = 0x0D; 122 plat->tx_queues_cfg[5].weight = 0x0E; 123 plat->tx_queues_cfg[6].weight = 0x0F; 124 plat->tx_queues_cfg[7].weight = 0x10; 125 126 plat->dma_cfg->pbl = 32; 127 plat->dma_cfg->pblx8 = true; 128 plat->dma_cfg->fixed_burst = 0; 129 plat->dma_cfg->mixed_burst = 0; 130 plat->dma_cfg->aal = 0; 131 132 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), 133 GFP_KERNEL); 134 if (!plat->axi) 135 return -ENOMEM; 136 137 plat->axi->axi_lpi_en = 0; 138 plat->axi->axi_xit_frm = 0; 139 plat->axi->axi_wr_osr_lmt = 1; 140 plat->axi->axi_rd_osr_lmt = 1; 141 plat->axi->axi_blen[0] = 4; 142 plat->axi->axi_blen[1] = 8; 143 plat->axi->axi_blen[2] = 16; 144 145 plat->ptp_max_adj = plat->clk_ptp_rate; 146 147 /* Set system clock */ 148 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, 149 "stmmac-clk", NULL, 0, 150 plat->clk_ptp_rate); 151 152 if (IS_ERR(plat->stmmac_clk)) { 153 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); 154 plat->stmmac_clk = NULL; 155 } 156 clk_prepare_enable(plat->stmmac_clk); 157 158 /* Set default value for multicast hash bins */ 159 plat->multicast_filter_bins = HASH_TABLE_SIZE; 160 161 /* Set default value for unicast filter entries */ 162 plat->unicast_filter_entries = 1; 163 164 /* Set the maxmtu to a default of JUMBO_LEN */ 165 plat->maxmtu = JUMBO_LEN; 166 167 return 0; 168 } 169 170 static int ehl_common_data(struct pci_dev *pdev, 171 struct plat_stmmacenet_data *plat) 172 { 173 int ret; 174 175 plat->rx_queues_to_use = 8; 176 plat->tx_queues_to_use = 8; 177 plat->clk_ptp_rate = 200000000; 178 ret = intel_mgbe_common_data(pdev, plat); 179 if (ret) 180 return ret; 181 182 return 0; 183 } 184 185 static int ehl_sgmii_data(struct pci_dev *pdev, 186 struct plat_stmmacenet_data *plat) 187 { 188 plat->bus_id = 1; 189 plat->phy_addr = 0; 190 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 191 192 return ehl_common_data(pdev, plat); 193 } 194 195 static struct stmmac_pci_info ehl_sgmii1g_pci_info = { 196 .setup = ehl_sgmii_data, 197 }; 198 199 static int ehl_rgmii_data(struct pci_dev *pdev, 200 struct plat_stmmacenet_data *plat) 201 { 202 plat->bus_id = 1; 203 plat->phy_addr = 0; 204 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; 205 206 return ehl_common_data(pdev, plat); 207 } 208 209 static struct stmmac_pci_info ehl_rgmii1g_pci_info = { 210 .setup = ehl_rgmii_data, 211 }; 212 213 static int ehl_pse0_common_data(struct pci_dev *pdev, 214 struct plat_stmmacenet_data *plat) 215 { 216 plat->bus_id = 2; 217 plat->phy_addr = 1; 218 return ehl_common_data(pdev, plat); 219 } 220 221 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev, 222 struct plat_stmmacenet_data *plat) 223 { 224 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 225 return ehl_pse0_common_data(pdev, plat); 226 } 227 228 static struct stmmac_pci_info ehl_pse0_rgmii1g_pci_info = { 229 .setup = ehl_pse0_rgmii1g_data, 230 }; 231 232 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev, 233 struct plat_stmmacenet_data *plat) 234 { 235 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 236 return ehl_pse0_common_data(pdev, plat); 237 } 238 239 static struct stmmac_pci_info ehl_pse0_sgmii1g_pci_info = { 240 .setup = ehl_pse0_sgmii1g_data, 241 }; 242 243 static int ehl_pse1_common_data(struct pci_dev *pdev, 244 struct plat_stmmacenet_data *plat) 245 { 246 plat->bus_id = 3; 247 plat->phy_addr = 1; 248 return ehl_common_data(pdev, plat); 249 } 250 251 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev, 252 struct plat_stmmacenet_data *plat) 253 { 254 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; 255 return ehl_pse1_common_data(pdev, plat); 256 } 257 258 static struct stmmac_pci_info ehl_pse1_rgmii1g_pci_info = { 259 .setup = ehl_pse1_rgmii1g_data, 260 }; 261 262 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev, 263 struct plat_stmmacenet_data *plat) 264 { 265 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 266 return ehl_pse1_common_data(pdev, plat); 267 } 268 269 static struct stmmac_pci_info ehl_pse1_sgmii1g_pci_info = { 270 .setup = ehl_pse1_sgmii1g_data, 271 }; 272 273 static int tgl_common_data(struct pci_dev *pdev, 274 struct plat_stmmacenet_data *plat) 275 { 276 int ret; 277 278 plat->rx_queues_to_use = 6; 279 plat->tx_queues_to_use = 4; 280 plat->clk_ptp_rate = 200000000; 281 ret = intel_mgbe_common_data(pdev, plat); 282 if (ret) 283 return ret; 284 285 return 0; 286 } 287 288 static int tgl_sgmii_data(struct pci_dev *pdev, 289 struct plat_stmmacenet_data *plat) 290 { 291 plat->bus_id = 1; 292 plat->phy_addr = 0; 293 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; 294 return tgl_common_data(pdev, plat); 295 } 296 297 static struct stmmac_pci_info tgl_sgmii1g_pci_info = { 298 .setup = tgl_sgmii_data, 299 }; 300 301 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = { 302 { 303 .func = 6, 304 .phy_addr = 1, 305 }, 306 }; 307 308 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = { 309 .func = galileo_stmmac_func_data, 310 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data), 311 }; 312 313 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = { 314 { 315 .func = 6, 316 .phy_addr = 1, 317 }, 318 { 319 .func = 7, 320 .phy_addr = 1, 321 }, 322 }; 323 324 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = { 325 .func = iot2040_stmmac_func_data, 326 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data), 327 }; 328 329 static const struct dmi_system_id quark_pci_dmi[] = { 330 { 331 .matches = { 332 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"), 333 }, 334 .driver_data = (void *)&galileo_stmmac_dmi_data, 335 }, 336 { 337 .matches = { 338 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 339 }, 340 .driver_data = (void *)&galileo_stmmac_dmi_data, 341 }, 342 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040. 343 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which 344 * has only one pci network device while other asset tags are 345 * for IOT2040 which has two. 346 */ 347 { 348 .matches = { 349 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 350 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG, 351 "6ES7647-0AA00-0YA2"), 352 }, 353 .driver_data = (void *)&galileo_stmmac_dmi_data, 354 }, 355 { 356 .matches = { 357 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"), 358 }, 359 .driver_data = (void *)&iot2040_stmmac_dmi_data, 360 }, 361 {} 362 }; 363 364 static int quark_default_data(struct pci_dev *pdev, 365 struct plat_stmmacenet_data *plat) 366 { 367 int ret; 368 369 /* Set common default data first */ 370 common_default_data(plat); 371 372 /* Refuse to load the driver and register net device if MAC controller 373 * does not connect to any PHY interface. 374 */ 375 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi); 376 if (ret < 0) { 377 /* Return error to the caller on DMI enabled boards. */ 378 if (dmi_get_system_info(DMI_BOARD_NAME)) 379 return ret; 380 381 /* Galileo boards with old firmware don't support DMI. We always 382 * use 1 here as PHY address, so at least the first found MAC 383 * controller would be probed. 384 */ 385 ret = 1; 386 } 387 388 plat->bus_id = pci_dev_id(pdev); 389 plat->phy_addr = ret; 390 plat->phy_interface = PHY_INTERFACE_MODE_RMII; 391 392 plat->dma_cfg->pbl = 16; 393 plat->dma_cfg->pblx8 = true; 394 plat->dma_cfg->fixed_burst = 1; 395 /* AXI (TODO) */ 396 397 return 0; 398 } 399 400 static const struct stmmac_pci_info quark_pci_info = { 401 .setup = quark_default_data, 402 }; 403 404 /** 405 * intel_eth_pci_probe 406 * 407 * @pdev: pci device pointer 408 * @id: pointer to table of device id/id's. 409 * 410 * Description: This probing function gets called for all PCI devices which 411 * match the ID table and are not "owned" by other driver yet. This function 412 * gets passed a "struct pci_dev *" for each device whose entry in the ID table 413 * matches the device. The probe functions returns zero when the driver choose 414 * to take "ownership" of the device or an error code(-ve no) otherwise. 415 */ 416 static int intel_eth_pci_probe(struct pci_dev *pdev, 417 const struct pci_device_id *id) 418 { 419 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; 420 struct plat_stmmacenet_data *plat; 421 struct stmmac_resources res; 422 int i; 423 int ret; 424 425 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); 426 if (!plat) 427 return -ENOMEM; 428 429 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, 430 sizeof(*plat->mdio_bus_data), 431 GFP_KERNEL); 432 if (!plat->mdio_bus_data) 433 return -ENOMEM; 434 435 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), 436 GFP_KERNEL); 437 if (!plat->dma_cfg) 438 return -ENOMEM; 439 440 /* Enable pci device */ 441 ret = pci_enable_device(pdev); 442 if (ret) { 443 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", 444 __func__); 445 return ret; 446 } 447 448 /* Get the base address of device */ 449 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 450 if (pci_resource_len(pdev, i) == 0) 451 continue; 452 ret = pcim_iomap_regions(pdev, BIT(i), pci_name(pdev)); 453 if (ret) 454 return ret; 455 break; 456 } 457 458 pci_set_master(pdev); 459 460 ret = info->setup(pdev, plat); 461 if (ret) 462 return ret; 463 464 pci_enable_msi(pdev); 465 466 memset(&res, 0, sizeof(res)); 467 res.addr = pcim_iomap_table(pdev)[i]; 468 res.wol_irq = pdev->irq; 469 res.irq = pdev->irq; 470 471 return stmmac_dvr_probe(&pdev->dev, plat, &res); 472 } 473 474 /** 475 * intel_eth_pci_remove 476 * 477 * @pdev: platform device pointer 478 * Description: this function calls the main to free the net resources 479 * and releases the PCI resources. 480 */ 481 static void intel_eth_pci_remove(struct pci_dev *pdev) 482 { 483 struct net_device *ndev = dev_get_drvdata(&pdev->dev); 484 struct stmmac_priv *priv = netdev_priv(ndev); 485 int i; 486 487 stmmac_dvr_remove(&pdev->dev); 488 489 if (priv->plat->stmmac_clk) 490 clk_unregister_fixed_rate(priv->plat->stmmac_clk); 491 492 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 493 if (pci_resource_len(pdev, i) == 0) 494 continue; 495 pcim_iounmap_regions(pdev, BIT(i)); 496 break; 497 } 498 499 pci_disable_device(pdev); 500 } 501 502 static int __maybe_unused intel_eth_pci_suspend(struct device *dev) 503 { 504 struct pci_dev *pdev = to_pci_dev(dev); 505 int ret; 506 507 ret = stmmac_suspend(dev); 508 if (ret) 509 return ret; 510 511 ret = pci_save_state(pdev); 512 if (ret) 513 return ret; 514 515 pci_disable_device(pdev); 516 pci_wake_from_d3(pdev, true); 517 return 0; 518 } 519 520 static int __maybe_unused intel_eth_pci_resume(struct device *dev) 521 { 522 struct pci_dev *pdev = to_pci_dev(dev); 523 int ret; 524 525 pci_restore_state(pdev); 526 pci_set_power_state(pdev, PCI_D0); 527 528 ret = pci_enable_device(pdev); 529 if (ret) 530 return ret; 531 532 pci_set_master(pdev); 533 534 return stmmac_resume(dev); 535 } 536 537 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend, 538 intel_eth_pci_resume); 539 540 #define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937 541 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30 542 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31 543 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5_ID 0x4b32 544 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC 545 * which are named PSE0 and PSE1 546 */ 547 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0 548 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1 549 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5_ID 0x4ba2 550 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0 551 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1 552 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5_ID 0x4bb2 553 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac 554 555 static const struct pci_device_id intel_eth_pci_id_table[] = { 556 { PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) }, 557 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) }, 558 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) }, 559 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5_ID, &ehl_sgmii1g_pci_info) }, 560 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID, 561 &ehl_pse0_rgmii1g_pci_info) }, 562 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID, 563 &ehl_pse0_sgmii1g_pci_info) }, 564 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5_ID, 565 &ehl_pse0_sgmii1g_pci_info) }, 566 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID, 567 &ehl_pse1_rgmii1g_pci_info) }, 568 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID, 569 &ehl_pse1_sgmii1g_pci_info) }, 570 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5_ID, 571 &ehl_pse1_sgmii1g_pci_info) }, 572 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) }, 573 {} 574 }; 575 576 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table); 577 578 static struct pci_driver intel_eth_pci_driver = { 579 .name = "intel-eth-pci", 580 .id_table = intel_eth_pci_id_table, 581 .probe = intel_eth_pci_probe, 582 .remove = intel_eth_pci_remove, 583 .driver = { 584 .pm = &intel_eth_pm_ops, 585 }, 586 }; 587 588 module_pci_driver(intel_eth_pci_driver); 589 590 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver"); 591 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>"); 592 MODULE_LICENSE("GPL v2"); 593