1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Synopsys DesignWare 8250 driver. 4 * 5 * Copyright 2011 Picochip, Jamie Iles. 6 * Copyright 2013 Intel Corporation 7 * 8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 */ 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 #include <linux/acpi.h> 24 #include <linux/clk.h> 25 #include <linux/reset.h> 26 #include <linux/pm_runtime.h> 27 28 #include <asm/byteorder.h> 29 30 #include "8250_dwlib.h" 31 32 /* Offsets for the DesignWare specific registers */ 33 #define DW_UART_USR 0x1f /* UART Status Register */ 34 35 /* DesignWare specific register fields */ 36 #define DW_UART_MCR_SIRE BIT(6) 37 38 struct dw8250_data { 39 struct dw8250_port_data data; 40 41 u8 usr_reg; 42 int msr_mask_on; 43 int msr_mask_off; 44 struct clk *clk; 45 struct clk *pclk; 46 struct reset_control *rst; 47 48 unsigned int skip_autocfg:1; 49 unsigned int uart_16550_compatible:1; 50 }; 51 52 static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data) 53 { 54 return container_of(data, struct dw8250_data, data); 55 } 56 57 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 58 { 59 struct dw8250_data *d = to_dw8250_data(p->private_data); 60 61 /* Override any modem control signals if needed */ 62 if (offset == UART_MSR) { 63 value |= d->msr_mask_on; 64 value &= ~d->msr_mask_off; 65 } 66 67 return value; 68 } 69 70 static void dw8250_force_idle(struct uart_port *p) 71 { 72 struct uart_8250_port *up = up_to_u8250p(p); 73 74 serial8250_clear_and_reinit_fifos(up); 75 (void)p->serial_in(p, UART_RX); 76 } 77 78 static void dw8250_check_lcr(struct uart_port *p, int value) 79 { 80 void __iomem *offset = p->membase + (UART_LCR << p->regshift); 81 int tries = 1000; 82 83 /* Make sure LCR write wasn't ignored */ 84 while (tries--) { 85 unsigned int lcr = p->serial_in(p, UART_LCR); 86 87 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 88 return; 89 90 dw8250_force_idle(p); 91 92 #ifdef CONFIG_64BIT 93 if (p->type == PORT_OCTEON) 94 __raw_writeq(value & 0xff, offset); 95 else 96 #endif 97 if (p->iotype == UPIO_MEM32) 98 writel(value, offset); 99 else if (p->iotype == UPIO_MEM32BE) 100 iowrite32be(value, offset); 101 else 102 writeb(value, offset); 103 } 104 /* 105 * FIXME: this deadlocks if port->lock is already held 106 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 107 */ 108 } 109 110 /* Returns once the transmitter is empty or we run out of retries */ 111 static void dw8250_tx_wait_empty(struct uart_port *p) 112 { 113 unsigned int tries = 20000; 114 unsigned int delay_threshold = tries - 1000; 115 unsigned int lsr; 116 117 while (tries--) { 118 lsr = readb (p->membase + (UART_LSR << p->regshift)); 119 if (lsr & UART_LSR_TEMT) 120 break; 121 122 /* The device is first given a chance to empty without delay, 123 * to avoid slowdowns at high bitrates. If after 1000 tries 124 * the buffer has still not emptied, allow more time for low- 125 * speed links. */ 126 if (tries < delay_threshold) 127 udelay (1); 128 } 129 } 130 131 static void dw8250_serial_out38x(struct uart_port *p, int offset, int value) 132 { 133 struct dw8250_data *d = to_dw8250_data(p->private_data); 134 135 /* Allow the TX to drain before we reconfigure */ 136 if (offset == UART_LCR) 137 dw8250_tx_wait_empty(p); 138 139 writeb(value, p->membase + (offset << p->regshift)); 140 141 if (offset == UART_LCR && !d->uart_16550_compatible) 142 dw8250_check_lcr(p, value); 143 } 144 145 146 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 147 { 148 struct dw8250_data *d = to_dw8250_data(p->private_data); 149 150 writeb(value, p->membase + (offset << p->regshift)); 151 152 if (offset == UART_LCR && !d->uart_16550_compatible) 153 dw8250_check_lcr(p, value); 154 } 155 156 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 157 { 158 unsigned int value = readb(p->membase + (offset << p->regshift)); 159 160 return dw8250_modify_msr(p, offset, value); 161 } 162 163 #ifdef CONFIG_64BIT 164 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 165 { 166 unsigned int value; 167 168 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 169 170 return dw8250_modify_msr(p, offset, value); 171 } 172 173 static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 174 { 175 struct dw8250_data *d = to_dw8250_data(p->private_data); 176 177 value &= 0xff; 178 __raw_writeq(value, p->membase + (offset << p->regshift)); 179 /* Read back to ensure register write ordering. */ 180 __raw_readq(p->membase + (UART_LCR << p->regshift)); 181 182 if (offset == UART_LCR && !d->uart_16550_compatible) 183 dw8250_check_lcr(p, value); 184 } 185 #endif /* CONFIG_64BIT */ 186 187 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 188 { 189 struct dw8250_data *d = to_dw8250_data(p->private_data); 190 191 writel(value, p->membase + (offset << p->regshift)); 192 193 if (offset == UART_LCR && !d->uart_16550_compatible) 194 dw8250_check_lcr(p, value); 195 } 196 197 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 198 { 199 unsigned int value = readl(p->membase + (offset << p->regshift)); 200 201 return dw8250_modify_msr(p, offset, value); 202 } 203 204 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) 205 { 206 struct dw8250_data *d = to_dw8250_data(p->private_data); 207 208 iowrite32be(value, p->membase + (offset << p->regshift)); 209 210 if (offset == UART_LCR && !d->uart_16550_compatible) 211 dw8250_check_lcr(p, value); 212 } 213 214 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) 215 { 216 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); 217 218 return dw8250_modify_msr(p, offset, value); 219 } 220 221 222 static int dw8250_handle_irq(struct uart_port *p) 223 { 224 struct uart_8250_port *up = up_to_u8250p(p); 225 struct dw8250_data *d = to_dw8250_data(p->private_data); 226 unsigned int iir = p->serial_in(p, UART_IIR); 227 unsigned int status; 228 unsigned long flags; 229 230 /* 231 * There are ways to get Designware-based UARTs into a state where 232 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual 233 * data available. If we see such a case then we'll do a bogus 234 * read. If we don't do this then the "RX TIMEOUT" interrupt will 235 * fire forever. 236 * 237 * This problem has only been observed so far when not in DMA mode 238 * so we limit the workaround only to non-DMA mode. 239 */ 240 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { 241 spin_lock_irqsave(&p->lock, flags); 242 status = p->serial_in(p, UART_LSR); 243 244 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 245 (void) p->serial_in(p, UART_RX); 246 247 spin_unlock_irqrestore(&p->lock, flags); 248 } 249 250 if (serial8250_handle_irq(p, iir)) 251 return 1; 252 253 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 254 /* Clear the USR */ 255 (void)p->serial_in(p, d->usr_reg); 256 257 return 1; 258 } 259 260 return 0; 261 } 262 263 static void 264 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 265 { 266 if (!state) 267 pm_runtime_get_sync(port->dev); 268 269 serial8250_do_pm(port, state, old); 270 271 if (state) 272 pm_runtime_put_sync_suspend(port->dev); 273 } 274 275 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 276 struct ktermios *old) 277 { 278 unsigned int baud = tty_termios_baud_rate(termios); 279 struct dw8250_data *d = to_dw8250_data(p->private_data); 280 long rate; 281 int ret; 282 283 clk_disable_unprepare(d->clk); 284 rate = clk_round_rate(d->clk, baud * 16); 285 if (rate < 0) 286 ret = rate; 287 else if (rate == 0) 288 ret = -ENOENT; 289 else 290 ret = clk_set_rate(d->clk, rate); 291 clk_prepare_enable(d->clk); 292 293 if (ret) 294 goto out; 295 296 p->uartclk = rate; 297 298 out: 299 p->status &= ~UPSTAT_AUTOCTS; 300 if (termios->c_cflag & CRTSCTS) 301 p->status |= UPSTAT_AUTOCTS; 302 303 serial8250_do_set_termios(p, termios, old); 304 } 305 306 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 307 { 308 struct uart_8250_port *up = up_to_u8250p(p); 309 unsigned int mcr = p->serial_in(p, UART_MCR); 310 311 if (up->capabilities & UART_CAP_IRDA) { 312 if (termios->c_line == N_IRDA) 313 mcr |= DW_UART_MCR_SIRE; 314 else 315 mcr &= ~DW_UART_MCR_SIRE; 316 317 p->serial_out(p, UART_MCR, mcr); 318 } 319 serial8250_do_set_ldisc(p, termios); 320 } 321 322 /* 323 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 324 * channel on platforms that have DMA engines, but don't have any channels 325 * assigned to the UART. 326 * 327 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 328 * core problem is fixed, this function is no longer needed. 329 */ 330 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 331 { 332 return false; 333 } 334 335 static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 336 { 337 return param == chan->device->dev; 338 } 339 340 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 341 { 342 if (p->dev->of_node) { 343 struct device_node *np = p->dev->of_node; 344 int id; 345 346 /* get index of serial line, if found in DT aliases */ 347 id = of_alias_get_id(np, "serial"); 348 if (id >= 0) 349 p->line = id; 350 #ifdef CONFIG_64BIT 351 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 352 p->serial_in = dw8250_serial_inq; 353 p->serial_out = dw8250_serial_outq; 354 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 355 p->type = PORT_OCTEON; 356 data->usr_reg = 0x27; 357 data->skip_autocfg = true; 358 } 359 #endif 360 if (of_device_is_big_endian(p->dev->of_node)) { 361 p->iotype = UPIO_MEM32BE; 362 p->serial_in = dw8250_serial_in32be; 363 p->serial_out = dw8250_serial_out32be; 364 } 365 if (of_device_is_compatible(np, "marvell,armada-38x-uart")) 366 p->serial_out = dw8250_serial_out38x; 367 368 } else if (acpi_dev_present("APMC0D08", NULL, -1)) { 369 p->iotype = UPIO_MEM32; 370 p->regshift = 2; 371 p->serial_in = dw8250_serial_in32; 372 data->uart_16550_compatible = true; 373 } 374 375 /* Platforms with iDMA 64-bit */ 376 if (platform_get_resource_byname(to_platform_device(p->dev), 377 IORESOURCE_MEM, "lpss_priv")) { 378 data->data.dma.rx_param = p->dev->parent; 379 data->data.dma.tx_param = p->dev->parent; 380 data->data.dma.fn = dw8250_idma_filter; 381 } 382 } 383 384 static int dw8250_probe(struct platform_device *pdev) 385 { 386 struct uart_8250_port uart = {}, *up = &uart; 387 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 388 struct uart_port *p = &up->port; 389 struct device *dev = &pdev->dev; 390 struct dw8250_data *data; 391 int irq; 392 int err; 393 u32 val; 394 395 if (!regs) { 396 dev_err(dev, "no registers defined\n"); 397 return -EINVAL; 398 } 399 400 irq = platform_get_irq(pdev, 0); 401 if (irq < 0) 402 return irq; 403 404 spin_lock_init(&p->lock); 405 p->mapbase = regs->start; 406 p->irq = irq; 407 p->handle_irq = dw8250_handle_irq; 408 p->pm = dw8250_do_pm; 409 p->type = PORT_8250; 410 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 411 p->dev = dev; 412 p->iotype = UPIO_MEM; 413 p->serial_in = dw8250_serial_in; 414 p->serial_out = dw8250_serial_out; 415 p->set_ldisc = dw8250_set_ldisc; 416 p->set_termios = dw8250_set_termios; 417 418 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); 419 if (!p->membase) 420 return -ENOMEM; 421 422 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 423 if (!data) 424 return -ENOMEM; 425 426 data->data.dma.fn = dw8250_fallback_dma_filter; 427 data->usr_reg = DW_UART_USR; 428 p->private_data = &data->data; 429 430 data->uart_16550_compatible = device_property_read_bool(dev, 431 "snps,uart-16550-compatible"); 432 433 err = device_property_read_u32(dev, "reg-shift", &val); 434 if (!err) 435 p->regshift = val; 436 437 err = device_property_read_u32(dev, "reg-io-width", &val); 438 if (!err && val == 4) { 439 p->iotype = UPIO_MEM32; 440 p->serial_in = dw8250_serial_in32; 441 p->serial_out = dw8250_serial_out32; 442 } 443 444 if (device_property_read_bool(dev, "dcd-override")) { 445 /* Always report DCD as active */ 446 data->msr_mask_on |= UART_MSR_DCD; 447 data->msr_mask_off |= UART_MSR_DDCD; 448 } 449 450 if (device_property_read_bool(dev, "dsr-override")) { 451 /* Always report DSR as active */ 452 data->msr_mask_on |= UART_MSR_DSR; 453 data->msr_mask_off |= UART_MSR_DDSR; 454 } 455 456 if (device_property_read_bool(dev, "cts-override")) { 457 /* Always report CTS as active */ 458 data->msr_mask_on |= UART_MSR_CTS; 459 data->msr_mask_off |= UART_MSR_DCTS; 460 } 461 462 if (device_property_read_bool(dev, "ri-override")) { 463 /* Always report Ring indicator as inactive */ 464 data->msr_mask_off |= UART_MSR_RI; 465 data->msr_mask_off |= UART_MSR_TERI; 466 } 467 468 /* Always ask for fixed clock rate from a property. */ 469 device_property_read_u32(dev, "clock-frequency", &p->uartclk); 470 471 /* If there is separate baudclk, get the rate from it. */ 472 data->clk = devm_clk_get_optional(dev, "baudclk"); 473 if (data->clk == NULL) 474 data->clk = devm_clk_get_optional(dev, NULL); 475 if (IS_ERR(data->clk)) 476 return PTR_ERR(data->clk); 477 478 err = clk_prepare_enable(data->clk); 479 if (err) 480 dev_warn(dev, "could not enable optional baudclk: %d\n", err); 481 482 if (data->clk) 483 p->uartclk = clk_get_rate(data->clk); 484 485 /* If no clock rate is defined, fail. */ 486 if (!p->uartclk) { 487 dev_err(dev, "clock rate not defined\n"); 488 err = -EINVAL; 489 goto err_clk; 490 } 491 492 data->pclk = devm_clk_get_optional(dev, "apb_pclk"); 493 if (IS_ERR(data->pclk)) { 494 err = PTR_ERR(data->pclk); 495 goto err_clk; 496 } 497 498 err = clk_prepare_enable(data->pclk); 499 if (err) { 500 dev_err(dev, "could not enable apb_pclk\n"); 501 goto err_clk; 502 } 503 504 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); 505 if (IS_ERR(data->rst)) { 506 err = PTR_ERR(data->rst); 507 goto err_pclk; 508 } 509 reset_control_deassert(data->rst); 510 511 dw8250_quirks(p, data); 512 513 /* If the Busy Functionality is not implemented, don't handle it */ 514 if (data->uart_16550_compatible) 515 p->handle_irq = NULL; 516 517 if (!data->skip_autocfg) 518 dw8250_setup_port(p); 519 520 /* If we have a valid fifosize, try hooking up DMA */ 521 if (p->fifosize) { 522 data->data.dma.rxconf.src_maxburst = p->fifosize / 4; 523 data->data.dma.txconf.dst_maxburst = p->fifosize / 4; 524 up->dma = &data->data.dma; 525 } 526 527 data->data.line = serial8250_register_8250_port(up); 528 if (data->data.line < 0) { 529 err = data->data.line; 530 goto err_reset; 531 } 532 533 platform_set_drvdata(pdev, data); 534 535 pm_runtime_set_active(dev); 536 pm_runtime_enable(dev); 537 538 return 0; 539 540 err_reset: 541 reset_control_assert(data->rst); 542 543 err_pclk: 544 clk_disable_unprepare(data->pclk); 545 546 err_clk: 547 clk_disable_unprepare(data->clk); 548 549 return err; 550 } 551 552 static int dw8250_remove(struct platform_device *pdev) 553 { 554 struct dw8250_data *data = platform_get_drvdata(pdev); 555 struct device *dev = &pdev->dev; 556 557 pm_runtime_get_sync(dev); 558 559 serial8250_unregister_port(data->data.line); 560 561 reset_control_assert(data->rst); 562 563 clk_disable_unprepare(data->pclk); 564 565 clk_disable_unprepare(data->clk); 566 567 pm_runtime_disable(dev); 568 pm_runtime_put_noidle(dev); 569 570 return 0; 571 } 572 573 #ifdef CONFIG_PM_SLEEP 574 static int dw8250_suspend(struct device *dev) 575 { 576 struct dw8250_data *data = dev_get_drvdata(dev); 577 578 serial8250_suspend_port(data->data.line); 579 580 return 0; 581 } 582 583 static int dw8250_resume(struct device *dev) 584 { 585 struct dw8250_data *data = dev_get_drvdata(dev); 586 587 serial8250_resume_port(data->data.line); 588 589 return 0; 590 } 591 #endif /* CONFIG_PM_SLEEP */ 592 593 #ifdef CONFIG_PM 594 static int dw8250_runtime_suspend(struct device *dev) 595 { 596 struct dw8250_data *data = dev_get_drvdata(dev); 597 598 clk_disable_unprepare(data->clk); 599 600 clk_disable_unprepare(data->pclk); 601 602 return 0; 603 } 604 605 static int dw8250_runtime_resume(struct device *dev) 606 { 607 struct dw8250_data *data = dev_get_drvdata(dev); 608 609 clk_prepare_enable(data->pclk); 610 611 clk_prepare_enable(data->clk); 612 613 return 0; 614 } 615 #endif 616 617 static const struct dev_pm_ops dw8250_pm_ops = { 618 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 619 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 620 }; 621 622 static const struct of_device_id dw8250_of_match[] = { 623 { .compatible = "snps,dw-apb-uart" }, 624 { .compatible = "cavium,octeon-3860-uart" }, 625 { .compatible = "marvell,armada-38x-uart" }, 626 { .compatible = "renesas,rzn1-uart" }, 627 { /* Sentinel */ } 628 }; 629 MODULE_DEVICE_TABLE(of, dw8250_of_match); 630 631 static const struct acpi_device_id dw8250_acpi_match[] = { 632 { "INT33C4", 0 }, 633 { "INT33C5", 0 }, 634 { "INT3434", 0 }, 635 { "INT3435", 0 }, 636 { "80860F0A", 0 }, 637 { "8086228A", 0 }, 638 { "APMC0D08", 0}, 639 { "AMD0020", 0 }, 640 { "AMDI0020", 0 }, 641 { "BRCM2032", 0 }, 642 { "HISI0031", 0 }, 643 { }, 644 }; 645 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 646 647 static struct platform_driver dw8250_platform_driver = { 648 .driver = { 649 .name = "dw-apb-uart", 650 .pm = &dw8250_pm_ops, 651 .of_match_table = dw8250_of_match, 652 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 653 }, 654 .probe = dw8250_probe, 655 .remove = dw8250_remove, 656 }; 657 658 module_platform_driver(dw8250_platform_driver); 659 660 MODULE_AUTHOR("Jamie Iles"); 661 MODULE_LICENSE("GPL"); 662 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 663 MODULE_ALIAS("platform:dw-apb-uart"); 664