1# SPDX-License-Identifier: (GPL-2.0 OR MIT)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/riscv/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: RISC-V bindings for 'cpus' DT nodes
8
9maintainers:
10  - Paul Walmsley <paul.walmsley@sifive.com>
11  - Palmer Dabbelt <palmer@sifive.com>
12
13description: |
14  This document uses some terminology common to the RISC-V community
15  that is not widely used, the definitions of which are listed here:
16
17  hart: A hardware execution context, which contains all the state
18  mandated by the RISC-V ISA: a PC and some registers.  This
19  terminology is designed to disambiguate software's view of execution
20  contexts from any particular microarchitectural implementation
21  strategy.  For example, an Intel laptop containing one socket with
22  two cores, each of which has two hyperthreads, could be described as
23  having four harts.
24
25properties:
26  compatible:
27    oneOf:
28      - items:
29          - enum:
30              - sifive,rocket0
31              - sifive,e5
32              - sifive,e51
33              - sifive,u54-mc
34              - sifive,u54
35              - sifive,u5
36          - const: riscv
37      - const: riscv    # Simulator only
38    description:
39      Identifies that the hart uses the RISC-V instruction set
40      and identifies the type of the hart.
41
42  mmu-type:
43    description:
44      Identifies the MMU address translation mode used on this
45      hart.  These values originate from the RISC-V Privileged
46      Specification document, available from
47      https://riscv.org/specifications/
48    $ref: "/schemas/types.yaml#/definitions/string"
49    enum:
50      - riscv,sv32
51      - riscv,sv39
52      - riscv,sv48
53
54  riscv,isa:
55    description:
56      Identifies the specific RISC-V instruction set architecture
57      supported by the hart.  These are documented in the RISC-V
58      User-Level ISA document, available from
59      https://riscv.org/specifications/
60
61      While the isa strings in ISA specification are case
62      insensitive, letters in the riscv,isa string must be all
63      lowercase to simplify parsing.
64    $ref: "/schemas/types.yaml#/definitions/string"
65    enum:
66      - rv64imac
67      - rv64imafdc
68
69  # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
70  timebase-frequency: false
71
72  interrupt-controller:
73    type: object
74    description: Describes the CPU's local interrupt controller
75
76    properties:
77      '#interrupt-cells':
78        const: 1
79
80      compatible:
81        const: riscv,cpu-intc
82
83      interrupt-controller: true
84
85    required:
86      - '#interrupt-cells'
87      - compatible
88      - interrupt-controller
89
90required:
91  - riscv,isa
92  - interrupt-controller
93
94examples:
95  - |
96    // Example 1: SiFive Freedom U540G Development Kit
97    cpus {
98        #address-cells = <1>;
99        #size-cells = <0>;
100        timebase-frequency = <1000000>;
101        cpu@0 {
102                clock-frequency = <0>;
103                compatible = "sifive,rocket0", "riscv";
104                device_type = "cpu";
105                i-cache-block-size = <64>;
106                i-cache-sets = <128>;
107                i-cache-size = <16384>;
108                reg = <0>;
109                riscv,isa = "rv64imac";
110                cpu_intc0: interrupt-controller {
111                        #interrupt-cells = <1>;
112                        compatible = "riscv,cpu-intc";
113                        interrupt-controller;
114                };
115        };
116        cpu@1 {
117                clock-frequency = <0>;
118                compatible = "sifive,rocket0", "riscv";
119                d-cache-block-size = <64>;
120                d-cache-sets = <64>;
121                d-cache-size = <32768>;
122                d-tlb-sets = <1>;
123                d-tlb-size = <32>;
124                device_type = "cpu";
125                i-cache-block-size = <64>;
126                i-cache-sets = <64>;
127                i-cache-size = <32768>;
128                i-tlb-sets = <1>;
129                i-tlb-size = <32>;
130                mmu-type = "riscv,sv39";
131                reg = <1>;
132                riscv,isa = "rv64imafdc";
133                tlb-split;
134                cpu_intc1: interrupt-controller {
135                        #interrupt-cells = <1>;
136                        compatible = "riscv,cpu-intc";
137                        interrupt-controller;
138                };
139        };
140    };
141
142  - |
143    // Example 2: Spike ISA Simulator with 1 Hart
144    cpus {
145        #address-cells = <1>;
146        #size-cells = <0>;
147        cpu@0 {
148                device_type = "cpu";
149                reg = <0>;
150                compatible = "riscv";
151                riscv,isa = "rv64imafdc";
152                mmu-type = "riscv,sv48";
153                interrupt-controller {
154                        #interrupt-cells = <1>;
155                        interrupt-controller;
156                        compatible = "riscv,cpu-intc";
157                };
158        };
159    };
160...
161