1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2016 Freescale Semiconductor, Inc. 4 * Copyright 2017-2018 NXP 5 * Dong Aisheng <aisheng.dong@nxp.com> 6 */ 7 8#include <dt-bindings/clock/imx8-clock.h> 9#include <dt-bindings/firmware/imx/rsrc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/pinctrl/pads-imx8qxp.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &lsio_gpio0; 23 gpio1 = &lsio_gpio1; 24 gpio2 = &lsio_gpio2; 25 gpio3 = &lsio_gpio3; 26 gpio4 = &lsio_gpio4; 27 gpio5 = &lsio_gpio5; 28 gpio6 = &lsio_gpio6; 29 gpio7 = &lsio_gpio7; 30 mmc0 = &usdhc1; 31 mmc1 = &usdhc2; 32 mmc2 = &usdhc3; 33 mu1 = &lsio_mu1; 34 serial0 = &adma_lpuart0; 35 serial1 = &adma_lpuart1; 36 serial2 = &adma_lpuart2; 37 serial3 = &adma_lpuart3; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 /* We have 1 clusters with 4 Cortex-A35 cores */ 45 A35_0: cpu@0 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a35"; 48 reg = <0x0 0x0>; 49 enable-method = "psci"; 50 next-level-cache = <&A35_L2>; 51 clocks = <&clk IMX_A35_CLK>; 52 operating-points-v2 = <&a35_opp_table>; 53 #cooling-cells = <2>; 54 }; 55 56 A35_1: cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a35"; 59 reg = <0x0 0x1>; 60 enable-method = "psci"; 61 next-level-cache = <&A35_L2>; 62 clocks = <&clk IMX_A35_CLK>; 63 operating-points-v2 = <&a35_opp_table>; 64 #cooling-cells = <2>; 65 }; 66 67 A35_2: cpu@2 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a35"; 70 reg = <0x0 0x2>; 71 enable-method = "psci"; 72 next-level-cache = <&A35_L2>; 73 clocks = <&clk IMX_A35_CLK>; 74 operating-points-v2 = <&a35_opp_table>; 75 #cooling-cells = <2>; 76 }; 77 78 A35_3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a35"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 next-level-cache = <&A35_L2>; 84 clocks = <&clk IMX_A35_CLK>; 85 operating-points-v2 = <&a35_opp_table>; 86 #cooling-cells = <2>; 87 }; 88 89 A35_L2: l2-cache0 { 90 compatible = "cache"; 91 }; 92 }; 93 94 a35_opp_table: opp-table { 95 compatible = "operating-points-v2"; 96 opp-shared; 97 98 opp-900000000 { 99 opp-hz = /bits/ 64 <900000000>; 100 opp-microvolt = <1000000>; 101 clock-latency-ns = <150000>; 102 }; 103 104 opp-1200000000 { 105 opp-hz = /bits/ 64 <1200000000>; 106 opp-microvolt = <1100000>; 107 clock-latency-ns = <150000>; 108 opp-suspend; 109 }; 110 }; 111 112 gic: interrupt-controller@51a00000 { 113 compatible = "arm,gic-v3"; 114 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ 115 <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ 116 #interrupt-cells = <3>; 117 interrupt-controller; 118 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 119 }; 120 121 reserved-memory { 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges; 125 126 dsp_reserved: dsp@92400000 { 127 reg = <0 0x92400000 0 0x2000000>; 128 no-map; 129 }; 130 }; 131 132 pmu { 133 compatible = "arm,armv8-pmuv3"; 134 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 135 }; 136 137 psci { 138 compatible = "arm,psci-1.0"; 139 method = "smc"; 140 }; 141 142 scu { 143 compatible = "fsl,imx-scu"; 144 mbox-names = "tx0", "tx1", "tx2", "tx3", 145 "rx0", "rx1", "rx2", "rx3", 146 "gip3"; 147 mboxes = <&lsio_mu1 0 0 148 &lsio_mu1 0 1 149 &lsio_mu1 0 2 150 &lsio_mu1 0 3 151 &lsio_mu1 1 0 152 &lsio_mu1 1 1 153 &lsio_mu1 1 2 154 &lsio_mu1 1 3 155 &lsio_mu1 3 3>; 156 157 clk: clock-controller { 158 compatible = "fsl,imx8qxp-clk"; 159 #clock-cells = <1>; 160 clocks = <&xtal32k &xtal24m>; 161 clock-names = "xtal_32KHz", "xtal_24Mhz"; 162 }; 163 164 iomuxc: pinctrl { 165 compatible = "fsl,imx8qxp-iomuxc"; 166 }; 167 168 ocotp: imx8qx-ocotp { 169 compatible = "fsl,imx8qxp-scu-ocotp"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 }; 173 174 pd: imx8qx-pd { 175 compatible = "fsl,imx8qxp-scu-pd"; 176 #power-domain-cells = <1>; 177 }; 178 179 scu_key: scu-key { 180 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 181 linux,keycodes = <KEY_POWER>; 182 status = "disabled"; 183 }; 184 185 rtc: rtc { 186 compatible = "fsl,imx8qxp-sc-rtc"; 187 }; 188 189 watchdog { 190 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 191 timeout-sec = <60>; 192 }; 193 194 tsens: thermal-sensor { 195 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 196 #thermal-sensor-cells = <1>; 197 }; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 203 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 204 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 205 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 206 }; 207 208 xtal32k: clock-xtal32k { 209 compatible = "fixed-clock"; 210 #clock-cells = <0>; 211 clock-frequency = <32768>; 212 clock-output-names = "xtal_32KHz"; 213 }; 214 215 xtal24m: clock-xtal24m { 216 compatible = "fixed-clock"; 217 #clock-cells = <0>; 218 clock-frequency = <24000000>; 219 clock-output-names = "xtal_24MHz"; 220 }; 221 222 adma_subsys: bus@59000000 { 223 compatible = "simple-bus"; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 ranges = <0x59000000 0x0 0x59000000 0x2000000>; 227 228 adma_lpcg: clock-controller@59000000 { 229 compatible = "fsl,imx8qxp-lpcg-adma"; 230 reg = <0x59000000 0x2000000>; 231 #clock-cells = <1>; 232 }; 233 234 adma_dsp: dsp@596e8000 { 235 compatible = "fsl,imx8qxp-dsp"; 236 reg = <0x596e8000 0x88000>; 237 clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, 238 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, 239 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; 240 clock-names = "ipg", "ocram", "core"; 241 power-domains = <&pd IMX_SC_R_MU_13A>, 242 <&pd IMX_SC_R_MU_13B>, 243 <&pd IMX_SC_R_DSP>, 244 <&pd IMX_SC_R_DSP_RAM>; 245 mbox-names = "txdb0", "txdb1", 246 "rxdb0", "rxdb1"; 247 mboxes = <&lsio_mu13 2 0>, 248 <&lsio_mu13 2 1>, 249 <&lsio_mu13 3 0>, 250 <&lsio_mu13 3 1>; 251 memory-region = <&dsp_reserved>; 252 status = "disabled"; 253 }; 254 255 adma_lpuart0: serial@5a060000 { 256 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 257 reg = <0x5a060000 0x1000>; 258 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>, 260 <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>; 261 clock-names = "ipg", "baud"; 262 power-domains = <&pd IMX_SC_R_UART_0>; 263 status = "disabled"; 264 }; 265 266 adma_lpuart1: serial@5a070000 { 267 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 268 reg = <0x5a070000 0x1000>; 269 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 270 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>, 271 <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>; 272 clock-names = "ipg", "baud"; 273 power-domains = <&pd IMX_SC_R_UART_1>; 274 status = "disabled"; 275 }; 276 277 adma_lpuart2: serial@5a080000 { 278 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 279 reg = <0x5a080000 0x1000>; 280 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 281 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>, 282 <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>; 283 clock-names = "ipg", "baud"; 284 power-domains = <&pd IMX_SC_R_UART_2>; 285 status = "disabled"; 286 }; 287 288 adma_lpuart3: serial@5a090000 { 289 compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; 290 reg = <0x5a090000 0x1000>; 291 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 292 clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>, 293 <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>; 294 clock-names = "ipg", "baud"; 295 power-domains = <&pd IMX_SC_R_UART_3>; 296 status = "disabled"; 297 }; 298 299 adma_i2c0: i2c@5a800000 { 300 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 301 reg = <0x5a800000 0x4000>; 302 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; 304 clock-names = "per"; 305 assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; 306 assigned-clock-rates = <24000000>; 307 power-domains = <&pd IMX_SC_R_I2C_0>; 308 status = "disabled"; 309 }; 310 311 adma_i2c1: i2c@5a810000 { 312 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 313 reg = <0x5a810000 0x4000>; 314 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; 316 clock-names = "per"; 317 assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; 318 assigned-clock-rates = <24000000>; 319 power-domains = <&pd IMX_SC_R_I2C_1>; 320 status = "disabled"; 321 }; 322 323 adma_i2c2: i2c@5a820000 { 324 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 325 reg = <0x5a820000 0x4000>; 326 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; 328 clock-names = "per"; 329 assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; 330 assigned-clock-rates = <24000000>; 331 power-domains = <&pd IMX_SC_R_I2C_2>; 332 status = "disabled"; 333 }; 334 335 adma_i2c3: i2c@5a830000 { 336 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 337 reg = <0x5a830000 0x4000>; 338 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; 340 clock-names = "per"; 341 assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; 342 assigned-clock-rates = <24000000>; 343 power-domains = <&pd IMX_SC_R_I2C_3>; 344 status = "disabled"; 345 }; 346 }; 347 348 conn_subsys: bus@5b000000 { 349 compatible = "simple-bus"; 350 #address-cells = <1>; 351 #size-cells = <1>; 352 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; 353 354 conn_lpcg: clock-controller@5b200000 { 355 compatible = "fsl,imx8qxp-lpcg-conn"; 356 reg = <0x5b200000 0xb0000>; 357 #clock-cells = <1>; 358 }; 359 360 usdhc1: mmc@5b010000 { 361 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 362 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 363 reg = <0x5b010000 0x10000>; 364 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>, 365 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>, 366 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>; 367 clock-names = "ipg", "per", "ahb"; 368 power-domains = <&pd IMX_SC_R_SDHC_0>; 369 status = "disabled"; 370 }; 371 372 usdhc2: mmc@5b020000 { 373 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 374 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 375 reg = <0x5b020000 0x10000>; 376 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>, 377 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>, 378 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>; 379 clock-names = "ipg", "per", "ahb"; 380 power-domains = <&pd IMX_SC_R_SDHC_1>; 381 fsl,tuning-start-tap = <20>; 382 fsl,tuning-step= <2>; 383 status = "disabled"; 384 }; 385 386 usdhc3: mmc@5b030000 { 387 compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 388 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 389 reg = <0x5b030000 0x10000>; 390 clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>, 391 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>, 392 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>; 393 clock-names = "ipg", "per", "ahb"; 394 power-domains = <&pd IMX_SC_R_SDHC_2>; 395 status = "disabled"; 396 }; 397 398 fec1: ethernet@5b040000 { 399 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 400 reg = <0x5b040000 0x10000>; 401 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, 406 <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, 407 <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, 408 <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; 409 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 410 fsl,num-tx-queues=<3>; 411 fsl,num-rx-queues=<3>; 412 power-domains = <&pd IMX_SC_R_ENET_0>; 413 status = "disabled"; 414 }; 415 416 fec2: ethernet@5b050000 { 417 compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; 418 reg = <0x5b050000 0x10000>; 419 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, 424 <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, 425 <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, 426 <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; 427 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; 428 fsl,num-tx-queues=<3>; 429 fsl,num-rx-queues=<3>; 430 power-domains = <&pd IMX_SC_R_ENET_1>; 431 status = "disabled"; 432 }; 433 }; 434 435 ddr_subsyss: bus@5c000000 { 436 compatible = "simple-bus"; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 ranges = <0x5c000000 0x0 0x5c000000 0x1000000>; 440 441 ddr-pmu@5c020000 { 442 compatible = "fsl,imx8-ddr-pmu"; 443 reg = <0x5c020000 0x10000>; 444 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 445 }; 446 }; 447 448 lsio_subsys: bus@5d000000 { 449 compatible = "simple-bus"; 450 #address-cells = <1>; 451 #size-cells = <1>; 452 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; 453 454 lsio_gpio0: gpio@5d080000 { 455 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 456 reg = <0x5d080000 0x10000>; 457 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 458 gpio-controller; 459 #gpio-cells = <2>; 460 interrupt-controller; 461 #interrupt-cells = <2>; 462 power-domains = <&pd IMX_SC_R_GPIO_0>; 463 }; 464 465 lsio_gpio1: gpio@5d090000 { 466 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 467 reg = <0x5d090000 0x10000>; 468 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 469 gpio-controller; 470 #gpio-cells = <2>; 471 interrupt-controller; 472 #interrupt-cells = <2>; 473 power-domains = <&pd IMX_SC_R_GPIO_1>; 474 }; 475 476 lsio_gpio2: gpio@5d0a0000 { 477 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 478 reg = <0x5d0a0000 0x10000>; 479 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 480 gpio-controller; 481 #gpio-cells = <2>; 482 interrupt-controller; 483 #interrupt-cells = <2>; 484 power-domains = <&pd IMX_SC_R_GPIO_2>; 485 }; 486 487 lsio_gpio3: gpio@5d0b0000 { 488 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 489 reg = <0x5d0b0000 0x10000>; 490 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 491 gpio-controller; 492 #gpio-cells = <2>; 493 interrupt-controller; 494 #interrupt-cells = <2>; 495 power-domains = <&pd IMX_SC_R_GPIO_3>; 496 }; 497 498 lsio_gpio4: gpio@5d0c0000 { 499 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 500 reg = <0x5d0c0000 0x10000>; 501 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 502 gpio-controller; 503 #gpio-cells = <2>; 504 interrupt-controller; 505 #interrupt-cells = <2>; 506 power-domains = <&pd IMX_SC_R_GPIO_4>; 507 }; 508 509 lsio_gpio5: gpio@5d0d0000 { 510 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 511 reg = <0x5d0d0000 0x10000>; 512 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 513 gpio-controller; 514 #gpio-cells = <2>; 515 interrupt-controller; 516 #interrupt-cells = <2>; 517 power-domains = <&pd IMX_SC_R_GPIO_5>; 518 }; 519 520 lsio_gpio6: gpio@5d0e0000 { 521 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 522 reg = <0x5d0e0000 0x10000>; 523 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 524 gpio-controller; 525 #gpio-cells = <2>; 526 interrupt-controller; 527 #interrupt-cells = <2>; 528 power-domains = <&pd IMX_SC_R_GPIO_6>; 529 }; 530 531 lsio_gpio7: gpio@5d0f0000 { 532 compatible = "fsl,imx8qxp-gpio", "fsl,imx35-gpio"; 533 reg = <0x5d0f0000 0x10000>; 534 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 535 gpio-controller; 536 #gpio-cells = <2>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 power-domains = <&pd IMX_SC_R_GPIO_7>; 540 }; 541 542 lsio_mu0: mailbox@5d1b0000 { 543 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 544 reg = <0x5d1b0000 0x10000>; 545 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 546 #mbox-cells = <2>; 547 status = "disabled"; 548 }; 549 550 lsio_mu1: mailbox@5d1c0000 { 551 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 552 reg = <0x5d1c0000 0x10000>; 553 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 554 #mbox-cells = <2>; 555 }; 556 557 lsio_mu2: mailbox@5d1d0000 { 558 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 559 reg = <0x5d1d0000 0x10000>; 560 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 561 #mbox-cells = <2>; 562 status = "disabled"; 563 }; 564 565 lsio_mu3: mailbox@5d1e0000 { 566 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 567 reg = <0x5d1e0000 0x10000>; 568 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 569 #mbox-cells = <2>; 570 status = "disabled"; 571 }; 572 573 lsio_mu4: mailbox@5d1f0000 { 574 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 575 reg = <0x5d1f0000 0x10000>; 576 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 577 #mbox-cells = <2>; 578 status = "disabled"; 579 }; 580 581 lsio_mu13: mailbox@5d280000 { 582 compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu"; 583 reg = <0x5d280000 0x10000>; 584 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 585 #mbox-cells = <2>; 586 power-domains = <&pd IMX_SC_R_MU_13A>; 587 }; 588 589 lsio_lpcg: clock-controller@5d400000 { 590 compatible = "fsl,imx8qxp-lpcg-lsio"; 591 reg = <0x5d400000 0x400000>; 592 #clock-cells = <1>; 593 }; 594 }; 595 596 thermal_zones: thermal-zones { 597 cpu-thermal0 { 598 polling-delay-passive = <250>; 599 polling-delay = <2000>; 600 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; 601 602 trips { 603 cpu_alert0: trip0 { 604 temperature = <107000>; 605 hysteresis = <2000>; 606 type = "passive"; 607 }; 608 609 cpu_crit0: trip1 { 610 temperature = <127000>; 611 hysteresis = <2000>; 612 type = "critical"; 613 }; 614 }; 615 616 cooling-maps { 617 map0 { 618 trip = <&cpu_alert0>; 619 cooling-device = 620 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 621 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 622 <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 623 <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 624 }; 625 }; 626 }; 627 }; 628}; 629