1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i2c_adap_pxa.c 4 * 5 * I2C adapter for the PXA I2C bus access. 6 * 7 * Copyright (C) 2002 Intrinsyc Software Inc. 8 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd. 9 * 10 * History: 11 * Apr 2002: Initial version [CS] 12 * Jun 2002: Properly separated algo/adap [FB] 13 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem] 14 * Jan 2003: added limited signal handling [Kai-Uwe Bloem] 15 * Sep 2004: Major rework to ensure efficient bus handling [RMK] 16 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood] 17 * Feb 2005: Rework slave mode handling [RMK] 18 */ 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/i2c.h> 22 #include <linux/init.h> 23 #include <linux/time.h> 24 #include <linux/sched.h> 25 #include <linux/delay.h> 26 #include <linux/errno.h> 27 #include <linux/interrupt.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/platform_device.h> 31 #include <linux/err.h> 32 #include <linux/clk.h> 33 #include <linux/slab.h> 34 #include <linux/io.h> 35 #include <linux/platform_data/i2c-pxa.h> 36 37 #include <asm/irq.h> 38 39 struct pxa_reg_layout { 40 u32 ibmr; 41 u32 idbr; 42 u32 icr; 43 u32 isr; 44 u32 isar; 45 u32 ilcr; 46 u32 iwcr; 47 u32 fm; 48 u32 hs; 49 }; 50 51 enum pxa_i2c_types { 52 REGS_PXA2XX, 53 REGS_PXA3XX, 54 REGS_CE4100, 55 REGS_PXA910, 56 REGS_A3700, 57 }; 58 59 #define ICR_BUSMODE_FM (1 << 16) /* shifted fast mode for armada-3700 */ 60 #define ICR_BUSMODE_HS (1 << 17) /* shifted high speed mode for armada-3700 */ 61 62 /* 63 * I2C registers definitions 64 */ 65 static struct pxa_reg_layout pxa_reg_layout[] = { 66 [REGS_PXA2XX] = { 67 .ibmr = 0x00, 68 .idbr = 0x08, 69 .icr = 0x10, 70 .isr = 0x18, 71 .isar = 0x20, 72 }, 73 [REGS_PXA3XX] = { 74 .ibmr = 0x00, 75 .idbr = 0x04, 76 .icr = 0x08, 77 .isr = 0x0c, 78 .isar = 0x10, 79 }, 80 [REGS_CE4100] = { 81 .ibmr = 0x14, 82 .idbr = 0x0c, 83 .icr = 0x00, 84 .isr = 0x04, 85 /* no isar register */ 86 }, 87 [REGS_PXA910] = { 88 .ibmr = 0x00, 89 .idbr = 0x08, 90 .icr = 0x10, 91 .isr = 0x18, 92 .isar = 0x20, 93 .ilcr = 0x28, 94 .iwcr = 0x30, 95 }, 96 [REGS_A3700] = { 97 .ibmr = 0x00, 98 .idbr = 0x04, 99 .icr = 0x08, 100 .isr = 0x0c, 101 .isar = 0x10, 102 .fm = ICR_BUSMODE_FM, 103 .hs = ICR_BUSMODE_HS, 104 }, 105 }; 106 107 static const struct platform_device_id i2c_pxa_id_table[] = { 108 { "pxa2xx-i2c", REGS_PXA2XX }, 109 { "pxa3xx-pwri2c", REGS_PXA3XX }, 110 { "ce4100-i2c", REGS_CE4100 }, 111 { "pxa910-i2c", REGS_PXA910 }, 112 { "armada-3700-i2c", REGS_A3700 }, 113 { }, 114 }; 115 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table); 116 117 /* 118 * I2C bit definitions 119 */ 120 121 #define ICR_START (1 << 0) /* start bit */ 122 #define ICR_STOP (1 << 1) /* stop bit */ 123 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */ 124 #define ICR_TB (1 << 3) /* transfer byte bit */ 125 #define ICR_MA (1 << 4) /* master abort */ 126 #define ICR_SCLE (1 << 5) /* master clock enable */ 127 #define ICR_IUE (1 << 6) /* unit enable */ 128 #define ICR_GCD (1 << 7) /* general call disable */ 129 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */ 130 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */ 131 #define ICR_BEIE (1 << 10) /* enable bus error ints */ 132 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */ 133 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */ 134 #define ICR_SADIE (1 << 13) /* slave address detected int enable */ 135 #define ICR_UR (1 << 14) /* unit reset */ 136 #define ICR_FM (1 << 15) /* fast mode */ 137 #define ICR_HS (1 << 16) /* High Speed mode */ 138 #define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */ 139 140 #define ISR_RWM (1 << 0) /* read/write mode */ 141 #define ISR_ACKNAK (1 << 1) /* ack/nak status */ 142 #define ISR_UB (1 << 2) /* unit busy */ 143 #define ISR_IBB (1 << 3) /* bus busy */ 144 #define ISR_SSD (1 << 4) /* slave stop detected */ 145 #define ISR_ALD (1 << 5) /* arbitration loss detected */ 146 #define ISR_ITE (1 << 6) /* tx buffer empty */ 147 #define ISR_IRF (1 << 7) /* rx buffer full */ 148 #define ISR_GCAD (1 << 8) /* general call address detected */ 149 #define ISR_SAD (1 << 9) /* slave address detected */ 150 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */ 151 152 /* bit field shift & mask */ 153 #define ILCR_SLV_SHIFT 0 154 #define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT) 155 #define ILCR_FLV_SHIFT 9 156 #define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT) 157 #define ILCR_HLVL_SHIFT 18 158 #define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT) 159 #define ILCR_HLVH_SHIFT 27 160 #define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT) 161 162 #define IWCR_CNT_SHIFT 0 163 #define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT) 164 #define IWCR_HS_CNT1_SHIFT 5 165 #define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT) 166 #define IWCR_HS_CNT2_SHIFT 10 167 #define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT) 168 169 struct pxa_i2c { 170 spinlock_t lock; 171 wait_queue_head_t wait; 172 struct i2c_msg *msg; 173 unsigned int msg_num; 174 unsigned int msg_idx; 175 unsigned int msg_ptr; 176 unsigned int slave_addr; 177 unsigned int req_slave_addr; 178 179 struct i2c_adapter adap; 180 struct clk *clk; 181 #ifdef CONFIG_I2C_PXA_SLAVE 182 struct i2c_client *slave; 183 #endif 184 185 unsigned int irqlogidx; 186 u32 isrlog[32]; 187 u32 icrlog[32]; 188 189 void __iomem *reg_base; 190 void __iomem *reg_ibmr; 191 void __iomem *reg_idbr; 192 void __iomem *reg_icr; 193 void __iomem *reg_isr; 194 void __iomem *reg_isar; 195 void __iomem *reg_ilcr; 196 void __iomem *reg_iwcr; 197 198 unsigned long iobase; 199 unsigned long iosize; 200 201 int irq; 202 unsigned int use_pio :1; 203 unsigned int fast_mode :1; 204 unsigned int high_mode:1; 205 unsigned char master_code; 206 unsigned long rate; 207 bool highmode_enter; 208 u32 fm_mask; 209 u32 hs_mask; 210 }; 211 212 #define _IBMR(i2c) ((i2c)->reg_ibmr) 213 #define _IDBR(i2c) ((i2c)->reg_idbr) 214 #define _ICR(i2c) ((i2c)->reg_icr) 215 #define _ISR(i2c) ((i2c)->reg_isr) 216 #define _ISAR(i2c) ((i2c)->reg_isar) 217 #define _ILCR(i2c) ((i2c)->reg_ilcr) 218 #define _IWCR(i2c) ((i2c)->reg_iwcr) 219 220 /* 221 * I2C Slave mode address 222 */ 223 #define I2C_PXA_SLAVE_ADDR 0x1 224 225 #ifdef DEBUG 226 227 struct bits { 228 u32 mask; 229 const char *set; 230 const char *unset; 231 }; 232 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u } 233 234 static inline void 235 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val) 236 { 237 printk("%s %08x: ", prefix, val); 238 while (num--) { 239 const char *str = val & bits->mask ? bits->set : bits->unset; 240 if (str) 241 printk("%s ", str); 242 bits++; 243 } 244 } 245 246 static const struct bits isr_bits[] = { 247 PXA_BIT(ISR_RWM, "RX", "TX"), 248 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"), 249 PXA_BIT(ISR_UB, "Bsy", "Rdy"), 250 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"), 251 PXA_BIT(ISR_SSD, "SlaveStop", NULL), 252 PXA_BIT(ISR_ALD, "ALD", NULL), 253 PXA_BIT(ISR_ITE, "TxEmpty", NULL), 254 PXA_BIT(ISR_IRF, "RxFull", NULL), 255 PXA_BIT(ISR_GCAD, "GenCall", NULL), 256 PXA_BIT(ISR_SAD, "SlaveAddr", NULL), 257 PXA_BIT(ISR_BED, "BusErr", NULL), 258 }; 259 260 static void decode_ISR(unsigned int val) 261 { 262 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val); 263 printk("\n"); 264 } 265 266 static const struct bits icr_bits[] = { 267 PXA_BIT(ICR_START, "START", NULL), 268 PXA_BIT(ICR_STOP, "STOP", NULL), 269 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL), 270 PXA_BIT(ICR_TB, "TB", NULL), 271 PXA_BIT(ICR_MA, "MA", NULL), 272 PXA_BIT(ICR_SCLE, "SCLE", "scle"), 273 PXA_BIT(ICR_IUE, "IUE", "iue"), 274 PXA_BIT(ICR_GCD, "GCD", NULL), 275 PXA_BIT(ICR_ITEIE, "ITEIE", NULL), 276 PXA_BIT(ICR_IRFIE, "IRFIE", NULL), 277 PXA_BIT(ICR_BEIE, "BEIE", NULL), 278 PXA_BIT(ICR_SSDIE, "SSDIE", NULL), 279 PXA_BIT(ICR_ALDIE, "ALDIE", NULL), 280 PXA_BIT(ICR_SADIE, "SADIE", NULL), 281 PXA_BIT(ICR_UR, "UR", "ur"), 282 }; 283 284 #ifdef CONFIG_I2C_PXA_SLAVE 285 static void decode_ICR(unsigned int val) 286 { 287 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val); 288 printk("\n"); 289 } 290 #endif 291 292 static unsigned int i2c_debug = DEBUG; 293 294 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname) 295 { 296 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, 297 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 298 } 299 300 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__) 301 302 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why) 303 { 304 unsigned int i; 305 struct device *dev = &i2c->adap.dev; 306 307 dev_err(dev, "slave_0x%x error: %s\n", 308 i2c->req_slave_addr >> 1, why); 309 dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n", 310 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr); 311 dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n", 312 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)), 313 readl(_ISR(i2c))); 314 dev_dbg(dev, "log: "); 315 for (i = 0; i < i2c->irqlogidx; i++) 316 pr_debug("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]); 317 318 pr_debug("\n"); 319 } 320 321 #else /* ifdef DEBUG */ 322 323 #define i2c_debug 0 324 325 #define show_state(i2c) do { } while (0) 326 #define decode_ISR(val) do { } while (0) 327 #define decode_ICR(val) do { } while (0) 328 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0) 329 330 #endif /* ifdef DEBUG / else */ 331 332 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret); 333 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id); 334 335 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c) 336 { 337 return !(readl(_ICR(i2c)) & ICR_SCLE); 338 } 339 340 static void i2c_pxa_abort(struct pxa_i2c *i2c) 341 { 342 int i = 250; 343 344 if (i2c_pxa_is_slavemode(i2c)) { 345 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__); 346 return; 347 } 348 349 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) { 350 unsigned long icr = readl(_ICR(i2c)); 351 352 icr &= ~ICR_START; 353 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB; 354 355 writel(icr, _ICR(i2c)); 356 357 show_state(i2c); 358 359 mdelay(1); 360 i --; 361 } 362 363 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), 364 _ICR(i2c)); 365 } 366 367 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c) 368 { 369 int timeout = DEF_TIMEOUT; 370 371 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { 372 if ((readl(_ISR(i2c)) & ISR_SAD) != 0) 373 timeout += 4; 374 375 msleep(2); 376 show_state(i2c); 377 } 378 379 if (timeout < 0) 380 show_state(i2c); 381 382 return timeout < 0 ? I2C_RETRY : 0; 383 } 384 385 static int i2c_pxa_wait_master(struct pxa_i2c *i2c) 386 { 387 unsigned long timeout = jiffies + HZ*4; 388 389 while (time_before(jiffies, timeout)) { 390 if (i2c_debug > 1) 391 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 392 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 393 394 if (readl(_ISR(i2c)) & ISR_SAD) { 395 if (i2c_debug > 0) 396 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__); 397 goto out; 398 } 399 400 /* wait for unit and bus being not busy, and we also do a 401 * quick check of the i2c lines themselves to ensure they've 402 * gone high... 403 */ 404 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) { 405 if (i2c_debug > 0) 406 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 407 return 1; 408 } 409 410 msleep(1); 411 } 412 413 if (i2c_debug > 0) 414 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); 415 out: 416 return 0; 417 } 418 419 static int i2c_pxa_set_master(struct pxa_i2c *i2c) 420 { 421 if (i2c_debug) 422 dev_dbg(&i2c->adap.dev, "setting to bus master\n"); 423 424 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) { 425 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__); 426 if (!i2c_pxa_wait_master(i2c)) { 427 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__); 428 return I2C_RETRY; 429 } 430 } 431 432 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); 433 return 0; 434 } 435 436 #ifdef CONFIG_I2C_PXA_SLAVE 437 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c) 438 { 439 unsigned long timeout = jiffies + HZ*1; 440 441 /* wait for stop */ 442 443 show_state(i2c); 444 445 while (time_before(jiffies, timeout)) { 446 if (i2c_debug > 1) 447 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n", 448 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c))); 449 450 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 || 451 (readl(_ISR(i2c)) & ISR_SAD) != 0 || 452 (readl(_ICR(i2c)) & ICR_SCLE) == 0) { 453 if (i2c_debug > 1) 454 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__); 455 return 1; 456 } 457 458 msleep(1); 459 } 460 461 if (i2c_debug > 0) 462 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__); 463 return 0; 464 } 465 466 /* 467 * clear the hold on the bus, and take of anything else 468 * that has been configured 469 */ 470 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode) 471 { 472 show_state(i2c); 473 474 if (errcode < 0) { 475 udelay(100); /* simple delay */ 476 } else { 477 /* we need to wait for the stop condition to end */ 478 479 /* if we where in stop, then clear... */ 480 if (readl(_ICR(i2c)) & ICR_STOP) { 481 udelay(100); 482 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); 483 } 484 485 if (!i2c_pxa_wait_slave(i2c)) { 486 dev_err(&i2c->adap.dev, "%s: wait timedout\n", 487 __func__); 488 return; 489 } 490 } 491 492 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); 493 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 494 495 if (i2c_debug) { 496 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c))); 497 decode_ICR(readl(_ICR(i2c))); 498 } 499 } 500 #else 501 #define i2c_pxa_set_slave(i2c, err) do { } while (0) 502 #endif 503 504 static void i2c_pxa_reset(struct pxa_i2c *i2c) 505 { 506 pr_debug("Resetting I2C Controller Unit\n"); 507 508 /* abort any transfer currently under way */ 509 i2c_pxa_abort(i2c); 510 511 /* reset according to 9.8 */ 512 writel(ICR_UR, _ICR(i2c)); 513 writel(I2C_ISR_INIT, _ISR(i2c)); 514 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); 515 516 if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE)) 517 writel(i2c->slave_addr, _ISAR(i2c)); 518 519 /* set control register values */ 520 writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c)); 521 writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c)); 522 523 #ifdef CONFIG_I2C_PXA_SLAVE 524 dev_info(&i2c->adap.dev, "Enabling slave mode\n"); 525 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c)); 526 #endif 527 528 i2c_pxa_set_slave(i2c, 0); 529 530 /* enable unit */ 531 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c)); 532 udelay(100); 533 } 534 535 536 #ifdef CONFIG_I2C_PXA_SLAVE 537 /* 538 * PXA I2C Slave mode 539 */ 540 541 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) 542 { 543 if (isr & ISR_BED) { 544 /* what should we do here? */ 545 } else { 546 u8 byte = 0; 547 548 if (i2c->slave != NULL) 549 i2c_slave_event(i2c->slave, I2C_SLAVE_READ_PROCESSED, 550 &byte); 551 552 writel(byte, _IDBR(i2c)); 553 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */ 554 } 555 } 556 557 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 558 { 559 u8 byte = readl(_IDBR(i2c)); 560 561 if (i2c->slave != NULL) 562 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_RECEIVED, &byte); 563 564 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 565 } 566 567 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 568 { 569 int timeout; 570 571 if (i2c_debug > 0) 572 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n", 573 (isr & ISR_RWM) ? 'r' : 't'); 574 575 if (i2c->slave != NULL) { 576 if (isr & ISR_RWM) { 577 u8 byte = 0; 578 579 i2c_slave_event(i2c->slave, I2C_SLAVE_READ_REQUESTED, 580 &byte); 581 writel(byte, _IDBR(i2c)); 582 } else { 583 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_REQUESTED, 584 NULL); 585 } 586 } 587 588 /* 589 * slave could interrupt in the middle of us generating a 590 * start condition... if this happens, we'd better back off 591 * and stop holding the poor thing up 592 */ 593 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); 594 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 595 596 timeout = 0x10000; 597 598 while (1) { 599 if ((readl(_IBMR(i2c)) & 2) == 2) 600 break; 601 602 timeout--; 603 604 if (timeout <= 0) { 605 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); 606 break; 607 } 608 } 609 610 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 611 } 612 613 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 614 { 615 if (i2c_debug > 2) 616 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n"); 617 618 if (i2c->slave != NULL) 619 i2c_slave_event(i2c->slave, I2C_SLAVE_STOP, NULL); 620 621 if (i2c_debug > 2) 622 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n"); 623 624 /* 625 * If we have a master-mode message waiting, 626 * kick it off now that the slave has completed. 627 */ 628 if (i2c->msg) 629 i2c_pxa_master_complete(i2c, I2C_RETRY); 630 } 631 632 static int i2c_pxa_slave_reg(struct i2c_client *slave) 633 { 634 struct pxa_i2c *i2c = slave->adapter->algo_data; 635 636 if (i2c->slave) 637 return -EBUSY; 638 639 if (!i2c->reg_isar) 640 return -EAFNOSUPPORT; 641 642 i2c->slave = slave; 643 i2c->slave_addr = slave->addr; 644 645 writel(i2c->slave_addr, _ISAR(i2c)); 646 647 return 0; 648 } 649 650 static int i2c_pxa_slave_unreg(struct i2c_client *slave) 651 { 652 struct pxa_i2c *i2c = slave->adapter->algo_data; 653 654 WARN_ON(!i2c->slave); 655 656 i2c->slave_addr = I2C_PXA_SLAVE_ADDR; 657 writel(i2c->slave_addr, _ISAR(i2c)); 658 659 i2c->slave = NULL; 660 661 return 0; 662 } 663 #else 664 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr) 665 { 666 if (isr & ISR_BED) { 667 /* what should we do here? */ 668 } else { 669 writel(0, _IDBR(i2c)); 670 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); 671 } 672 } 673 674 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr) 675 { 676 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); 677 } 678 679 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr) 680 { 681 int timeout; 682 683 /* 684 * slave could interrupt in the middle of us generating a 685 * start condition... if this happens, we'd better back off 686 * and stop holding the poor thing up 687 */ 688 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c)); 689 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c)); 690 691 timeout = 0x10000; 692 693 while (1) { 694 if ((readl(_IBMR(i2c)) & 2) == 2) 695 break; 696 697 timeout--; 698 699 if (timeout <= 0) { 700 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n"); 701 break; 702 } 703 } 704 705 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); 706 } 707 708 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c) 709 { 710 if (i2c->msg) 711 i2c_pxa_master_complete(i2c, I2C_RETRY); 712 } 713 #endif 714 715 /* 716 * PXA I2C Master mode 717 */ 718 719 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg) 720 { 721 unsigned int addr = (msg->addr & 0x7f) << 1; 722 723 if (msg->flags & I2C_M_RD) 724 addr |= 1; 725 726 return addr; 727 } 728 729 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c) 730 { 731 u32 icr; 732 733 /* 734 * Step 1: target slave address into IDBR 735 */ 736 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); 737 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg); 738 739 /* 740 * Step 2: initiate the write. 741 */ 742 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); 743 writel(icr | ICR_START | ICR_TB, _ICR(i2c)); 744 } 745 746 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c) 747 { 748 u32 icr; 749 750 /* 751 * Clear the STOP and ACK flags 752 */ 753 icr = readl(_ICR(i2c)); 754 icr &= ~(ICR_STOP | ICR_ACKNAK); 755 writel(icr, _ICR(i2c)); 756 } 757 758 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c) 759 { 760 /* make timeout the same as for interrupt based functions */ 761 long timeout = 2 * DEF_TIMEOUT; 762 763 /* 764 * Wait for the bus to become free. 765 */ 766 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) { 767 udelay(1000); 768 show_state(i2c); 769 } 770 771 if (timeout < 0) { 772 show_state(i2c); 773 dev_err(&i2c->adap.dev, 774 "i2c_pxa: timeout waiting for bus free\n"); 775 return I2C_RETRY; 776 } 777 778 /* 779 * Set master mode. 780 */ 781 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); 782 783 return 0; 784 } 785 786 /* 787 * PXA I2C send master code 788 * 1. Load master code to IDBR and send it. 789 * Note for HS mode, set ICR [GPIOEN]. 790 * 2. Wait until win arbitration. 791 */ 792 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c) 793 { 794 u32 icr; 795 long timeout; 796 797 spin_lock_irq(&i2c->lock); 798 i2c->highmode_enter = true; 799 writel(i2c->master_code, _IDBR(i2c)); 800 801 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE); 802 icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE; 803 writel(icr, _ICR(i2c)); 804 805 spin_unlock_irq(&i2c->lock); 806 timeout = wait_event_timeout(i2c->wait, 807 i2c->highmode_enter == false, HZ * 1); 808 809 i2c->highmode_enter = false; 810 811 return (timeout == 0) ? I2C_RETRY : 0; 812 } 813 814 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c, 815 struct i2c_msg *msg, int num) 816 { 817 unsigned long timeout = 500000; /* 5 seconds */ 818 int ret = 0; 819 820 ret = i2c_pxa_pio_set_master(i2c); 821 if (ret) 822 goto out; 823 824 i2c->msg = msg; 825 i2c->msg_num = num; 826 i2c->msg_idx = 0; 827 i2c->msg_ptr = 0; 828 i2c->irqlogidx = 0; 829 830 i2c_pxa_start_message(i2c); 831 832 while (i2c->msg_num > 0 && --timeout) { 833 i2c_pxa_handler(0, i2c); 834 udelay(10); 835 } 836 837 i2c_pxa_stop_message(i2c); 838 839 /* 840 * We place the return code in i2c->msg_idx. 841 */ 842 ret = i2c->msg_idx; 843 844 out: 845 if (timeout == 0) { 846 i2c_pxa_scream_blue_murder(i2c, "timeout"); 847 ret = I2C_RETRY; 848 } 849 850 return ret; 851 } 852 853 /* 854 * We are protected by the adapter bus mutex. 855 */ 856 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num) 857 { 858 long timeout; 859 int ret; 860 861 /* 862 * Wait for the bus to become free. 863 */ 864 ret = i2c_pxa_wait_bus_not_busy(i2c); 865 if (ret) { 866 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n"); 867 goto out; 868 } 869 870 /* 871 * Set master mode. 872 */ 873 ret = i2c_pxa_set_master(i2c); 874 if (ret) { 875 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret); 876 goto out; 877 } 878 879 if (i2c->high_mode) { 880 ret = i2c_pxa_send_mastercode(i2c); 881 if (ret) { 882 dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n"); 883 goto out; 884 } 885 } 886 887 spin_lock_irq(&i2c->lock); 888 889 i2c->msg = msg; 890 i2c->msg_num = num; 891 i2c->msg_idx = 0; 892 i2c->msg_ptr = 0; 893 i2c->irqlogidx = 0; 894 895 i2c_pxa_start_message(i2c); 896 897 spin_unlock_irq(&i2c->lock); 898 899 /* 900 * The rest of the processing occurs in the interrupt handler. 901 */ 902 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 903 i2c_pxa_stop_message(i2c); 904 905 /* 906 * We place the return code in i2c->msg_idx. 907 */ 908 ret = i2c->msg_idx; 909 910 if (!timeout && i2c->msg_num) { 911 i2c_pxa_scream_blue_murder(i2c, "timeout"); 912 ret = I2C_RETRY; 913 } 914 915 out: 916 return ret; 917 } 918 919 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap, 920 struct i2c_msg msgs[], int num) 921 { 922 struct pxa_i2c *i2c = adap->algo_data; 923 int ret, i; 924 925 /* If the I2C controller is disabled we need to reset it 926 (probably due to a suspend/resume destroying state). We do 927 this here as we can then avoid worrying about resuming the 928 controller before its users. */ 929 if (!(readl(_ICR(i2c)) & ICR_IUE)) 930 i2c_pxa_reset(i2c); 931 932 for (i = adap->retries; i >= 0; i--) { 933 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num); 934 if (ret != I2C_RETRY) 935 goto out; 936 937 if (i2c_debug) 938 dev_dbg(&adap->dev, "Retrying transmission\n"); 939 udelay(100); 940 } 941 i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); 942 ret = -EREMOTEIO; 943 out: 944 i2c_pxa_set_slave(i2c, ret); 945 return ret; 946 } 947 948 /* 949 * i2c_pxa_master_complete - complete the message and wake up. 950 */ 951 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret) 952 { 953 i2c->msg_ptr = 0; 954 i2c->msg = NULL; 955 i2c->msg_idx ++; 956 i2c->msg_num = 0; 957 if (ret) 958 i2c->msg_idx = ret; 959 if (!i2c->use_pio) 960 wake_up(&i2c->wait); 961 } 962 963 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr) 964 { 965 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 966 967 again: 968 /* 969 * If ISR_ALD is set, we lost arbitration. 970 */ 971 if (isr & ISR_ALD) { 972 /* 973 * Do we need to do anything here? The PXA docs 974 * are vague about what happens. 975 */ 976 i2c_pxa_scream_blue_murder(i2c, "ALD set"); 977 978 /* 979 * We ignore this error. We seem to see spurious ALDs 980 * for seemingly no reason. If we handle them as I think 981 * they should, we end up causing an I2C error, which 982 * is painful for some systems. 983 */ 984 return; /* ignore */ 985 } 986 987 if ((isr & ISR_BED) && 988 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) && 989 (isr & ISR_ACKNAK)))) { 990 int ret = BUS_ERROR; 991 992 /* 993 * I2C bus error - either the device NAK'd us, or 994 * something more serious happened. If we were NAK'd 995 * on the initial address phase, we can retry. 996 */ 997 if (isr & ISR_ACKNAK) { 998 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0) 999 ret = I2C_RETRY; 1000 else 1001 ret = XFER_NAKED; 1002 } 1003 i2c_pxa_master_complete(i2c, ret); 1004 } else if (isr & ISR_RWM) { 1005 /* 1006 * Read mode. We have just sent the address byte, and 1007 * now we must initiate the transfer. 1008 */ 1009 if (i2c->msg_ptr == i2c->msg->len - 1 && 1010 i2c->msg_idx == i2c->msg_num - 1) 1011 icr |= ICR_STOP | ICR_ACKNAK; 1012 1013 icr |= ICR_ALDIE | ICR_TB; 1014 } else if (i2c->msg_ptr < i2c->msg->len) { 1015 /* 1016 * Write mode. Write the next data byte. 1017 */ 1018 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c)); 1019 1020 icr |= ICR_ALDIE | ICR_TB; 1021 1022 /* 1023 * If this is the last byte of the last message or last byte 1024 * of any message with I2C_M_STOP (e.g. SCCB), send a STOP. 1025 */ 1026 if ((i2c->msg_ptr == i2c->msg->len) && 1027 ((i2c->msg->flags & I2C_M_STOP) || 1028 (i2c->msg_idx == i2c->msg_num - 1))) 1029 icr |= ICR_STOP; 1030 1031 } else if (i2c->msg_idx < i2c->msg_num - 1) { 1032 /* 1033 * Next segment of the message. 1034 */ 1035 i2c->msg_ptr = 0; 1036 i2c->msg_idx ++; 1037 i2c->msg++; 1038 1039 /* 1040 * If we aren't doing a repeated start and address, 1041 * go back and try to send the next byte. Note that 1042 * we do not support switching the R/W direction here. 1043 */ 1044 if (i2c->msg->flags & I2C_M_NOSTART) 1045 goto again; 1046 1047 /* 1048 * Write the next address. 1049 */ 1050 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c)); 1051 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg); 1052 1053 /* 1054 * And trigger a repeated start, and send the byte. 1055 */ 1056 icr &= ~ICR_ALDIE; 1057 icr |= ICR_START | ICR_TB; 1058 } else { 1059 if (i2c->msg->len == 0) { 1060 /* 1061 * Device probes have a message length of zero 1062 * and need the bus to be reset before it can 1063 * be used again. 1064 */ 1065 i2c_pxa_reset(i2c); 1066 } 1067 i2c_pxa_master_complete(i2c, 0); 1068 } 1069 1070 i2c->icrlog[i2c->irqlogidx-1] = icr; 1071 1072 writel(icr, _ICR(i2c)); 1073 show_state(i2c); 1074 } 1075 1076 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr) 1077 { 1078 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB); 1079 1080 /* 1081 * Read the byte. 1082 */ 1083 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c)); 1084 1085 if (i2c->msg_ptr < i2c->msg->len) { 1086 /* 1087 * If this is the last byte of the last 1088 * message, send a STOP. 1089 */ 1090 if (i2c->msg_ptr == i2c->msg->len - 1) 1091 icr |= ICR_STOP | ICR_ACKNAK; 1092 1093 icr |= ICR_ALDIE | ICR_TB; 1094 } else { 1095 i2c_pxa_master_complete(i2c, 0); 1096 } 1097 1098 i2c->icrlog[i2c->irqlogidx-1] = icr; 1099 1100 writel(icr, _ICR(i2c)); 1101 } 1102 1103 #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \ 1104 ISR_SAD | ISR_BED) 1105 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id) 1106 { 1107 struct pxa_i2c *i2c = dev_id; 1108 u32 isr = readl(_ISR(i2c)); 1109 1110 if (!(isr & VALID_INT_SOURCE)) 1111 return IRQ_NONE; 1112 1113 if (i2c_debug > 2 && 0) { 1114 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n", 1115 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c))); 1116 decode_ISR(isr); 1117 } 1118 1119 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog)) 1120 i2c->isrlog[i2c->irqlogidx++] = isr; 1121 1122 show_state(i2c); 1123 1124 /* 1125 * Always clear all pending IRQs. 1126 */ 1127 writel(isr & VALID_INT_SOURCE, _ISR(i2c)); 1128 1129 if (isr & ISR_SAD) 1130 i2c_pxa_slave_start(i2c, isr); 1131 if (isr & ISR_SSD) 1132 i2c_pxa_slave_stop(i2c); 1133 1134 if (i2c_pxa_is_slavemode(i2c)) { 1135 if (isr & ISR_ITE) 1136 i2c_pxa_slave_txempty(i2c, isr); 1137 if (isr & ISR_IRF) 1138 i2c_pxa_slave_rxfull(i2c, isr); 1139 } else if (i2c->msg && (!i2c->highmode_enter)) { 1140 if (isr & ISR_ITE) 1141 i2c_pxa_irq_txempty(i2c, isr); 1142 if (isr & ISR_IRF) 1143 i2c_pxa_irq_rxfull(i2c, isr); 1144 } else if ((isr & ISR_ITE) && i2c->highmode_enter) { 1145 i2c->highmode_enter = false; 1146 wake_up(&i2c->wait); 1147 } else { 1148 i2c_pxa_scream_blue_murder(i2c, "spurious irq"); 1149 } 1150 1151 return IRQ_HANDLED; 1152 } 1153 1154 1155 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 1156 { 1157 struct pxa_i2c *i2c = adap->algo_data; 1158 int ret, i; 1159 1160 for (i = adap->retries; i >= 0; i--) { 1161 ret = i2c_pxa_do_xfer(i2c, msgs, num); 1162 if (ret != I2C_RETRY) 1163 goto out; 1164 1165 if (i2c_debug) 1166 dev_dbg(&adap->dev, "Retrying transmission\n"); 1167 udelay(100); 1168 } 1169 i2c_pxa_scream_blue_murder(i2c, "exhausted retries"); 1170 ret = -EREMOTEIO; 1171 out: 1172 i2c_pxa_set_slave(i2c, ret); 1173 return ret; 1174 } 1175 1176 static u32 i2c_pxa_functionality(struct i2c_adapter *adap) 1177 { 1178 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 1179 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART; 1180 } 1181 1182 static const struct i2c_algorithm i2c_pxa_algorithm = { 1183 .master_xfer = i2c_pxa_xfer, 1184 .functionality = i2c_pxa_functionality, 1185 #ifdef CONFIG_I2C_PXA_SLAVE 1186 .reg_slave = i2c_pxa_slave_reg, 1187 .unreg_slave = i2c_pxa_slave_unreg, 1188 #endif 1189 }; 1190 1191 static const struct i2c_algorithm i2c_pxa_pio_algorithm = { 1192 .master_xfer = i2c_pxa_pio_xfer, 1193 .functionality = i2c_pxa_functionality, 1194 #ifdef CONFIG_I2C_PXA_SLAVE 1195 .reg_slave = i2c_pxa_slave_reg, 1196 .unreg_slave = i2c_pxa_slave_unreg, 1197 #endif 1198 }; 1199 1200 static const struct of_device_id i2c_pxa_dt_ids[] = { 1201 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX }, 1202 { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX }, 1203 { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 }, 1204 { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 }, 1205 {} 1206 }; 1207 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids); 1208 1209 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c, 1210 enum pxa_i2c_types *i2c_types) 1211 { 1212 struct device_node *np = pdev->dev.of_node; 1213 const struct of_device_id *of_id = 1214 of_match_device(i2c_pxa_dt_ids, &pdev->dev); 1215 1216 if (!of_id) 1217 return 1; 1218 1219 /* For device tree we always use the dynamic or alias-assigned ID */ 1220 i2c->adap.nr = -1; 1221 1222 if (of_get_property(np, "mrvl,i2c-polling", NULL)) 1223 i2c->use_pio = 1; 1224 if (of_get_property(np, "mrvl,i2c-fast-mode", NULL)) 1225 i2c->fast_mode = 1; 1226 1227 *i2c_types = (enum pxa_i2c_types)(of_id->data); 1228 1229 return 0; 1230 } 1231 1232 static int i2c_pxa_probe_pdata(struct platform_device *pdev, 1233 struct pxa_i2c *i2c, 1234 enum pxa_i2c_types *i2c_types) 1235 { 1236 struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev); 1237 const struct platform_device_id *id = platform_get_device_id(pdev); 1238 1239 *i2c_types = id->driver_data; 1240 if (plat) { 1241 i2c->use_pio = plat->use_pio; 1242 i2c->fast_mode = plat->fast_mode; 1243 i2c->high_mode = plat->high_mode; 1244 i2c->master_code = plat->master_code; 1245 if (!i2c->master_code) 1246 i2c->master_code = 0xe; 1247 i2c->rate = plat->rate; 1248 } 1249 return 0; 1250 } 1251 1252 static int i2c_pxa_probe(struct platform_device *dev) 1253 { 1254 struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev); 1255 enum pxa_i2c_types i2c_type; 1256 struct pxa_i2c *i2c; 1257 struct resource *res = NULL; 1258 int ret, irq; 1259 1260 i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL); 1261 if (!i2c) 1262 return -ENOMEM; 1263 1264 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 1265 i2c->reg_base = devm_ioremap_resource(&dev->dev, res); 1266 if (IS_ERR(i2c->reg_base)) 1267 return PTR_ERR(i2c->reg_base); 1268 1269 irq = platform_get_irq(dev, 0); 1270 if (irq < 0) { 1271 dev_err(&dev->dev, "no irq resource: %d\n", irq); 1272 return irq; 1273 } 1274 1275 /* Default adapter num to device id; i2c_pxa_probe_dt can override. */ 1276 i2c->adap.nr = dev->id; 1277 1278 ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type); 1279 if (ret > 0) 1280 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type); 1281 if (ret < 0) 1282 return ret; 1283 1284 i2c->adap.owner = THIS_MODULE; 1285 i2c->adap.retries = 5; 1286 1287 spin_lock_init(&i2c->lock); 1288 init_waitqueue_head(&i2c->wait); 1289 1290 strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name)); 1291 1292 i2c->clk = devm_clk_get(&dev->dev, NULL); 1293 if (IS_ERR(i2c->clk)) { 1294 dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk)); 1295 return PTR_ERR(i2c->clk); 1296 } 1297 1298 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr; 1299 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr; 1300 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr; 1301 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr; 1302 i2c->fm_mask = pxa_reg_layout[i2c_type].fm ? : ICR_FM; 1303 i2c->hs_mask = pxa_reg_layout[i2c_type].hs ? : ICR_HS; 1304 1305 if (i2c_type != REGS_CE4100) 1306 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar; 1307 1308 if (i2c_type == REGS_PXA910) { 1309 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr; 1310 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr; 1311 } 1312 1313 i2c->iobase = res->start; 1314 i2c->iosize = resource_size(res); 1315 1316 i2c->irq = irq; 1317 1318 i2c->slave_addr = I2C_PXA_SLAVE_ADDR; 1319 i2c->highmode_enter = false; 1320 1321 if (plat) { 1322 i2c->adap.class = plat->class; 1323 } 1324 1325 if (i2c->high_mode) { 1326 if (i2c->rate) { 1327 clk_set_rate(i2c->clk, i2c->rate); 1328 pr_info("i2c: <%s> set rate to %ld\n", 1329 i2c->adap.name, clk_get_rate(i2c->clk)); 1330 } else 1331 pr_warn("i2c: <%s> clock rate not set\n", 1332 i2c->adap.name); 1333 } 1334 1335 clk_prepare_enable(i2c->clk); 1336 1337 if (i2c->use_pio) { 1338 i2c->adap.algo = &i2c_pxa_pio_algorithm; 1339 } else { 1340 i2c->adap.algo = &i2c_pxa_algorithm; 1341 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler, 1342 IRQF_SHARED | IRQF_NO_SUSPEND, 1343 dev_name(&dev->dev), i2c); 1344 if (ret) { 1345 dev_err(&dev->dev, "failed to request irq: %d\n", ret); 1346 goto ereqirq; 1347 } 1348 } 1349 1350 i2c_pxa_reset(i2c); 1351 1352 i2c->adap.algo_data = i2c; 1353 i2c->adap.dev.parent = &dev->dev; 1354 #ifdef CONFIG_OF 1355 i2c->adap.dev.of_node = dev->dev.of_node; 1356 #endif 1357 1358 ret = i2c_add_numbered_adapter(&i2c->adap); 1359 if (ret < 0) 1360 goto ereqirq; 1361 1362 platform_set_drvdata(dev, i2c); 1363 1364 #ifdef CONFIG_I2C_PXA_SLAVE 1365 dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n", 1366 i2c->slave_addr); 1367 #else 1368 dev_info(&i2c->adap.dev, " PXA I2C adapter\n"); 1369 #endif 1370 return 0; 1371 1372 ereqirq: 1373 clk_disable_unprepare(i2c->clk); 1374 return ret; 1375 } 1376 1377 static int i2c_pxa_remove(struct platform_device *dev) 1378 { 1379 struct pxa_i2c *i2c = platform_get_drvdata(dev); 1380 1381 i2c_del_adapter(&i2c->adap); 1382 1383 clk_disable_unprepare(i2c->clk); 1384 1385 return 0; 1386 } 1387 1388 #ifdef CONFIG_PM 1389 static int i2c_pxa_suspend_noirq(struct device *dev) 1390 { 1391 struct pxa_i2c *i2c = dev_get_drvdata(dev); 1392 1393 clk_disable(i2c->clk); 1394 1395 return 0; 1396 } 1397 1398 static int i2c_pxa_resume_noirq(struct device *dev) 1399 { 1400 struct pxa_i2c *i2c = dev_get_drvdata(dev); 1401 1402 clk_enable(i2c->clk); 1403 i2c_pxa_reset(i2c); 1404 1405 return 0; 1406 } 1407 1408 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = { 1409 .suspend_noirq = i2c_pxa_suspend_noirq, 1410 .resume_noirq = i2c_pxa_resume_noirq, 1411 }; 1412 1413 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops) 1414 #else 1415 #define I2C_PXA_DEV_PM_OPS NULL 1416 #endif 1417 1418 static struct platform_driver i2c_pxa_driver = { 1419 .probe = i2c_pxa_probe, 1420 .remove = i2c_pxa_remove, 1421 .driver = { 1422 .name = "pxa2xx-i2c", 1423 .pm = I2C_PXA_DEV_PM_OPS, 1424 .of_match_table = i2c_pxa_dt_ids, 1425 }, 1426 .id_table = i2c_pxa_id_table, 1427 }; 1428 1429 static int __init i2c_adap_pxa_init(void) 1430 { 1431 return platform_driver_register(&i2c_pxa_driver); 1432 } 1433 1434 static void __exit i2c_adap_pxa_exit(void) 1435 { 1436 platform_driver_unregister(&i2c_pxa_driver); 1437 } 1438 1439 MODULE_LICENSE("GPL"); 1440 MODULE_ALIAS("platform:pxa2xx-i2c"); 1441 1442 subsys_initcall(i2c_adap_pxa_init); 1443 module_exit(i2c_adap_pxa_exit); 1444