1 /***************************************************************************\ 2 |* *| 3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| 4 |* *| 5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *| 6 |* international laws. Users and possessors of this source code are *| 7 |* hereby granted a nonexclusive, royalty-free copyright license to *| 8 |* use this code in individual and commercial software. *| 9 |* *| 10 |* Any use of this source code must include, in the user documenta- *| 11 |* tion and internal comments to the code, notices to the end user *| 12 |* as follows: *| 13 |* *| 14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *| 15 |* *| 16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| 17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| 18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| 19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| 20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| 21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| 22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| 23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| 24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| 25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| 26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| 27 |* *| 28 |* U.S. Government End Users. This source code is a "commercial *| 29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| 30 |* consisting of "commercial computer software" and "commercial *| 31 |* computer software documentation," as such terms are used in *| 32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| 33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *| 34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| 35 |* all U.S. Government End Users acquire the source code with only *| 36 |* those rights set forth herein. *| 37 |* *| 38 \***************************************************************************/ 39 40 /* 41 * GPL licensing note -- nVidia is allowing a liberal interpretation of 42 * the documentation restriction above, to merely say that this nVidia's 43 * copyright and disclaimer should be included with all code derived 44 * from this source. -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99 45 */ 46 47 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.33 2002/08/05 20:47:06 mvojkovi Exp $ */ 48 49 #include <linux/kernel.h> 50 #include <linux/pci.h> 51 #include <linux/pci_ids.h> 52 #include "riva_hw.h" 53 #include "riva_tbl.h" 54 #include "nv_type.h" 55 56 /* 57 * This file is an OS-agnostic file used to make RIVA 128 and RIVA TNT 58 * operate identically (except TNT has more memory and better 3D quality. 59 */ 60 static int nv3Busy 61 ( 62 RIVA_HW_INST *chip 63 ) 64 { 65 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || 66 NV_RD32(&chip->PGRAPH[0x000006B0/4], 0) & 0x01); 67 } 68 static int nv4Busy 69 ( 70 RIVA_HW_INST *chip 71 ) 72 { 73 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || 74 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); 75 } 76 static int nv10Busy 77 ( 78 RIVA_HW_INST *chip 79 ) 80 { 81 return ((NV_RD32(&chip->Rop->FifoFree, 0) < chip->FifoEmptyCount) || 82 NV_RD32(&chip->PGRAPH[0x00000700/4], 0) & 0x01); 83 } 84 85 static void vgaLockUnlock 86 ( 87 RIVA_HW_INST *chip, 88 int Lock 89 ) 90 { 91 U008 cr11; 92 VGA_WR08(chip->PCIO, 0x3D4, 0x11); 93 cr11 = VGA_RD08(chip->PCIO, 0x3D5); 94 if(Lock) cr11 |= 0x80; 95 else cr11 &= ~0x80; 96 VGA_WR08(chip->PCIO, 0x3D5, cr11); 97 } 98 static void nv3LockUnlock 99 ( 100 RIVA_HW_INST *chip, 101 int Lock 102 ) 103 { 104 VGA_WR08(chip->PVIO, 0x3C4, 0x06); 105 VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57); 106 vgaLockUnlock(chip, Lock); 107 } 108 static void nv4LockUnlock 109 ( 110 RIVA_HW_INST *chip, 111 int Lock 112 ) 113 { 114 VGA_WR08(chip->PCIO, 0x3D4, 0x1F); 115 VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); 116 vgaLockUnlock(chip, Lock); 117 } 118 119 static int ShowHideCursor 120 ( 121 RIVA_HW_INST *chip, 122 int ShowHide 123 ) 124 { 125 int cursor; 126 cursor = chip->CurrentState->cursor1; 127 chip->CurrentState->cursor1 = (chip->CurrentState->cursor1 & 0xFE) | 128 (ShowHide & 0x01); 129 VGA_WR08(chip->PCIO, 0x3D4, 0x31); 130 VGA_WR08(chip->PCIO, 0x3D5, chip->CurrentState->cursor1); 131 return (cursor & 0x01); 132 } 133 134 /****************************************************************************\ 135 * * 136 * The video arbitration routines calculate some "magic" numbers. Fixes * 137 * the snow seen when accessing the framebuffer without it. * 138 * It just works (I hope). * 139 * * 140 \****************************************************************************/ 141 142 #define DEFAULT_GR_LWM 100 143 #define DEFAULT_VID_LWM 100 144 #define DEFAULT_GR_BURST_SIZE 256 145 #define DEFAULT_VID_BURST_SIZE 128 146 #define VIDEO 0 147 #define GRAPHICS 1 148 #define MPORT 2 149 #define ENGINE 3 150 #define GFIFO_SIZE 320 151 #define GFIFO_SIZE_128 256 152 #define MFIFO_SIZE 120 153 #define VFIFO_SIZE 256 154 155 typedef struct { 156 int gdrain_rate; 157 int vdrain_rate; 158 int mdrain_rate; 159 int gburst_size; 160 int vburst_size; 161 char vid_en; 162 char gr_en; 163 int wcmocc, wcgocc, wcvocc, wcvlwm, wcglwm; 164 int by_gfacc; 165 char vid_only_once; 166 char gr_only_once; 167 char first_vacc; 168 char first_gacc; 169 char first_macc; 170 int vocc; 171 int gocc; 172 int mocc; 173 char cur; 174 char engine_en; 175 char converged; 176 int priority; 177 } nv3_arb_info; 178 typedef struct { 179 int graphics_lwm; 180 int video_lwm; 181 int graphics_burst_size; 182 int video_burst_size; 183 int graphics_hi_priority; 184 int media_hi_priority; 185 int rtl_values; 186 int valid; 187 } nv3_fifo_info; 188 typedef struct { 189 char pix_bpp; 190 char enable_video; 191 char gr_during_vid; 192 char enable_mp; 193 int memory_width; 194 int video_scale; 195 int pclk_khz; 196 int mclk_khz; 197 int mem_page_miss; 198 int mem_latency; 199 char mem_aligned; 200 } nv3_sim_state; 201 typedef struct { 202 int graphics_lwm; 203 int video_lwm; 204 int graphics_burst_size; 205 int video_burst_size; 206 int valid; 207 } nv4_fifo_info; 208 typedef struct { 209 int pclk_khz; 210 int mclk_khz; 211 int nvclk_khz; 212 char mem_page_miss; 213 char mem_latency; 214 int memory_width; 215 char enable_video; 216 char gr_during_vid; 217 char pix_bpp; 218 char mem_aligned; 219 char enable_mp; 220 } nv4_sim_state; 221 typedef struct { 222 int graphics_lwm; 223 int video_lwm; 224 int graphics_burst_size; 225 int video_burst_size; 226 int valid; 227 } nv10_fifo_info; 228 typedef struct { 229 int pclk_khz; 230 int mclk_khz; 231 int nvclk_khz; 232 char mem_page_miss; 233 char mem_latency; 234 u32 memory_type; 235 int memory_width; 236 char enable_video; 237 char gr_during_vid; 238 char pix_bpp; 239 char mem_aligned; 240 char enable_mp; 241 } nv10_sim_state; 242 static int nv3_iterate(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) 243 { 244 int iter = 0; 245 int tmp; 246 int vfsize, mfsize, gfsize; 247 int mburst_size = 32; 248 int mmisses, gmisses, vmisses; 249 int misses; 250 int vlwm, glwm, mlwm; 251 int last, next, cur; 252 int max_gfsize ; 253 long ns; 254 255 vlwm = 0; 256 glwm = 0; 257 mlwm = 0; 258 vfsize = 0; 259 gfsize = 0; 260 cur = ainfo->cur; 261 mmisses = 2; 262 gmisses = 2; 263 vmisses = 2; 264 if (ainfo->gburst_size == 128) max_gfsize = GFIFO_SIZE_128; 265 else max_gfsize = GFIFO_SIZE; 266 max_gfsize = GFIFO_SIZE; 267 while (1) 268 { 269 if (ainfo->vid_en) 270 { 271 if (ainfo->wcvocc > ainfo->vocc) ainfo->wcvocc = ainfo->vocc; 272 if (ainfo->wcvlwm > vlwm) ainfo->wcvlwm = vlwm ; 273 ns = 1000000 * ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; 274 vfsize = ns * ainfo->vdrain_rate / 1000000; 275 vfsize = ainfo->wcvlwm - ainfo->vburst_size + vfsize; 276 } 277 if (state->enable_mp) 278 { 279 if (ainfo->wcmocc > ainfo->mocc) ainfo->wcmocc = ainfo->mocc; 280 } 281 if (ainfo->gr_en) 282 { 283 if (ainfo->wcglwm > glwm) ainfo->wcglwm = glwm ; 284 if (ainfo->wcgocc > ainfo->gocc) ainfo->wcgocc = ainfo->gocc; 285 ns = 1000000 * (ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; 286 gfsize = (ns * (long) ainfo->gdrain_rate)/1000000; 287 gfsize = ainfo->wcglwm - ainfo->gburst_size + gfsize; 288 } 289 mfsize = 0; 290 if (!state->gr_during_vid && ainfo->vid_en) 291 if (ainfo->vid_en && (ainfo->vocc < 0) && !ainfo->vid_only_once) 292 next = VIDEO; 293 else if (ainfo->mocc < 0) 294 next = MPORT; 295 else if (ainfo->gocc< ainfo->by_gfacc) 296 next = GRAPHICS; 297 else return (0); 298 else switch (ainfo->priority) 299 { 300 case VIDEO: 301 if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) 302 next = VIDEO; 303 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) 304 next = GRAPHICS; 305 else if (ainfo->mocc<0) 306 next = MPORT; 307 else return (0); 308 break; 309 case GRAPHICS: 310 if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) 311 next = GRAPHICS; 312 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) 313 next = VIDEO; 314 else if (ainfo->mocc<0) 315 next = MPORT; 316 else return (0); 317 break; 318 default: 319 if (ainfo->mocc<0) 320 next = MPORT; 321 else if (ainfo->gr_en && ainfo->gocc<0 && !ainfo->gr_only_once) 322 next = GRAPHICS; 323 else if (ainfo->vid_en && ainfo->vocc<0 && !ainfo->vid_only_once) 324 next = VIDEO; 325 else return (0); 326 break; 327 } 328 last = cur; 329 cur = next; 330 iter++; 331 switch (cur) 332 { 333 case VIDEO: 334 if (last==cur) misses = 0; 335 else if (ainfo->first_vacc) misses = vmisses; 336 else misses = 1; 337 ainfo->first_vacc = 0; 338 if (last!=cur) 339 { 340 ns = 1000000 * (vmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; 341 vlwm = ns * ainfo->vdrain_rate/ 1000000; 342 vlwm = ainfo->vocc - vlwm; 343 } 344 ns = 1000000*(misses*state->mem_page_miss + ainfo->vburst_size)/(state->memory_width/8)/state->mclk_khz; 345 ainfo->vocc = ainfo->vocc + ainfo->vburst_size - ns*ainfo->vdrain_rate/1000000; 346 ainfo->gocc = ainfo->gocc - ns*ainfo->gdrain_rate/1000000; 347 ainfo->mocc = ainfo->mocc - ns*ainfo->mdrain_rate/1000000; 348 break; 349 case GRAPHICS: 350 if (last==cur) misses = 0; 351 else if (ainfo->first_gacc) misses = gmisses; 352 else misses = 1; 353 ainfo->first_gacc = 0; 354 if (last!=cur) 355 { 356 ns = 1000000*(gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz ; 357 glwm = ns * ainfo->gdrain_rate/1000000; 358 glwm = ainfo->gocc - glwm; 359 } 360 ns = 1000000*(misses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8))/state->mclk_khz; 361 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; 362 ainfo->gocc = ainfo->gocc + ainfo->gburst_size - ns*ainfo->gdrain_rate/1000000; 363 ainfo->mocc = ainfo->mocc + 0 - ns*ainfo->mdrain_rate/1000000; 364 break; 365 default: 366 if (last==cur) misses = 0; 367 else if (ainfo->first_macc) misses = mmisses; 368 else misses = 1; 369 ainfo->first_macc = 0; 370 ns = 1000000*(misses*state->mem_page_miss + mburst_size/(state->memory_width/8))/state->mclk_khz; 371 ainfo->vocc = ainfo->vocc + 0 - ns*ainfo->vdrain_rate/1000000; 372 ainfo->gocc = ainfo->gocc + 0 - ns*ainfo->gdrain_rate/1000000; 373 ainfo->mocc = ainfo->mocc + mburst_size - ns*ainfo->mdrain_rate/1000000; 374 break; 375 } 376 if (iter>100) 377 { 378 ainfo->converged = 0; 379 return (1); 380 } 381 ns = 1000000*ainfo->gburst_size/(state->memory_width/8)/state->mclk_khz; 382 tmp = ns * ainfo->gdrain_rate/1000000; 383 if (abs(ainfo->gburst_size) + ((abs(ainfo->wcglwm) + 16 ) & ~0x7) - tmp > max_gfsize) 384 { 385 ainfo->converged = 0; 386 return (1); 387 } 388 ns = 1000000*ainfo->vburst_size/(state->memory_width/8)/state->mclk_khz; 389 tmp = ns * ainfo->vdrain_rate/1000000; 390 if (abs(ainfo->vburst_size) + (abs(ainfo->wcvlwm + 32) & ~0xf) - tmp> VFIFO_SIZE) 391 { 392 ainfo->converged = 0; 393 return (1); 394 } 395 if (abs(ainfo->gocc) > max_gfsize) 396 { 397 ainfo->converged = 0; 398 return (1); 399 } 400 if (abs(ainfo->vocc) > VFIFO_SIZE) 401 { 402 ainfo->converged = 0; 403 return (1); 404 } 405 if (abs(ainfo->mocc) > MFIFO_SIZE) 406 { 407 ainfo->converged = 0; 408 return (1); 409 } 410 if (abs(vfsize) > VFIFO_SIZE) 411 { 412 ainfo->converged = 0; 413 return (1); 414 } 415 if (abs(gfsize) > max_gfsize) 416 { 417 ainfo->converged = 0; 418 return (1); 419 } 420 if (abs(mfsize) > MFIFO_SIZE) 421 { 422 ainfo->converged = 0; 423 return (1); 424 } 425 } 426 } 427 static char nv3_arb(nv3_fifo_info * res_info, nv3_sim_state * state, nv3_arb_info *ainfo) 428 { 429 long ens, vns, mns, gns; 430 int mmisses, gmisses, vmisses, eburst_size, mburst_size; 431 int refresh_cycle; 432 433 refresh_cycle = 2*(state->mclk_khz/state->pclk_khz) + 5; 434 mmisses = 2; 435 if (state->mem_aligned) gmisses = 2; 436 else gmisses = 3; 437 vmisses = 2; 438 eburst_size = state->memory_width * 1; 439 mburst_size = 32; 440 gns = 1000000 * (gmisses*state->mem_page_miss + state->mem_latency)/state->mclk_khz; 441 ainfo->by_gfacc = gns*ainfo->gdrain_rate/1000000; 442 ainfo->wcmocc = 0; 443 ainfo->wcgocc = 0; 444 ainfo->wcvocc = 0; 445 ainfo->wcvlwm = 0; 446 ainfo->wcglwm = 0; 447 ainfo->engine_en = 1; 448 ainfo->converged = 1; 449 if (ainfo->engine_en) 450 { 451 ens = 1000000*(state->mem_page_miss + eburst_size/(state->memory_width/8) +refresh_cycle)/state->mclk_khz; 452 ainfo->mocc = state->enable_mp ? 0-ens*ainfo->mdrain_rate/1000000 : 0; 453 ainfo->vocc = ainfo->vid_en ? 0-ens*ainfo->vdrain_rate/1000000 : 0; 454 ainfo->gocc = ainfo->gr_en ? 0-ens*ainfo->gdrain_rate/1000000 : 0; 455 ainfo->cur = ENGINE; 456 ainfo->first_vacc = 1; 457 ainfo->first_gacc = 1; 458 ainfo->first_macc = 1; 459 nv3_iterate(res_info, state,ainfo); 460 } 461 if (state->enable_mp) 462 { 463 mns = 1000000 * (mmisses*state->mem_page_miss + mburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; 464 ainfo->mocc = state->enable_mp ? 0 : mburst_size - mns*ainfo->mdrain_rate/1000000; 465 ainfo->vocc = ainfo->vid_en ? 0 : 0- mns*ainfo->vdrain_rate/1000000; 466 ainfo->gocc = ainfo->gr_en ? 0: 0- mns*ainfo->gdrain_rate/1000000; 467 ainfo->cur = MPORT; 468 ainfo->first_vacc = 1; 469 ainfo->first_gacc = 1; 470 ainfo->first_macc = 0; 471 nv3_iterate(res_info, state,ainfo); 472 } 473 if (ainfo->gr_en) 474 { 475 ainfo->first_vacc = 1; 476 ainfo->first_gacc = 0; 477 ainfo->first_macc = 1; 478 gns = 1000000*(gmisses*state->mem_page_miss + ainfo->gburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; 479 ainfo->gocc = ainfo->gburst_size - gns*ainfo->gdrain_rate/1000000; 480 ainfo->vocc = ainfo->vid_en? 0-gns*ainfo->vdrain_rate/1000000 : 0; 481 ainfo->mocc = state->enable_mp ? 0-gns*ainfo->mdrain_rate/1000000: 0; 482 ainfo->cur = GRAPHICS; 483 nv3_iterate(res_info, state,ainfo); 484 } 485 if (ainfo->vid_en) 486 { 487 ainfo->first_vacc = 0; 488 ainfo->first_gacc = 1; 489 ainfo->first_macc = 1; 490 vns = 1000000*(vmisses*state->mem_page_miss + ainfo->vburst_size/(state->memory_width/8) + refresh_cycle)/state->mclk_khz; 491 ainfo->vocc = ainfo->vburst_size - vns*ainfo->vdrain_rate/1000000; 492 ainfo->gocc = ainfo->gr_en? (0-vns*ainfo->gdrain_rate/1000000) : 0; 493 ainfo->mocc = state->enable_mp? 0-vns*ainfo->mdrain_rate/1000000 :0 ; 494 ainfo->cur = VIDEO; 495 nv3_iterate(res_info, state, ainfo); 496 } 497 if (ainfo->converged) 498 { 499 res_info->graphics_lwm = (int)abs(ainfo->wcglwm) + 16; 500 res_info->video_lwm = (int)abs(ainfo->wcvlwm) + 32; 501 res_info->graphics_burst_size = ainfo->gburst_size; 502 res_info->video_burst_size = ainfo->vburst_size; 503 res_info->graphics_hi_priority = (ainfo->priority == GRAPHICS); 504 res_info->media_hi_priority = (ainfo->priority == MPORT); 505 if (res_info->video_lwm > 160) 506 { 507 res_info->graphics_lwm = 256; 508 res_info->video_lwm = 128; 509 res_info->graphics_burst_size = 64; 510 res_info->video_burst_size = 64; 511 res_info->graphics_hi_priority = 0; 512 res_info->media_hi_priority = 0; 513 ainfo->converged = 0; 514 return (0); 515 } 516 if (res_info->video_lwm > 128) 517 { 518 res_info->video_lwm = 128; 519 } 520 return (1); 521 } 522 else 523 { 524 res_info->graphics_lwm = 256; 525 res_info->video_lwm = 128; 526 res_info->graphics_burst_size = 64; 527 res_info->video_burst_size = 64; 528 res_info->graphics_hi_priority = 0; 529 res_info->media_hi_priority = 0; 530 return (0); 531 } 532 } 533 static char nv3_get_param(nv3_fifo_info *res_info, nv3_sim_state * state, nv3_arb_info *ainfo) 534 { 535 int done, g,v, p; 536 537 done = 0; 538 for (p=0; p < 2; p++) 539 { 540 for (g=128 ; g > 32; g= g>> 1) 541 { 542 for (v=128; v >=32; v = v>> 1) 543 { 544 ainfo->priority = p; 545 ainfo->gburst_size = g; 546 ainfo->vburst_size = v; 547 done = nv3_arb(res_info, state,ainfo); 548 if (done && (g==128)) 549 if ((res_info->graphics_lwm + g) > 256) 550 done = 0; 551 if (done) 552 goto Done; 553 } 554 } 555 } 556 557 Done: 558 return done; 559 } 560 static void nv3CalcArbitration 561 ( 562 nv3_fifo_info * res_info, 563 nv3_sim_state * state 564 ) 565 { 566 nv3_fifo_info save_info; 567 nv3_arb_info ainfo; 568 char res_gr, res_vid; 569 570 ainfo.gr_en = 1; 571 ainfo.vid_en = state->enable_video; 572 ainfo.vid_only_once = 0; 573 ainfo.gr_only_once = 0; 574 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); 575 ainfo.vdrain_rate = (int) state->pclk_khz * 2; 576 if (state->video_scale != 0) 577 ainfo.vdrain_rate = ainfo.vdrain_rate/state->video_scale; 578 ainfo.mdrain_rate = 33000; 579 res_info->rtl_values = 0; 580 if (!state->gr_during_vid && state->enable_video) 581 { 582 ainfo.gr_only_once = 1; 583 ainfo.gr_en = 1; 584 ainfo.gdrain_rate = 0; 585 res_vid = nv3_get_param(res_info, state, &ainfo); 586 res_vid = ainfo.converged; 587 save_info.video_lwm = res_info->video_lwm; 588 save_info.video_burst_size = res_info->video_burst_size; 589 ainfo.vid_en = 1; 590 ainfo.vid_only_once = 1; 591 ainfo.gr_en = 1; 592 ainfo.gdrain_rate = (int) state->pclk_khz * (state->pix_bpp/8); 593 ainfo.vdrain_rate = 0; 594 res_gr = nv3_get_param(res_info, state, &ainfo); 595 res_gr = ainfo.converged; 596 res_info->video_lwm = save_info.video_lwm; 597 res_info->video_burst_size = save_info.video_burst_size; 598 res_info->valid = res_gr & res_vid; 599 } 600 else 601 { 602 if (!ainfo.gr_en) ainfo.gdrain_rate = 0; 603 if (!ainfo.vid_en) ainfo.vdrain_rate = 0; 604 res_gr = nv3_get_param(res_info, state, &ainfo); 605 res_info->valid = ainfo.converged; 606 } 607 } 608 static void nv3UpdateArbitrationSettings 609 ( 610 unsigned VClk, 611 unsigned pixelDepth, 612 unsigned *burst, 613 unsigned *lwm, 614 RIVA_HW_INST *chip 615 ) 616 { 617 nv3_fifo_info fifo_data; 618 nv3_sim_state sim_data; 619 unsigned int M, N, P, pll, MClk; 620 621 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 622 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 623 MClk = (N * chip->CrystalFreqKHz / M) >> P; 624 sim_data.pix_bpp = (char)pixelDepth; 625 sim_data.enable_video = 0; 626 sim_data.enable_mp = 0; 627 sim_data.video_scale = 1; 628 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? 629 128 : 64; 630 sim_data.memory_width = 128; 631 632 sim_data.mem_latency = 9; 633 sim_data.mem_aligned = 1; 634 sim_data.mem_page_miss = 11; 635 sim_data.gr_during_vid = 0; 636 sim_data.pclk_khz = VClk; 637 sim_data.mclk_khz = MClk; 638 nv3CalcArbitration(&fifo_data, &sim_data); 639 if (fifo_data.valid) 640 { 641 int b = fifo_data.graphics_burst_size >> 4; 642 *burst = 0; 643 while (b >>= 1) 644 (*burst)++; 645 *lwm = fifo_data.graphics_lwm >> 3; 646 } 647 else 648 { 649 *lwm = 0x24; 650 *burst = 0x2; 651 } 652 } 653 static void nv4CalcArbitration 654 ( 655 nv4_fifo_info *fifo, 656 nv4_sim_state *arb 657 ) 658 { 659 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; 660 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; 661 int found, mclk_extra, mclk_loop, cbs, m1, p1; 662 int mclk_freq, pclk_freq, nvclk_freq, mp_enable; 663 int us_m, us_n, us_p, video_drain_rate, crtc_drain_rate; 664 int vpm_us, us_video, vlwm, video_fill_us, cpm_us, us_crt,clwm; 665 int craw, vraw; 666 667 fifo->valid = 1; 668 pclk_freq = arb->pclk_khz; 669 mclk_freq = arb->mclk_khz; 670 nvclk_freq = arb->nvclk_khz; 671 pagemiss = arb->mem_page_miss; 672 cas = arb->mem_latency; 673 width = arb->memory_width >> 6; 674 video_enable = arb->enable_video; 675 color_key_enable = arb->gr_during_vid; 676 bpp = arb->pix_bpp; 677 align = arb->mem_aligned; 678 mp_enable = arb->enable_mp; 679 clwm = 0; 680 vlwm = 0; 681 cbs = 128; 682 pclks = 2; 683 nvclks = 2; 684 nvclks += 2; 685 nvclks += 1; 686 mclks = 5; 687 mclks += 3; 688 mclks += 1; 689 mclks += cas; 690 mclks += 1; 691 mclks += 1; 692 mclks += 1; 693 mclks += 1; 694 mclk_extra = 3; 695 nvclks += 2; 696 nvclks += 1; 697 nvclks += 1; 698 nvclks += 1; 699 if (mp_enable) 700 mclks+=4; 701 nvclks += 0; 702 pclks += 0; 703 found = 0; 704 vbs = 0; 705 while (found != 1) 706 { 707 fifo->valid = 1; 708 found = 1; 709 mclk_loop = mclks+mclk_extra; 710 us_m = mclk_loop *1000*1000 / mclk_freq; 711 us_n = nvclks*1000*1000 / nvclk_freq; 712 us_p = nvclks*1000*1000 / pclk_freq; 713 if (video_enable) 714 { 715 video_drain_rate = pclk_freq * 2; 716 crtc_drain_rate = pclk_freq * bpp/8; 717 vpagemiss = 2; 718 vpagemiss += 1; 719 crtpagemiss = 2; 720 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; 721 if (nvclk_freq * 2 > mclk_freq * width) 722 video_fill_us = cbs*1000*1000 / 16 / nvclk_freq ; 723 else 724 video_fill_us = cbs*1000*1000 / (8 * width) / mclk_freq; 725 us_video = vpm_us + us_m + us_n + us_p + video_fill_us; 726 vlwm = us_video * video_drain_rate/(1000*1000); 727 vlwm++; 728 vbs = 128; 729 if (vlwm > 128) vbs = 64; 730 if (vlwm > (256-64)) vbs = 32; 731 if (nvclk_freq * 2 > mclk_freq * width) 732 video_fill_us = vbs *1000*1000/ 16 / nvclk_freq ; 733 else 734 video_fill_us = vbs*1000*1000 / (8 * width) / mclk_freq; 735 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 736 us_crt = 737 us_video 738 +video_fill_us 739 +cpm_us 740 +us_m + us_n +us_p 741 ; 742 clwm = us_crt * crtc_drain_rate/(1000*1000); 743 clwm++; 744 } 745 else 746 { 747 crtc_drain_rate = pclk_freq * bpp/8; 748 crtpagemiss = 2; 749 crtpagemiss += 1; 750 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 751 us_crt = cpm_us + us_m + us_n + us_p ; 752 clwm = us_crt * crtc_drain_rate/(1000*1000); 753 clwm++; 754 } 755 m1 = clwm + cbs - 512; 756 p1 = m1 * pclk_freq / mclk_freq; 757 p1 = p1 * bpp / 8; 758 if ((p1 < m1) && (m1 > 0)) 759 { 760 fifo->valid = 0; 761 found = 0; 762 if (mclk_extra ==0) found = 1; 763 mclk_extra--; 764 } 765 else if (video_enable) 766 { 767 if ((clwm > 511) || (vlwm > 255)) 768 { 769 fifo->valid = 0; 770 found = 0; 771 if (mclk_extra ==0) found = 1; 772 mclk_extra--; 773 } 774 } 775 else 776 { 777 if (clwm > 519) 778 { 779 fifo->valid = 0; 780 found = 0; 781 if (mclk_extra ==0) found = 1; 782 mclk_extra--; 783 } 784 } 785 craw = clwm; 786 vraw = vlwm; 787 if (clwm < 384) clwm = 384; 788 if (vlwm < 128) vlwm = 128; 789 data = (int)(clwm); 790 fifo->graphics_lwm = data; 791 fifo->graphics_burst_size = 128; 792 data = (int)((vlwm+15)); 793 fifo->video_lwm = data; 794 fifo->video_burst_size = vbs; 795 } 796 } 797 static void nv4UpdateArbitrationSettings 798 ( 799 unsigned VClk, 800 unsigned pixelDepth, 801 unsigned *burst, 802 unsigned *lwm, 803 RIVA_HW_INST *chip 804 ) 805 { 806 nv4_fifo_info fifo_data; 807 nv4_sim_state sim_data; 808 unsigned int M, N, P, pll, MClk, NVClk, cfg1; 809 810 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 811 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 812 MClk = (N * chip->CrystalFreqKHz / M) >> P; 813 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); 814 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 815 NVClk = (N * chip->CrystalFreqKHz / M) >> P; 816 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); 817 sim_data.pix_bpp = (char)pixelDepth; 818 sim_data.enable_video = 0; 819 sim_data.enable_mp = 0; 820 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? 821 128 : 64; 822 sim_data.mem_latency = (char)cfg1 & 0x0F; 823 sim_data.mem_aligned = 1; 824 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); 825 sim_data.gr_during_vid = 0; 826 sim_data.pclk_khz = VClk; 827 sim_data.mclk_khz = MClk; 828 sim_data.nvclk_khz = NVClk; 829 nv4CalcArbitration(&fifo_data, &sim_data); 830 if (fifo_data.valid) 831 { 832 int b = fifo_data.graphics_burst_size >> 4; 833 *burst = 0; 834 while (b >>= 1) 835 (*burst)++; 836 *lwm = fifo_data.graphics_lwm >> 3; 837 } 838 } 839 static void nv10CalcArbitration 840 ( 841 nv10_fifo_info *fifo, 842 nv10_sim_state *arb 843 ) 844 { 845 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; 846 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; 847 int nvclk_fill, us_extra; 848 int found, mclk_extra, mclk_loop, cbs, m1; 849 int mclk_freq, pclk_freq, nvclk_freq, mp_enable; 850 int us_m, us_m_min, us_n, us_p, video_drain_rate, crtc_drain_rate; 851 int vus_m, vus_n, vus_p; 852 int vpm_us, us_video, vlwm, cpm_us, us_crt,clwm; 853 int clwm_rnd_down; 854 int craw, m2us, us_pipe, us_pipe_min, vus_pipe, p1clk, p2; 855 int pclks_2_top_fifo, min_mclk_extra; 856 int us_min_mclk_extra; 857 858 fifo->valid = 1; 859 pclk_freq = arb->pclk_khz; /* freq in KHz */ 860 mclk_freq = arb->mclk_khz; 861 nvclk_freq = arb->nvclk_khz; 862 pagemiss = arb->mem_page_miss; 863 cas = arb->mem_latency; 864 width = arb->memory_width/64; 865 video_enable = arb->enable_video; 866 color_key_enable = arb->gr_during_vid; 867 bpp = arb->pix_bpp; 868 align = arb->mem_aligned; 869 mp_enable = arb->enable_mp; 870 clwm = 0; 871 vlwm = 1024; 872 873 cbs = 512; 874 vbs = 512; 875 876 pclks = 4; /* lwm detect. */ 877 878 nvclks = 3; /* lwm -> sync. */ 879 nvclks += 2; /* fbi bus cycles (1 req + 1 busy) */ 880 881 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */ 882 883 mclks += 1; /* arb_hp_req */ 884 mclks += 5; /* ap_hp_req tiling pipeline */ 885 886 mclks += 2; /* tc_req latency fifo */ 887 mclks += 2; /* fb_cas_n_ memory request to fbio block */ 888 mclks += 7; /* sm_d_rdv data returned from fbio block */ 889 890 /* fb.rd.d.Put_gc need to accumulate 256 bits for read */ 891 if (arb->memory_type == 0) 892 if (arb->memory_width == 64) /* 64 bit bus */ 893 mclks += 4; 894 else 895 mclks += 2; 896 else 897 if (arb->memory_width == 64) /* 64 bit bus */ 898 mclks += 2; 899 else 900 mclks += 1; 901 902 if ((!video_enable) && (arb->memory_width == 128)) 903 { 904 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */ 905 min_mclk_extra = 17; 906 } 907 else 908 { 909 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */ 910 /* mclk_extra = 4; */ /* Margin of error */ 911 min_mclk_extra = 18; 912 } 913 914 nvclks += 1; /* 2 edge sync. may be very close to edge so just put one. */ 915 nvclks += 1; /* fbi_d_rdv_n */ 916 nvclks += 1; /* Fbi_d_rdata */ 917 nvclks += 1; /* crtfifo load */ 918 919 if(mp_enable) 920 mclks+=4; /* Mp can get in with a burst of 8. */ 921 /* Extra clocks determined by heuristics */ 922 923 nvclks += 0; 924 pclks += 0; 925 found = 0; 926 while(found != 1) { 927 fifo->valid = 1; 928 found = 1; 929 mclk_loop = mclks+mclk_extra; 930 us_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ 931 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */ 932 us_min_mclk_extra = min_mclk_extra *1000*1000 / mclk_freq; 933 us_n = nvclks*1000*1000 / nvclk_freq;/* nvclk latency in us */ 934 us_p = pclks*1000*1000 / pclk_freq;/* nvclk latency in us */ 935 us_pipe = us_m + us_n + us_p; 936 us_pipe_min = us_m_min + us_n + us_p; 937 us_extra = 0; 938 939 vus_m = mclk_loop *1000*1000 / mclk_freq; /* Mclk latency in us */ 940 vus_n = (4)*1000*1000 / nvclk_freq;/* nvclk latency in us */ 941 vus_p = 0*1000*1000 / pclk_freq;/* pclk latency in us */ 942 vus_pipe = vus_m + vus_n + vus_p; 943 944 if(video_enable) { 945 video_drain_rate = pclk_freq * 4; /* MB/s */ 946 crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */ 947 948 vpagemiss = 1; /* self generating page miss */ 949 vpagemiss += 1; /* One higher priority before */ 950 951 crtpagemiss = 2; /* self generating page miss */ 952 if(mp_enable) 953 crtpagemiss += 1; /* if MA0 conflict */ 954 955 vpm_us = (vpagemiss * pagemiss)*1000*1000/mclk_freq; 956 957 us_video = vpm_us + vus_m; /* Video has separate read return path */ 958 959 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 960 us_crt = 961 us_video /* Wait for video */ 962 +cpm_us /* CRT Page miss */ 963 +us_m + us_n +us_p /* other latency */ 964 ; 965 966 clwm = us_crt * crtc_drain_rate/(1000*1000); 967 clwm++; /* fixed point <= float_point - 1. Fixes that */ 968 } else { 969 crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */ 970 971 crtpagemiss = 1; /* self generating page miss */ 972 crtpagemiss += 1; /* MA0 page miss */ 973 if(mp_enable) 974 crtpagemiss += 1; /* if MA0 conflict */ 975 cpm_us = crtpagemiss * pagemiss *1000*1000/ mclk_freq; 976 us_crt = cpm_us + us_m + us_n + us_p ; 977 clwm = us_crt * crtc_drain_rate/(1000*1000); 978 clwm++; /* fixed point <= float_point - 1. Fixes that */ 979 980 /* 981 // 982 // Another concern, only for high pclks so don't do this 983 // with video: 984 // What happens if the latency to fetch the cbs is so large that 985 // fifo empties. In that case we need to have an alternate clwm value 986 // based off the total burst fetch 987 // 988 us_crt = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; 989 us_crt = us_crt + us_m + us_n + us_p + (4 * 1000 * 1000)/mclk_freq; 990 clwm_mt = us_crt * crtc_drain_rate/(1000*1000); 991 clwm_mt ++; 992 if(clwm_mt > clwm) 993 clwm = clwm_mt; 994 */ 995 /* Finally, a heuristic check when width == 64 bits */ 996 if(width == 1){ 997 nvclk_fill = nvclk_freq * 8; 998 if(crtc_drain_rate * 100 >= nvclk_fill * 102) 999 clwm = 0xfff; /*Large number to fail */ 1000 1001 else if(crtc_drain_rate * 100 >= nvclk_fill * 98) { 1002 clwm = 1024; 1003 cbs = 512; 1004 us_extra = (cbs * 1000 * 1000)/ (8*width)/mclk_freq ; 1005 } 1006 } 1007 } 1008 1009 1010 /* 1011 Overfill check: 1012 1013 */ 1014 1015 clwm_rnd_down = ((int)clwm/8)*8; 1016 if (clwm_rnd_down < clwm) 1017 clwm += 8; 1018 1019 m1 = clwm + cbs - 1024; /* Amount of overfill */ 1020 m2us = us_pipe_min + us_min_mclk_extra; 1021 pclks_2_top_fifo = (1024-clwm)/(8*width); 1022 1023 /* pclk cycles to drain */ 1024 p1clk = m2us * pclk_freq/(1000*1000); 1025 p2 = p1clk * bpp / 8; /* bytes drained. */ 1026 1027 if((p2 < m1) && (m1 > 0)) { 1028 fifo->valid = 0; 1029 found = 0; 1030 if(min_mclk_extra == 0) { 1031 if(cbs <= 32) { 1032 found = 1; /* Can't adjust anymore! */ 1033 } else { 1034 cbs = cbs/2; /* reduce the burst size */ 1035 } 1036 } else { 1037 min_mclk_extra--; 1038 } 1039 } else { 1040 if (clwm > 1023){ /* Have some margin */ 1041 fifo->valid = 0; 1042 found = 0; 1043 if(min_mclk_extra == 0) 1044 found = 1; /* Can't adjust anymore! */ 1045 else 1046 min_mclk_extra--; 1047 } 1048 } 1049 craw = clwm; 1050 1051 if(clwm < (1024-cbs+8)) clwm = 1024-cbs+8; 1052 data = (int)(clwm); 1053 /* printf("CRT LWM: %f bytes, prog: 0x%x, bs: 256\n", clwm, data ); */ 1054 fifo->graphics_lwm = data; fifo->graphics_burst_size = cbs; 1055 1056 /* printf("VID LWM: %f bytes, prog: 0x%x, bs: %d\n, ", vlwm, data, vbs ); */ 1057 fifo->video_lwm = 1024; fifo->video_burst_size = 512; 1058 } 1059 } 1060 static void nv10UpdateArbitrationSettings 1061 ( 1062 unsigned VClk, 1063 unsigned pixelDepth, 1064 unsigned *burst, 1065 unsigned *lwm, 1066 RIVA_HW_INST *chip 1067 ) 1068 { 1069 nv10_fifo_info fifo_data; 1070 nv10_sim_state sim_data; 1071 unsigned int M, N, P, pll, MClk, NVClk, cfg1; 1072 1073 pll = NV_RD32(&chip->PRAMDAC0[0x00000504/4], 0); 1074 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 1075 MClk = (N * chip->CrystalFreqKHz / M) >> P; 1076 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); 1077 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 1078 NVClk = (N * chip->CrystalFreqKHz / M) >> P; 1079 cfg1 = NV_RD32(&chip->PFB[0x00000204/4], 0); 1080 sim_data.pix_bpp = (char)pixelDepth; 1081 sim_data.enable_video = 0; 1082 sim_data.enable_mp = 0; 1083 sim_data.memory_type = (NV_RD32(&chip->PFB[0x00000200/4], 0) & 0x01) ? 1084 1 : 0; 1085 sim_data.memory_width = (NV_RD32(&chip->PEXTDEV[0x00000000/4], 0) & 0x10) ? 1086 128 : 64; 1087 sim_data.mem_latency = (char)cfg1 & 0x0F; 1088 sim_data.mem_aligned = 1; 1089 sim_data.mem_page_miss = (char)(((cfg1 >> 4) &0x0F) + ((cfg1 >> 31) & 0x01)); 1090 sim_data.gr_during_vid = 0; 1091 sim_data.pclk_khz = VClk; 1092 sim_data.mclk_khz = MClk; 1093 sim_data.nvclk_khz = NVClk; 1094 nv10CalcArbitration(&fifo_data, &sim_data); 1095 if (fifo_data.valid) 1096 { 1097 int b = fifo_data.graphics_burst_size >> 4; 1098 *burst = 0; 1099 while (b >>= 1) 1100 (*burst)++; 1101 *lwm = fifo_data.graphics_lwm >> 3; 1102 } 1103 } 1104 1105 static void nForceUpdateArbitrationSettings 1106 ( 1107 unsigned VClk, 1108 unsigned pixelDepth, 1109 unsigned *burst, 1110 unsigned *lwm, 1111 RIVA_HW_INST *chip, 1112 struct pci_dev *pdev 1113 ) 1114 { 1115 nv10_fifo_info fifo_data; 1116 nv10_sim_state sim_data; 1117 unsigned int M, N, P, pll, MClk, NVClk; 1118 unsigned int uMClkPostDiv; 1119 struct pci_dev *dev; 1120 int domain = pci_domain_nr(pdev->bus); 1121 1122 dev = pci_get_domain_bus_and_slot(domain, 0, 3); 1123 pci_read_config_dword(dev, 0x6C, &uMClkPostDiv); 1124 pci_dev_put(dev); 1125 uMClkPostDiv = (uMClkPostDiv >> 8) & 0xf; 1126 1127 if(!uMClkPostDiv) uMClkPostDiv = 4; 1128 MClk = 400000 / uMClkPostDiv; 1129 1130 pll = NV_RD32(&chip->PRAMDAC0[0x00000500/4], 0); 1131 M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; 1132 NVClk = (N * chip->CrystalFreqKHz / M) >> P; 1133 sim_data.pix_bpp = (char)pixelDepth; 1134 sim_data.enable_video = 0; 1135 sim_data.enable_mp = 0; 1136 1137 dev = pci_get_domain_bus_and_slot(domain, 0, 1); 1138 pci_read_config_dword(dev, 0x7C, &sim_data.memory_type); 1139 pci_dev_put(dev); 1140 sim_data.memory_type = (sim_data.memory_type >> 12) & 1; 1141 1142 sim_data.memory_width = 64; 1143 sim_data.mem_latency = 3; 1144 sim_data.mem_aligned = 1; 1145 sim_data.mem_page_miss = 10; 1146 sim_data.gr_during_vid = 0; 1147 sim_data.pclk_khz = VClk; 1148 sim_data.mclk_khz = MClk; 1149 sim_data.nvclk_khz = NVClk; 1150 nv10CalcArbitration(&fifo_data, &sim_data); 1151 if (fifo_data.valid) 1152 { 1153 int b = fifo_data.graphics_burst_size >> 4; 1154 *burst = 0; 1155 while (b >>= 1) 1156 (*burst)++; 1157 *lwm = fifo_data.graphics_lwm >> 3; 1158 } 1159 } 1160 1161 /****************************************************************************\ 1162 * * 1163 * RIVA Mode State Routines * 1164 * * 1165 \****************************************************************************/ 1166 1167 /* 1168 * Calculate the Video Clock parameters for the PLL. 1169 */ 1170 static int CalcVClock 1171 ( 1172 int clockIn, 1173 int *clockOut, 1174 int *mOut, 1175 int *nOut, 1176 int *pOut, 1177 RIVA_HW_INST *chip 1178 ) 1179 { 1180 unsigned lowM, highM, highP; 1181 unsigned DeltaNew, DeltaOld; 1182 unsigned VClk, Freq; 1183 unsigned M, N, P; 1184 1185 DeltaOld = 0xFFFFFFFF; 1186 1187 VClk = (unsigned)clockIn; 1188 1189 if (chip->CrystalFreqKHz == 13500) 1190 { 1191 lowM = 7; 1192 highM = 13 - (chip->Architecture == NV_ARCH_03); 1193 } 1194 else 1195 { 1196 lowM = 8; 1197 highM = 14 - (chip->Architecture == NV_ARCH_03); 1198 } 1199 1200 highP = 4 - (chip->Architecture == NV_ARCH_03); 1201 for (P = 0; P <= highP; P ++) 1202 { 1203 Freq = VClk << P; 1204 if ((Freq >= 128000) && (Freq <= chip->MaxVClockFreqKHz)) 1205 { 1206 for (M = lowM; M <= highM; M++) 1207 { 1208 N = (VClk << P) * M / chip->CrystalFreqKHz; 1209 if(N <= 255) { 1210 Freq = (chip->CrystalFreqKHz * N / M) >> P; 1211 if (Freq > VClk) 1212 DeltaNew = Freq - VClk; 1213 else 1214 DeltaNew = VClk - Freq; 1215 if (DeltaNew < DeltaOld) 1216 { 1217 *mOut = M; 1218 *nOut = N; 1219 *pOut = P; 1220 *clockOut = Freq; 1221 DeltaOld = DeltaNew; 1222 } 1223 } 1224 } 1225 } 1226 } 1227 1228 /* non-zero: M/N/P/clock values assigned. zero: error (not set) */ 1229 return (DeltaOld != 0xFFFFFFFF); 1230 } 1231 /* 1232 * Calculate extended mode parameters (SVGA) and save in a 1233 * mode state structure. 1234 */ 1235 int CalcStateExt 1236 ( 1237 RIVA_HW_INST *chip, 1238 RIVA_HW_STATE *state, 1239 struct pci_dev *pdev, 1240 int bpp, 1241 int width, 1242 int hDisplaySize, 1243 int height, 1244 int dotClock 1245 ) 1246 { 1247 int pixelDepth; 1248 int VClk, m, n, p; 1249 1250 /* 1251 * Save mode parameters. 1252 */ 1253 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ 1254 state->width = width; 1255 state->height = height; 1256 /* 1257 * Extended RIVA registers. 1258 */ 1259 pixelDepth = (bpp + 1)/8; 1260 if (!CalcVClock(dotClock, &VClk, &m, &n, &p, chip)) 1261 return -EINVAL; 1262 1263 switch (chip->Architecture) 1264 { 1265 case NV_ARCH_03: 1266 nv3UpdateArbitrationSettings(VClk, 1267 pixelDepth * 8, 1268 &(state->arbitration0), 1269 &(state->arbitration1), 1270 chip); 1271 state->cursor0 = 0x00; 1272 state->cursor1 = 0x78; 1273 state->cursor2 = 0x00000000; 1274 state->pllsel = 0x10010100; 1275 state->config = ((width + 31)/32) 1276 | (((pixelDepth > 2) ? 3 : pixelDepth) << 8) 1277 | 0x1000; 1278 state->general = 0x00100100; 1279 state->repaint1 = hDisplaySize < 1280 ? 0x06 : 0x02; 1280 break; 1281 case NV_ARCH_04: 1282 nv4UpdateArbitrationSettings(VClk, 1283 pixelDepth * 8, 1284 &(state->arbitration0), 1285 &(state->arbitration1), 1286 chip); 1287 state->cursor0 = 0x00; 1288 state->cursor1 = 0xFC; 1289 state->cursor2 = 0x00000000; 1290 state->pllsel = 0x10000700; 1291 state->config = 0x00001114; 1292 state->general = bpp == 16 ? 0x00101100 : 0x00100100; 1293 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; 1294 break; 1295 case NV_ARCH_10: 1296 case NV_ARCH_20: 1297 case NV_ARCH_30: 1298 if((chip->Chipset == NV_CHIP_IGEFORCE2) || 1299 (chip->Chipset == NV_CHIP_0x01F0)) 1300 { 1301 nForceUpdateArbitrationSettings(VClk, 1302 pixelDepth * 8, 1303 &(state->arbitration0), 1304 &(state->arbitration1), 1305 chip, pdev); 1306 } else { 1307 nv10UpdateArbitrationSettings(VClk, 1308 pixelDepth * 8, 1309 &(state->arbitration0), 1310 &(state->arbitration1), 1311 chip); 1312 } 1313 state->cursor0 = 0x80 | (chip->CursorStart >> 17); 1314 state->cursor1 = (chip->CursorStart >> 11) << 2; 1315 state->cursor2 = chip->CursorStart >> 24; 1316 state->pllsel = 0x10000700; 1317 state->config = NV_RD32(&chip->PFB[0x00000200/4], 0); 1318 state->general = bpp == 16 ? 0x00101100 : 0x00100100; 1319 state->repaint1 = hDisplaySize < 1280 ? 0x04 : 0x00; 1320 break; 1321 } 1322 1323 /* Paul Richards: below if block borks things in kernel for some reason */ 1324 /* Tony: Below is needed to set hardware in DirectColor */ 1325 if((bpp != 8) && (chip->Architecture != NV_ARCH_03)) 1326 state->general |= 0x00000030; 1327 1328 state->vpll = (p << 16) | (n << 8) | m; 1329 state->repaint0 = (((width/8)*pixelDepth) & 0x700) >> 3; 1330 state->pixel = pixelDepth > 2 ? 3 : pixelDepth; 1331 state->offset0 = 1332 state->offset1 = 1333 state->offset2 = 1334 state->offset3 = 0; 1335 state->pitch0 = 1336 state->pitch1 = 1337 state->pitch2 = 1338 state->pitch3 = pixelDepth * width; 1339 1340 return 0; 1341 } 1342 /* 1343 * Load fixed function state and pre-calculated/stored state. 1344 */ 1345 #define LOAD_FIXED_STATE(tbl,dev) \ 1346 for (i = 0; i < sizeof(tbl##Table##dev)/8; i++) \ 1347 NV_WR32(&chip->dev[tbl##Table##dev[i][0]], 0, tbl##Table##dev[i][1]) 1348 #define LOAD_FIXED_STATE_8BPP(tbl,dev) \ 1349 for (i = 0; i < sizeof(tbl##Table##dev##_8BPP)/8; i++) \ 1350 NV_WR32(&chip->dev[tbl##Table##dev##_8BPP[i][0]], 0, tbl##Table##dev##_8BPP[i][1]) 1351 #define LOAD_FIXED_STATE_15BPP(tbl,dev) \ 1352 for (i = 0; i < sizeof(tbl##Table##dev##_15BPP)/8; i++) \ 1353 NV_WR32(&chip->dev[tbl##Table##dev##_15BPP[i][0]], 0, tbl##Table##dev##_15BPP[i][1]) 1354 #define LOAD_FIXED_STATE_16BPP(tbl,dev) \ 1355 for (i = 0; i < sizeof(tbl##Table##dev##_16BPP)/8; i++) \ 1356 NV_WR32(&chip->dev[tbl##Table##dev##_16BPP[i][0]], 0, tbl##Table##dev##_16BPP[i][1]) 1357 #define LOAD_FIXED_STATE_32BPP(tbl,dev) \ 1358 for (i = 0; i < sizeof(tbl##Table##dev##_32BPP)/8; i++) \ 1359 NV_WR32(&chip->dev[tbl##Table##dev##_32BPP[i][0]], 0, tbl##Table##dev##_32BPP[i][1]) 1360 1361 static void UpdateFifoState 1362 ( 1363 RIVA_HW_INST *chip 1364 ) 1365 { 1366 int i; 1367 1368 switch (chip->Architecture) 1369 { 1370 case NV_ARCH_04: 1371 LOAD_FIXED_STATE(nv4,FIFO); 1372 chip->Tri03 = NULL; 1373 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); 1374 break; 1375 case NV_ARCH_10: 1376 case NV_ARCH_20: 1377 case NV_ARCH_30: 1378 /* 1379 * Initialize state for the RivaTriangle3D05 routines. 1380 */ 1381 LOAD_FIXED_STATE(nv10tri05,PGRAPH); 1382 LOAD_FIXED_STATE(nv10,FIFO); 1383 chip->Tri03 = NULL; 1384 chip->Tri05 = (RivaTexturedTriangle05 __iomem *)&(chip->FIFO[0x0000E000/4]); 1385 break; 1386 } 1387 } 1388 static void LoadStateExt 1389 ( 1390 RIVA_HW_INST *chip, 1391 RIVA_HW_STATE *state 1392 ) 1393 { 1394 int i; 1395 1396 /* 1397 * Load HW fixed function state. 1398 */ 1399 LOAD_FIXED_STATE(Riva,PMC); 1400 LOAD_FIXED_STATE(Riva,PTIMER); 1401 switch (chip->Architecture) 1402 { 1403 case NV_ARCH_03: 1404 /* 1405 * Make sure frame buffer config gets set before loading PRAMIN. 1406 */ 1407 NV_WR32(chip->PFB, 0x00000200, state->config); 1408 LOAD_FIXED_STATE(nv3,PFIFO); 1409 LOAD_FIXED_STATE(nv3,PRAMIN); 1410 LOAD_FIXED_STATE(nv3,PGRAPH); 1411 switch (state->bpp) 1412 { 1413 case 15: 1414 case 16: 1415 LOAD_FIXED_STATE_15BPP(nv3,PRAMIN); 1416 LOAD_FIXED_STATE_15BPP(nv3,PGRAPH); 1417 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1418 break; 1419 case 24: 1420 case 32: 1421 LOAD_FIXED_STATE_32BPP(nv3,PRAMIN); 1422 LOAD_FIXED_STATE_32BPP(nv3,PGRAPH); 1423 chip->Tri03 = NULL; 1424 break; 1425 case 8: 1426 default: 1427 LOAD_FIXED_STATE_8BPP(nv3,PRAMIN); 1428 LOAD_FIXED_STATE_8BPP(nv3,PGRAPH); 1429 chip->Tri03 = NULL; 1430 break; 1431 } 1432 for (i = 0x00000; i < 0x00800; i++) 1433 NV_WR32(&chip->PRAMIN[0x00000502 + i], 0, (i << 12) | 0x03); 1434 NV_WR32(chip->PGRAPH, 0x00000630, state->offset0); 1435 NV_WR32(chip->PGRAPH, 0x00000634, state->offset1); 1436 NV_WR32(chip->PGRAPH, 0x00000638, state->offset2); 1437 NV_WR32(chip->PGRAPH, 0x0000063C, state->offset3); 1438 NV_WR32(chip->PGRAPH, 0x00000650, state->pitch0); 1439 NV_WR32(chip->PGRAPH, 0x00000654, state->pitch1); 1440 NV_WR32(chip->PGRAPH, 0x00000658, state->pitch2); 1441 NV_WR32(chip->PGRAPH, 0x0000065C, state->pitch3); 1442 break; 1443 case NV_ARCH_04: 1444 /* 1445 * Make sure frame buffer config gets set before loading PRAMIN. 1446 */ 1447 NV_WR32(chip->PFB, 0x00000200, state->config); 1448 LOAD_FIXED_STATE(nv4,PFIFO); 1449 LOAD_FIXED_STATE(nv4,PRAMIN); 1450 LOAD_FIXED_STATE(nv4,PGRAPH); 1451 switch (state->bpp) 1452 { 1453 case 15: 1454 LOAD_FIXED_STATE_15BPP(nv4,PRAMIN); 1455 LOAD_FIXED_STATE_15BPP(nv4,PGRAPH); 1456 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1457 break; 1458 case 16: 1459 LOAD_FIXED_STATE_16BPP(nv4,PRAMIN); 1460 LOAD_FIXED_STATE_16BPP(nv4,PGRAPH); 1461 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1462 break; 1463 case 24: 1464 case 32: 1465 LOAD_FIXED_STATE_32BPP(nv4,PRAMIN); 1466 LOAD_FIXED_STATE_32BPP(nv4,PGRAPH); 1467 chip->Tri03 = NULL; 1468 break; 1469 case 8: 1470 default: 1471 LOAD_FIXED_STATE_8BPP(nv4,PRAMIN); 1472 LOAD_FIXED_STATE_8BPP(nv4,PGRAPH); 1473 chip->Tri03 = NULL; 1474 break; 1475 } 1476 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); 1477 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); 1478 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); 1479 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); 1480 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); 1481 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); 1482 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); 1483 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); 1484 break; 1485 case NV_ARCH_10: 1486 case NV_ARCH_20: 1487 case NV_ARCH_30: 1488 if(chip->twoHeads) { 1489 VGA_WR08(chip->PCIO, 0x03D4, 0x44); 1490 VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); 1491 chip->LockUnlock(chip, 0); 1492 } 1493 1494 LOAD_FIXED_STATE(nv10,PFIFO); 1495 LOAD_FIXED_STATE(nv10,PRAMIN); 1496 LOAD_FIXED_STATE(nv10,PGRAPH); 1497 switch (state->bpp) 1498 { 1499 case 15: 1500 LOAD_FIXED_STATE_15BPP(nv10,PRAMIN); 1501 LOAD_FIXED_STATE_15BPP(nv10,PGRAPH); 1502 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1503 break; 1504 case 16: 1505 LOAD_FIXED_STATE_16BPP(nv10,PRAMIN); 1506 LOAD_FIXED_STATE_16BPP(nv10,PGRAPH); 1507 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 1508 break; 1509 case 24: 1510 case 32: 1511 LOAD_FIXED_STATE_32BPP(nv10,PRAMIN); 1512 LOAD_FIXED_STATE_32BPP(nv10,PGRAPH); 1513 chip->Tri03 = NULL; 1514 break; 1515 case 8: 1516 default: 1517 LOAD_FIXED_STATE_8BPP(nv10,PRAMIN); 1518 LOAD_FIXED_STATE_8BPP(nv10,PGRAPH); 1519 chip->Tri03 = NULL; 1520 break; 1521 } 1522 1523 if(chip->Architecture == NV_ARCH_10) { 1524 NV_WR32(chip->PGRAPH, 0x00000640, state->offset0); 1525 NV_WR32(chip->PGRAPH, 0x00000644, state->offset1); 1526 NV_WR32(chip->PGRAPH, 0x00000648, state->offset2); 1527 NV_WR32(chip->PGRAPH, 0x0000064C, state->offset3); 1528 NV_WR32(chip->PGRAPH, 0x00000670, state->pitch0); 1529 NV_WR32(chip->PGRAPH, 0x00000674, state->pitch1); 1530 NV_WR32(chip->PGRAPH, 0x00000678, state->pitch2); 1531 NV_WR32(chip->PGRAPH, 0x0000067C, state->pitch3); 1532 NV_WR32(chip->PGRAPH, 0x00000680, state->pitch3); 1533 } else { 1534 NV_WR32(chip->PGRAPH, 0x00000820, state->offset0); 1535 NV_WR32(chip->PGRAPH, 0x00000824, state->offset1); 1536 NV_WR32(chip->PGRAPH, 0x00000828, state->offset2); 1537 NV_WR32(chip->PGRAPH, 0x0000082C, state->offset3); 1538 NV_WR32(chip->PGRAPH, 0x00000850, state->pitch0); 1539 NV_WR32(chip->PGRAPH, 0x00000854, state->pitch1); 1540 NV_WR32(chip->PGRAPH, 0x00000858, state->pitch2); 1541 NV_WR32(chip->PGRAPH, 0x0000085C, state->pitch3); 1542 NV_WR32(chip->PGRAPH, 0x00000860, state->pitch3); 1543 NV_WR32(chip->PGRAPH, 0x00000864, state->pitch3); 1544 NV_WR32(chip->PGRAPH, 0x000009A4, NV_RD32(chip->PFB, 0x00000200)); 1545 NV_WR32(chip->PGRAPH, 0x000009A8, NV_RD32(chip->PFB, 0x00000204)); 1546 } 1547 if(chip->twoHeads) { 1548 NV_WR32(chip->PCRTC0, 0x00000860, state->head); 1549 NV_WR32(chip->PCRTC0, 0x00002860, state->head2); 1550 } 1551 NV_WR32(chip->PRAMDAC, 0x00000404, NV_RD32(chip->PRAMDAC, 0x00000404) | (1 << 25)); 1552 1553 NV_WR32(chip->PMC, 0x00008704, 1); 1554 NV_WR32(chip->PMC, 0x00008140, 0); 1555 NV_WR32(chip->PMC, 0x00008920, 0); 1556 NV_WR32(chip->PMC, 0x00008924, 0); 1557 NV_WR32(chip->PMC, 0x00008908, 0x01ffffff); 1558 NV_WR32(chip->PMC, 0x0000890C, 0x01ffffff); 1559 NV_WR32(chip->PMC, 0x00001588, 0); 1560 1561 NV_WR32(chip->PFB, 0x00000240, 0); 1562 NV_WR32(chip->PFB, 0x00000250, 0); 1563 NV_WR32(chip->PFB, 0x00000260, 0); 1564 NV_WR32(chip->PFB, 0x00000270, 0); 1565 NV_WR32(chip->PFB, 0x00000280, 0); 1566 NV_WR32(chip->PFB, 0x00000290, 0); 1567 NV_WR32(chip->PFB, 0x000002A0, 0); 1568 NV_WR32(chip->PFB, 0x000002B0, 0); 1569 1570 NV_WR32(chip->PGRAPH, 0x00000B00, NV_RD32(chip->PFB, 0x00000240)); 1571 NV_WR32(chip->PGRAPH, 0x00000B04, NV_RD32(chip->PFB, 0x00000244)); 1572 NV_WR32(chip->PGRAPH, 0x00000B08, NV_RD32(chip->PFB, 0x00000248)); 1573 NV_WR32(chip->PGRAPH, 0x00000B0C, NV_RD32(chip->PFB, 0x0000024C)); 1574 NV_WR32(chip->PGRAPH, 0x00000B10, NV_RD32(chip->PFB, 0x00000250)); 1575 NV_WR32(chip->PGRAPH, 0x00000B14, NV_RD32(chip->PFB, 0x00000254)); 1576 NV_WR32(chip->PGRAPH, 0x00000B18, NV_RD32(chip->PFB, 0x00000258)); 1577 NV_WR32(chip->PGRAPH, 0x00000B1C, NV_RD32(chip->PFB, 0x0000025C)); 1578 NV_WR32(chip->PGRAPH, 0x00000B20, NV_RD32(chip->PFB, 0x00000260)); 1579 NV_WR32(chip->PGRAPH, 0x00000B24, NV_RD32(chip->PFB, 0x00000264)); 1580 NV_WR32(chip->PGRAPH, 0x00000B28, NV_RD32(chip->PFB, 0x00000268)); 1581 NV_WR32(chip->PGRAPH, 0x00000B2C, NV_RD32(chip->PFB, 0x0000026C)); 1582 NV_WR32(chip->PGRAPH, 0x00000B30, NV_RD32(chip->PFB, 0x00000270)); 1583 NV_WR32(chip->PGRAPH, 0x00000B34, NV_RD32(chip->PFB, 0x00000274)); 1584 NV_WR32(chip->PGRAPH, 0x00000B38, NV_RD32(chip->PFB, 0x00000278)); 1585 NV_WR32(chip->PGRAPH, 0x00000B3C, NV_RD32(chip->PFB, 0x0000027C)); 1586 NV_WR32(chip->PGRAPH, 0x00000B40, NV_RD32(chip->PFB, 0x00000280)); 1587 NV_WR32(chip->PGRAPH, 0x00000B44, NV_RD32(chip->PFB, 0x00000284)); 1588 NV_WR32(chip->PGRAPH, 0x00000B48, NV_RD32(chip->PFB, 0x00000288)); 1589 NV_WR32(chip->PGRAPH, 0x00000B4C, NV_RD32(chip->PFB, 0x0000028C)); 1590 NV_WR32(chip->PGRAPH, 0x00000B50, NV_RD32(chip->PFB, 0x00000290)); 1591 NV_WR32(chip->PGRAPH, 0x00000B54, NV_RD32(chip->PFB, 0x00000294)); 1592 NV_WR32(chip->PGRAPH, 0x00000B58, NV_RD32(chip->PFB, 0x00000298)); 1593 NV_WR32(chip->PGRAPH, 0x00000B5C, NV_RD32(chip->PFB, 0x0000029C)); 1594 NV_WR32(chip->PGRAPH, 0x00000B60, NV_RD32(chip->PFB, 0x000002A0)); 1595 NV_WR32(chip->PGRAPH, 0x00000B64, NV_RD32(chip->PFB, 0x000002A4)); 1596 NV_WR32(chip->PGRAPH, 0x00000B68, NV_RD32(chip->PFB, 0x000002A8)); 1597 NV_WR32(chip->PGRAPH, 0x00000B6C, NV_RD32(chip->PFB, 0x000002AC)); 1598 NV_WR32(chip->PGRAPH, 0x00000B70, NV_RD32(chip->PFB, 0x000002B0)); 1599 NV_WR32(chip->PGRAPH, 0x00000B74, NV_RD32(chip->PFB, 0x000002B4)); 1600 NV_WR32(chip->PGRAPH, 0x00000B78, NV_RD32(chip->PFB, 0x000002B8)); 1601 NV_WR32(chip->PGRAPH, 0x00000B7C, NV_RD32(chip->PFB, 0x000002BC)); 1602 NV_WR32(chip->PGRAPH, 0x00000F40, 0x10000000); 1603 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000000); 1604 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); 1605 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000008); 1606 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000200); 1607 for (i = 0; i < (3*16); i++) 1608 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1609 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); 1610 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1611 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000800); 1612 for (i = 0; i < (16*16); i++) 1613 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1614 NV_WR32(chip->PGRAPH, 0x00000F40, 0x30000000); 1615 NV_WR32(chip->PGRAPH, 0x00000F44, 0x00000004); 1616 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006400); 1617 for (i = 0; i < (59*4); i++) 1618 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1619 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006800); 1620 for (i = 0; i < (47*4); i++) 1621 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1622 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00006C00); 1623 for (i = 0; i < (3*4); i++) 1624 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1625 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007000); 1626 for (i = 0; i < (19*4); i++) 1627 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1628 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007400); 1629 for (i = 0; i < (12*4); i++) 1630 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1631 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00007800); 1632 for (i = 0; i < (12*4); i++) 1633 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1634 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00004400); 1635 for (i = 0; i < (8*4); i++) 1636 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1637 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000000); 1638 for (i = 0; i < 16; i++) 1639 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1640 NV_WR32(chip->PGRAPH, 0x00000F50, 0x00000040); 1641 for (i = 0; i < 4; i++) 1642 NV_WR32(chip->PGRAPH, 0x00000F54, 0x00000000); 1643 1644 NV_WR32(chip->PCRTC, 0x00000810, state->cursorConfig); 1645 1646 if(chip->flatPanel) { 1647 if((chip->Chipset & 0x0ff0) == 0x0110) { 1648 NV_WR32(chip->PRAMDAC, 0x0528, state->dither); 1649 } else 1650 if((chip->Chipset & 0x0ff0) >= 0x0170) { 1651 NV_WR32(chip->PRAMDAC, 0x083C, state->dither); 1652 } 1653 1654 VGA_WR08(chip->PCIO, 0x03D4, 0x53); 1655 VGA_WR08(chip->PCIO, 0x03D5, 0); 1656 VGA_WR08(chip->PCIO, 0x03D4, 0x54); 1657 VGA_WR08(chip->PCIO, 0x03D5, 0); 1658 VGA_WR08(chip->PCIO, 0x03D4, 0x21); 1659 VGA_WR08(chip->PCIO, 0x03D5, 0xfa); 1660 } 1661 1662 VGA_WR08(chip->PCIO, 0x03D4, 0x41); 1663 VGA_WR08(chip->PCIO, 0x03D5, state->extra); 1664 } 1665 LOAD_FIXED_STATE(Riva,FIFO); 1666 UpdateFifoState(chip); 1667 /* 1668 * Load HW mode state. 1669 */ 1670 VGA_WR08(chip->PCIO, 0x03D4, 0x19); 1671 VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); 1672 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); 1673 VGA_WR08(chip->PCIO, 0x03D5, state->repaint1); 1674 VGA_WR08(chip->PCIO, 0x03D4, 0x25); 1675 VGA_WR08(chip->PCIO, 0x03D5, state->screen); 1676 VGA_WR08(chip->PCIO, 0x03D4, 0x28); 1677 VGA_WR08(chip->PCIO, 0x03D5, state->pixel); 1678 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); 1679 VGA_WR08(chip->PCIO, 0x03D5, state->horiz); 1680 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); 1681 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration0); 1682 VGA_WR08(chip->PCIO, 0x03D4, 0x20); 1683 VGA_WR08(chip->PCIO, 0x03D5, state->arbitration1); 1684 VGA_WR08(chip->PCIO, 0x03D4, 0x30); 1685 VGA_WR08(chip->PCIO, 0x03D5, state->cursor0); 1686 VGA_WR08(chip->PCIO, 0x03D4, 0x31); 1687 VGA_WR08(chip->PCIO, 0x03D5, state->cursor1); 1688 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); 1689 VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); 1690 VGA_WR08(chip->PCIO, 0x03D4, 0x39); 1691 VGA_WR08(chip->PCIO, 0x03D5, state->interlace); 1692 1693 if(!chip->flatPanel) { 1694 NV_WR32(chip->PRAMDAC0, 0x00000508, state->vpll); 1695 NV_WR32(chip->PRAMDAC0, 0x0000050C, state->pllsel); 1696 if(chip->twoHeads) 1697 NV_WR32(chip->PRAMDAC0, 0x00000520, state->vpll2); 1698 } else { 1699 NV_WR32(chip->PRAMDAC, 0x00000848 , state->scale); 1700 } 1701 NV_WR32(chip->PRAMDAC, 0x00000600 , state->general); 1702 1703 /* 1704 * Turn off VBlank enable and reset. 1705 */ 1706 NV_WR32(chip->PCRTC, 0x00000140, 0); 1707 NV_WR32(chip->PCRTC, 0x00000100, chip->VBlankBit); 1708 /* 1709 * Set interrupt enable. 1710 */ 1711 NV_WR32(chip->PMC, 0x00000140, chip->EnableIRQ & 0x01); 1712 /* 1713 * Set current state pointer. 1714 */ 1715 chip->CurrentState = state; 1716 /* 1717 * Reset FIFO free and empty counts. 1718 */ 1719 chip->FifoFreeCount = 0; 1720 /* Free count from first subchannel */ 1721 chip->FifoEmptyCount = NV_RD32(&chip->Rop->FifoFree, 0); 1722 } 1723 static void UnloadStateExt 1724 ( 1725 RIVA_HW_INST *chip, 1726 RIVA_HW_STATE *state 1727 ) 1728 { 1729 /* 1730 * Save current HW state. 1731 */ 1732 VGA_WR08(chip->PCIO, 0x03D4, 0x19); 1733 state->repaint0 = VGA_RD08(chip->PCIO, 0x03D5); 1734 VGA_WR08(chip->PCIO, 0x03D4, 0x1A); 1735 state->repaint1 = VGA_RD08(chip->PCIO, 0x03D5); 1736 VGA_WR08(chip->PCIO, 0x03D4, 0x25); 1737 state->screen = VGA_RD08(chip->PCIO, 0x03D5); 1738 VGA_WR08(chip->PCIO, 0x03D4, 0x28); 1739 state->pixel = VGA_RD08(chip->PCIO, 0x03D5); 1740 VGA_WR08(chip->PCIO, 0x03D4, 0x2D); 1741 state->horiz = VGA_RD08(chip->PCIO, 0x03D5); 1742 VGA_WR08(chip->PCIO, 0x03D4, 0x1B); 1743 state->arbitration0 = VGA_RD08(chip->PCIO, 0x03D5); 1744 VGA_WR08(chip->PCIO, 0x03D4, 0x20); 1745 state->arbitration1 = VGA_RD08(chip->PCIO, 0x03D5); 1746 VGA_WR08(chip->PCIO, 0x03D4, 0x30); 1747 state->cursor0 = VGA_RD08(chip->PCIO, 0x03D5); 1748 VGA_WR08(chip->PCIO, 0x03D4, 0x31); 1749 state->cursor1 = VGA_RD08(chip->PCIO, 0x03D5); 1750 VGA_WR08(chip->PCIO, 0x03D4, 0x2F); 1751 state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); 1752 VGA_WR08(chip->PCIO, 0x03D4, 0x39); 1753 state->interlace = VGA_RD08(chip->PCIO, 0x03D5); 1754 state->vpll = NV_RD32(chip->PRAMDAC0, 0x00000508); 1755 state->vpll2 = NV_RD32(chip->PRAMDAC0, 0x00000520); 1756 state->pllsel = NV_RD32(chip->PRAMDAC0, 0x0000050C); 1757 state->general = NV_RD32(chip->PRAMDAC, 0x00000600); 1758 state->scale = NV_RD32(chip->PRAMDAC, 0x00000848); 1759 state->config = NV_RD32(chip->PFB, 0x00000200); 1760 switch (chip->Architecture) 1761 { 1762 case NV_ARCH_03: 1763 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000630); 1764 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000634); 1765 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000638); 1766 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000063C); 1767 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000650); 1768 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000654); 1769 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000658); 1770 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000065C); 1771 break; 1772 case NV_ARCH_04: 1773 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); 1774 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); 1775 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); 1776 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); 1777 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); 1778 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); 1779 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); 1780 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); 1781 break; 1782 case NV_ARCH_10: 1783 case NV_ARCH_20: 1784 case NV_ARCH_30: 1785 state->offset0 = NV_RD32(chip->PGRAPH, 0x00000640); 1786 state->offset1 = NV_RD32(chip->PGRAPH, 0x00000644); 1787 state->offset2 = NV_RD32(chip->PGRAPH, 0x00000648); 1788 state->offset3 = NV_RD32(chip->PGRAPH, 0x0000064C); 1789 state->pitch0 = NV_RD32(chip->PGRAPH, 0x00000670); 1790 state->pitch1 = NV_RD32(chip->PGRAPH, 0x00000674); 1791 state->pitch2 = NV_RD32(chip->PGRAPH, 0x00000678); 1792 state->pitch3 = NV_RD32(chip->PGRAPH, 0x0000067C); 1793 if(chip->twoHeads) { 1794 state->head = NV_RD32(chip->PCRTC0, 0x00000860); 1795 state->head2 = NV_RD32(chip->PCRTC0, 0x00002860); 1796 VGA_WR08(chip->PCIO, 0x03D4, 0x44); 1797 state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); 1798 } 1799 VGA_WR08(chip->PCIO, 0x03D4, 0x41); 1800 state->extra = VGA_RD08(chip->PCIO, 0x03D5); 1801 state->cursorConfig = NV_RD32(chip->PCRTC, 0x00000810); 1802 1803 if((chip->Chipset & 0x0ff0) == 0x0110) { 1804 state->dither = NV_RD32(chip->PRAMDAC, 0x0528); 1805 } else 1806 if((chip->Chipset & 0x0ff0) >= 0x0170) { 1807 state->dither = NV_RD32(chip->PRAMDAC, 0x083C); 1808 } 1809 break; 1810 } 1811 } 1812 static void SetStartAddress 1813 ( 1814 RIVA_HW_INST *chip, 1815 unsigned start 1816 ) 1817 { 1818 NV_WR32(chip->PCRTC, 0x800, start); 1819 } 1820 1821 static void SetStartAddress3 1822 ( 1823 RIVA_HW_INST *chip, 1824 unsigned start 1825 ) 1826 { 1827 int offset = start >> 2; 1828 int pan = (start & 3) << 1; 1829 unsigned char tmp; 1830 1831 /* 1832 * Unlock extended registers. 1833 */ 1834 chip->LockUnlock(chip, 0); 1835 /* 1836 * Set start address. 1837 */ 1838 VGA_WR08(chip->PCIO, 0x3D4, 0x0D); VGA_WR08(chip->PCIO, 0x3D5, offset); 1839 offset >>= 8; 1840 VGA_WR08(chip->PCIO, 0x3D4, 0x0C); VGA_WR08(chip->PCIO, 0x3D5, offset); 1841 offset >>= 8; 1842 VGA_WR08(chip->PCIO, 0x3D4, 0x19); tmp = VGA_RD08(chip->PCIO, 0x3D5); 1843 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x01F) | (tmp & ~0x1F)); 1844 VGA_WR08(chip->PCIO, 0x3D4, 0x2D); tmp = VGA_RD08(chip->PCIO, 0x3D5); 1845 VGA_WR08(chip->PCIO, 0x3D5, (offset & 0x60) | (tmp & ~0x60)); 1846 /* 1847 * 4 pixel pan register. 1848 */ 1849 offset = VGA_RD08(chip->PCIO, chip->IO + 0x0A); 1850 VGA_WR08(chip->PCIO, 0x3C0, 0x13); 1851 VGA_WR08(chip->PCIO, 0x3C0, pan); 1852 } 1853 static void nv3SetSurfaces2D 1854 ( 1855 RIVA_HW_INST *chip, 1856 unsigned surf0, 1857 unsigned surf1 1858 ) 1859 { 1860 RivaSurface __iomem *Surface = 1861 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1862 1863 RIVA_FIFO_FREE(*chip,Tri03,5); 1864 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); 1865 NV_WR32(&Surface->Offset, 0, surf0); 1866 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); 1867 NV_WR32(&Surface->Offset, 0, surf1); 1868 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); 1869 } 1870 static void nv4SetSurfaces2D 1871 ( 1872 RIVA_HW_INST *chip, 1873 unsigned surf0, 1874 unsigned surf1 1875 ) 1876 { 1877 RivaSurface __iomem *Surface = 1878 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1879 1880 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); 1881 NV_WR32(&Surface->Offset, 0, surf0); 1882 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); 1883 NV_WR32(&Surface->Offset, 0, surf1); 1884 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1885 } 1886 static void nv10SetSurfaces2D 1887 ( 1888 RIVA_HW_INST *chip, 1889 unsigned surf0, 1890 unsigned surf1 1891 ) 1892 { 1893 RivaSurface __iomem *Surface = 1894 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1895 1896 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000003); 1897 NV_WR32(&Surface->Offset, 0, surf0); 1898 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000004); 1899 NV_WR32(&Surface->Offset, 0, surf1); 1900 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1901 } 1902 static void nv3SetSurfaces3D 1903 ( 1904 RIVA_HW_INST *chip, 1905 unsigned surf0, 1906 unsigned surf1 1907 ) 1908 { 1909 RivaSurface __iomem *Surface = 1910 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1911 1912 RIVA_FIFO_FREE(*chip,Tri03,5); 1913 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); 1914 NV_WR32(&Surface->Offset, 0, surf0); 1915 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); 1916 NV_WR32(&Surface->Offset, 0, surf1); 1917 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000013); 1918 } 1919 static void nv4SetSurfaces3D 1920 ( 1921 RIVA_HW_INST *chip, 1922 unsigned surf0, 1923 unsigned surf1 1924 ) 1925 { 1926 RivaSurface __iomem *Surface = 1927 (RivaSurface __iomem *)&(chip->FIFO[0x0000E000/4]); 1928 1929 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000005); 1930 NV_WR32(&Surface->Offset, 0, surf0); 1931 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000006); 1932 NV_WR32(&Surface->Offset, 0, surf1); 1933 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1934 } 1935 static void nv10SetSurfaces3D 1936 ( 1937 RIVA_HW_INST *chip, 1938 unsigned surf0, 1939 unsigned surf1 1940 ) 1941 { 1942 RivaSurface3D __iomem *Surfaces3D = 1943 (RivaSurface3D __iomem *)&(chip->FIFO[0x0000E000/4]); 1944 1945 RIVA_FIFO_FREE(*chip,Tri03,4); 1946 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000007); 1947 NV_WR32(&Surfaces3D->RenderBufferOffset, 0, surf0); 1948 NV_WR32(&Surfaces3D->ZBufferOffset, 0, surf1); 1949 NV_WR32(&chip->FIFO[0x00003800], 0, 0x80000014); 1950 } 1951 1952 /****************************************************************************\ 1953 * * 1954 * Probe RIVA Chip Configuration * 1955 * * 1956 \****************************************************************************/ 1957 1958 static void nv3GetConfig 1959 ( 1960 RIVA_HW_INST *chip 1961 ) 1962 { 1963 /* 1964 * Fill in chip configuration. 1965 */ 1966 if (NV_RD32(&chip->PFB[0x00000000/4], 0) & 0x00000020) 1967 { 1968 if (((NV_RD32(chip->PMC, 0x00000000) & 0xF0) == 0x20) 1969 && ((NV_RD32(chip->PMC, 0x00000000) & 0x0F) >= 0x02)) 1970 { 1971 /* 1972 * SDRAM 128 ZX. 1973 */ 1974 chip->RamBandwidthKBytesPerSec = 800000; 1975 switch (NV_RD32(chip->PFB, 0x00000000) & 0x03) 1976 { 1977 case 2: 1978 chip->RamAmountKBytes = 1024 * 4; 1979 break; 1980 case 1: 1981 chip->RamAmountKBytes = 1024 * 2; 1982 break; 1983 default: 1984 chip->RamAmountKBytes = 1024 * 8; 1985 break; 1986 } 1987 } 1988 else 1989 { 1990 chip->RamBandwidthKBytesPerSec = 1000000; 1991 chip->RamAmountKBytes = 1024 * 8; 1992 } 1993 } 1994 else 1995 { 1996 /* 1997 * SGRAM 128. 1998 */ 1999 chip->RamBandwidthKBytesPerSec = 1000000; 2000 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) 2001 { 2002 case 0: 2003 chip->RamAmountKBytes = 1024 * 8; 2004 break; 2005 case 2: 2006 chip->RamAmountKBytes = 1024 * 4; 2007 break; 2008 default: 2009 chip->RamAmountKBytes = 1024 * 2; 2010 break; 2011 } 2012 } 2013 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; 2014 chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); 2015 chip->VBlankBit = 0x00000100; 2016 chip->MaxVClockFreqKHz = 256000; 2017 /* 2018 * Set chip functions. 2019 */ 2020 chip->Busy = nv3Busy; 2021 chip->ShowHideCursor = ShowHideCursor; 2022 chip->LoadStateExt = LoadStateExt; 2023 chip->UnloadStateExt = UnloadStateExt; 2024 chip->SetStartAddress = SetStartAddress3; 2025 chip->SetSurfaces2D = nv3SetSurfaces2D; 2026 chip->SetSurfaces3D = nv3SetSurfaces3D; 2027 chip->LockUnlock = nv3LockUnlock; 2028 } 2029 static void nv4GetConfig 2030 ( 2031 RIVA_HW_INST *chip 2032 ) 2033 { 2034 /* 2035 * Fill in chip configuration. 2036 */ 2037 if (NV_RD32(chip->PFB, 0x00000000) & 0x00000100) 2038 { 2039 chip->RamAmountKBytes = ((NV_RD32(chip->PFB, 0x00000000) >> 12) & 0x0F) * 1024 * 2 2040 + 1024 * 2; 2041 } 2042 else 2043 { 2044 switch (NV_RD32(chip->PFB, 0x00000000) & 0x00000003) 2045 { 2046 case 0: 2047 chip->RamAmountKBytes = 1024 * 32; 2048 break; 2049 case 1: 2050 chip->RamAmountKBytes = 1024 * 4; 2051 break; 2052 case 2: 2053 chip->RamAmountKBytes = 1024 * 8; 2054 break; 2055 case 3: 2056 default: 2057 chip->RamAmountKBytes = 1024 * 16; 2058 break; 2059 } 2060 } 2061 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) 2062 { 2063 case 3: 2064 chip->RamBandwidthKBytesPerSec = 800000; 2065 break; 2066 default: 2067 chip->RamBandwidthKBytesPerSec = 1000000; 2068 break; 2069 } 2070 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x00000000) & 0x00000040) ? 14318 : 13500; 2071 chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); 2072 chip->VBlankBit = 0x00000001; 2073 chip->MaxVClockFreqKHz = 350000; 2074 /* 2075 * Set chip functions. 2076 */ 2077 chip->Busy = nv4Busy; 2078 chip->ShowHideCursor = ShowHideCursor; 2079 chip->LoadStateExt = LoadStateExt; 2080 chip->UnloadStateExt = UnloadStateExt; 2081 chip->SetStartAddress = SetStartAddress; 2082 chip->SetSurfaces2D = nv4SetSurfaces2D; 2083 chip->SetSurfaces3D = nv4SetSurfaces3D; 2084 chip->LockUnlock = nv4LockUnlock; 2085 } 2086 static void nv10GetConfig 2087 ( 2088 RIVA_HW_INST *chip, 2089 struct pci_dev *pdev, 2090 unsigned int chipset 2091 ) 2092 { 2093 struct pci_dev* dev; 2094 int domain = pci_domain_nr(pdev->bus); 2095 u32 amt; 2096 2097 #ifdef __BIG_ENDIAN 2098 /* turn on big endian register access */ 2099 if(!(NV_RD32(chip->PMC, 0x00000004) & 0x01000001)) 2100 NV_WR32(chip->PMC, 0x00000004, 0x01000001); 2101 #endif 2102 2103 /* 2104 * Fill in chip configuration. 2105 */ 2106 if(chipset == NV_CHIP_IGEFORCE2) { 2107 dev = pci_get_domain_bus_and_slot(domain, 0, 1); 2108 pci_read_config_dword(dev, 0x7C, &amt); 2109 pci_dev_put(dev); 2110 chip->RamAmountKBytes = (((amt >> 6) & 31) + 1) * 1024; 2111 } else if(chipset == NV_CHIP_0x01F0) { 2112 dev = pci_get_domain_bus_and_slot(domain, 0, 1); 2113 pci_read_config_dword(dev, 0x84, &amt); 2114 pci_dev_put(dev); 2115 chip->RamAmountKBytes = (((amt >> 4) & 127) + 1) * 1024; 2116 } else { 2117 switch ((NV_RD32(chip->PFB, 0x0000020C) >> 20) & 0x000000FF) 2118 { 2119 case 0x02: 2120 chip->RamAmountKBytes = 1024 * 2; 2121 break; 2122 case 0x04: 2123 chip->RamAmountKBytes = 1024 * 4; 2124 break; 2125 case 0x08: 2126 chip->RamAmountKBytes = 1024 * 8; 2127 break; 2128 case 0x10: 2129 chip->RamAmountKBytes = 1024 * 16; 2130 break; 2131 case 0x20: 2132 chip->RamAmountKBytes = 1024 * 32; 2133 break; 2134 case 0x40: 2135 chip->RamAmountKBytes = 1024 * 64; 2136 break; 2137 case 0x80: 2138 chip->RamAmountKBytes = 1024 * 128; 2139 break; 2140 default: 2141 chip->RamAmountKBytes = 1024 * 16; 2142 break; 2143 } 2144 } 2145 switch ((NV_RD32(chip->PFB, 0x00000000) >> 3) & 0x00000003) 2146 { 2147 case 3: 2148 chip->RamBandwidthKBytesPerSec = 800000; 2149 break; 2150 default: 2151 chip->RamBandwidthKBytesPerSec = 1000000; 2152 break; 2153 } 2154 chip->CrystalFreqKHz = (NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 6)) ? 2155 14318 : 13500; 2156 2157 switch (chipset & 0x0ff0) { 2158 case 0x0170: 2159 case 0x0180: 2160 case 0x01F0: 2161 case 0x0250: 2162 case 0x0280: 2163 case 0x0300: 2164 case 0x0310: 2165 case 0x0320: 2166 case 0x0330: 2167 case 0x0340: 2168 if(NV_RD32(chip->PEXTDEV, 0x0000) & (1 << 22)) 2169 chip->CrystalFreqKHz = 27000; 2170 break; 2171 default: 2172 break; 2173 } 2174 2175 chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024; 2176 chip->CURSOR = NULL; /* can't set this here */ 2177 chip->VBlankBit = 0x00000001; 2178 chip->MaxVClockFreqKHz = 350000; 2179 /* 2180 * Set chip functions. 2181 */ 2182 chip->Busy = nv10Busy; 2183 chip->ShowHideCursor = ShowHideCursor; 2184 chip->LoadStateExt = LoadStateExt; 2185 chip->UnloadStateExt = UnloadStateExt; 2186 chip->SetStartAddress = SetStartAddress; 2187 chip->SetSurfaces2D = nv10SetSurfaces2D; 2188 chip->SetSurfaces3D = nv10SetSurfaces3D; 2189 chip->LockUnlock = nv4LockUnlock; 2190 2191 switch(chipset & 0x0ff0) { 2192 case 0x0110: 2193 case 0x0170: 2194 case 0x0180: 2195 case 0x01F0: 2196 case 0x0250: 2197 case 0x0280: 2198 case 0x0300: 2199 case 0x0310: 2200 case 0x0320: 2201 case 0x0330: 2202 case 0x0340: 2203 chip->twoHeads = TRUE; 2204 break; 2205 default: 2206 chip->twoHeads = FALSE; 2207 break; 2208 } 2209 } 2210 int RivaGetConfig 2211 ( 2212 RIVA_HW_INST *chip, 2213 struct pci_dev *pdev, 2214 unsigned int chipset 2215 ) 2216 { 2217 /* 2218 * Save this so future SW know whats it's dealing with. 2219 */ 2220 chip->Version = RIVA_SW_VERSION; 2221 /* 2222 * Chip specific configuration. 2223 */ 2224 switch (chip->Architecture) 2225 { 2226 case NV_ARCH_03: 2227 nv3GetConfig(chip); 2228 break; 2229 case NV_ARCH_04: 2230 nv4GetConfig(chip); 2231 break; 2232 case NV_ARCH_10: 2233 case NV_ARCH_20: 2234 case NV_ARCH_30: 2235 nv10GetConfig(chip, pdev, chipset); 2236 break; 2237 default: 2238 return (-1); 2239 } 2240 chip->Chipset = chipset; 2241 /* 2242 * Fill in FIFO pointers. 2243 */ 2244 chip->Rop = (RivaRop __iomem *)&(chip->FIFO[0x00000000/4]); 2245 chip->Clip = (RivaClip __iomem *)&(chip->FIFO[0x00002000/4]); 2246 chip->Patt = (RivaPattern __iomem *)&(chip->FIFO[0x00004000/4]); 2247 chip->Pixmap = (RivaPixmap __iomem *)&(chip->FIFO[0x00006000/4]); 2248 chip->Blt = (RivaScreenBlt __iomem *)&(chip->FIFO[0x00008000/4]); 2249 chip->Bitmap = (RivaBitmap __iomem *)&(chip->FIFO[0x0000A000/4]); 2250 chip->Line = (RivaLine __iomem *)&(chip->FIFO[0x0000C000/4]); 2251 chip->Tri03 = (RivaTexturedTriangle03 __iomem *)&(chip->FIFO[0x0000E000/4]); 2252 return (0); 2253 } 2254 2255