1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Ingenic SoCs pinctrl driver 4 * 5 * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> 6 * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 7 * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk> 8 */ 9 10 #include <linux/compiler.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_platform.h> 17 #include <linux/pinctrl/pinctrl.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 25 #include "core.h" 26 #include "pinconf.h" 27 #include "pinmux.h" 28 29 #define GPIO_PIN 0x00 30 #define GPIO_MSK 0x20 31 32 #define JZ4740_GPIO_DATA 0x10 33 #define JZ4740_GPIO_PULL_DIS 0x30 34 #define JZ4740_GPIO_FUNC 0x40 35 #define JZ4740_GPIO_SELECT 0x50 36 #define JZ4740_GPIO_DIR 0x60 37 #define JZ4740_GPIO_TRIG 0x70 38 #define JZ4740_GPIO_FLAG 0x80 39 40 #define JZ4760_GPIO_INT 0x10 41 #define JZ4760_GPIO_PAT1 0x30 42 #define JZ4760_GPIO_PAT0 0x40 43 #define JZ4760_GPIO_FLAG 0x50 44 #define JZ4760_GPIO_PEN 0x70 45 46 #define X1830_GPIO_PEL 0x110 47 #define X1830_GPIO_PEH 0x120 48 49 #define REG_SET(x) ((x) + 0x4) 50 #define REG_CLEAR(x) ((x) + 0x8) 51 52 #define REG_PZ_BASE(x) ((x) * 7) 53 #define REG_PZ_GID2LD(x) ((x) * 7 + 0xf0) 54 55 #define GPIO_PULL_DIS 0 56 #define GPIO_PULL_UP 1 57 #define GPIO_PULL_DOWN 2 58 59 #define PINS_PER_GPIO_CHIP 32 60 61 enum jz_version { 62 ID_JZ4740, 63 ID_JZ4725B, 64 ID_JZ4760, 65 ID_JZ4770, 66 ID_JZ4780, 67 ID_X1000, 68 ID_X1500, 69 ID_X1830, 70 }; 71 72 struct ingenic_chip_info { 73 unsigned int num_chips; 74 unsigned int reg_offset; 75 enum jz_version version; 76 77 const struct group_desc *groups; 78 unsigned int num_groups; 79 80 const struct function_desc *functions; 81 unsigned int num_functions; 82 83 const u32 *pull_ups, *pull_downs; 84 }; 85 86 struct ingenic_pinctrl { 87 struct device *dev; 88 struct regmap *map; 89 struct pinctrl_dev *pctl; 90 struct pinctrl_pin_desc *pdesc; 91 92 const struct ingenic_chip_info *info; 93 }; 94 95 struct ingenic_gpio_chip { 96 struct ingenic_pinctrl *jzpc; 97 struct gpio_chip gc; 98 struct irq_chip irq_chip; 99 unsigned int irq, reg_base; 100 }; 101 102 static const u32 jz4740_pull_ups[4] = { 103 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 104 }; 105 106 static const u32 jz4740_pull_downs[4] = { 107 0x00000000, 0x00000000, 0x00000000, 0x00000000, 108 }; 109 110 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, }; 111 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, }; 112 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, }; 113 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, }; 114 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, }; 115 static int jz4740_lcd_8bit_pins[] = { 116 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x52, 0x53, 0x54, 117 }; 118 static int jz4740_lcd_16bit_pins[] = { 119 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 0x55, 120 }; 121 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, }; 122 static int jz4740_lcd_18bit_tft_pins[] = { 0x56, 0x57, 0x31, 0x32, }; 123 static int jz4740_nand_cs1_pins[] = { 0x39, }; 124 static int jz4740_nand_cs2_pins[] = { 0x3a, }; 125 static int jz4740_nand_cs3_pins[] = { 0x3b, }; 126 static int jz4740_nand_cs4_pins[] = { 0x3c, }; 127 static int jz4740_pwm_pwm0_pins[] = { 0x77, }; 128 static int jz4740_pwm_pwm1_pins[] = { 0x78, }; 129 static int jz4740_pwm_pwm2_pins[] = { 0x79, }; 130 static int jz4740_pwm_pwm3_pins[] = { 0x7a, }; 131 static int jz4740_pwm_pwm4_pins[] = { 0x7b, }; 132 static int jz4740_pwm_pwm5_pins[] = { 0x7c, }; 133 static int jz4740_pwm_pwm6_pins[] = { 0x7e, }; 134 static int jz4740_pwm_pwm7_pins[] = { 0x7f, }; 135 136 static int jz4740_mmc_1bit_funcs[] = { 0, 0, 0, }; 137 static int jz4740_mmc_4bit_funcs[] = { 0, 0, 0, }; 138 static int jz4740_uart0_data_funcs[] = { 1, 1, }; 139 static int jz4740_uart0_hwflow_funcs[] = { 1, 1, }; 140 static int jz4740_uart1_data_funcs[] = { 2, 2, }; 141 static int jz4740_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 142 static int jz4740_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 143 static int jz4740_lcd_18bit_funcs[] = { 0, 0, }; 144 static int jz4740_lcd_18bit_tft_funcs[] = { 0, 0, 0, 0, }; 145 static int jz4740_nand_cs1_funcs[] = { 0, }; 146 static int jz4740_nand_cs2_funcs[] = { 0, }; 147 static int jz4740_nand_cs3_funcs[] = { 0, }; 148 static int jz4740_nand_cs4_funcs[] = { 0, }; 149 static int jz4740_pwm_pwm0_funcs[] = { 0, }; 150 static int jz4740_pwm_pwm1_funcs[] = { 0, }; 151 static int jz4740_pwm_pwm2_funcs[] = { 0, }; 152 static int jz4740_pwm_pwm3_funcs[] = { 0, }; 153 static int jz4740_pwm_pwm4_funcs[] = { 0, }; 154 static int jz4740_pwm_pwm5_funcs[] = { 0, }; 155 static int jz4740_pwm_pwm6_funcs[] = { 0, }; 156 static int jz4740_pwm_pwm7_funcs[] = { 0, }; 157 158 #define INGENIC_PIN_GROUP(name, id) \ 159 { \ 160 name, \ 161 id##_pins, \ 162 ARRAY_SIZE(id##_pins), \ 163 id##_funcs, \ 164 } 165 166 static const struct group_desc jz4740_groups[] = { 167 INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit), 168 INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit), 169 INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data), 170 INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow), 171 INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data), 172 INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit), 173 INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit), 174 INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit), 175 INGENIC_PIN_GROUP("lcd-18bit-tft", jz4740_lcd_18bit_tft), 176 { "lcd-no-pins", }, 177 INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1), 178 INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2), 179 INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3), 180 INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4), 181 INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0), 182 INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1), 183 INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2), 184 INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3), 185 INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4), 186 INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5), 187 INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6), 188 INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7), 189 }; 190 191 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 192 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 193 static const char *jz4740_uart1_groups[] = { "uart1-data", }; 194 static const char *jz4740_lcd_groups[] = { 195 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-18bit-tft", "lcd-no-pins", 196 }; 197 static const char *jz4740_nand_groups[] = { 198 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 199 }; 200 static const char *jz4740_pwm0_groups[] = { "pwm0", }; 201 static const char *jz4740_pwm1_groups[] = { "pwm1", }; 202 static const char *jz4740_pwm2_groups[] = { "pwm2", }; 203 static const char *jz4740_pwm3_groups[] = { "pwm3", }; 204 static const char *jz4740_pwm4_groups[] = { "pwm4", }; 205 static const char *jz4740_pwm5_groups[] = { "pwm5", }; 206 static const char *jz4740_pwm6_groups[] = { "pwm6", }; 207 static const char *jz4740_pwm7_groups[] = { "pwm7", }; 208 209 static const struct function_desc jz4740_functions[] = { 210 { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), }, 211 { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), }, 212 { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), }, 213 { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), }, 214 { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), }, 215 { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), }, 216 { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), }, 217 { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), }, 218 { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), }, 219 { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), }, 220 { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), }, 221 { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), }, 222 { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), }, 223 }; 224 225 static const struct ingenic_chip_info jz4740_chip_info = { 226 .num_chips = 4, 227 .reg_offset = 0x100, 228 .version = ID_JZ4740, 229 .groups = jz4740_groups, 230 .num_groups = ARRAY_SIZE(jz4740_groups), 231 .functions = jz4740_functions, 232 .num_functions = ARRAY_SIZE(jz4740_functions), 233 .pull_ups = jz4740_pull_ups, 234 .pull_downs = jz4740_pull_downs, 235 }; 236 237 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, }; 238 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, }; 239 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, }; 240 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, }; 241 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, }; 242 static int jz4725b_nand_cs1_pins[] = { 0x55, }; 243 static int jz4725b_nand_cs2_pins[] = { 0x56, }; 244 static int jz4725b_nand_cs3_pins[] = { 0x57, }; 245 static int jz4725b_nand_cs4_pins[] = { 0x58, }; 246 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 }; 247 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d }; 248 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, }; 249 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, }; 250 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, }; 251 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, }; 252 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, }; 253 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, }; 254 static int jz4725b_lcd_8bit_pins[] = { 255 0x72, 0x73, 0x74, 256 0x60, 0x61, 0x62, 0x63, 257 0x64, 0x65, 0x66, 0x67, 258 }; 259 static int jz4725b_lcd_16bit_pins[] = { 260 0x68, 0x69, 0x6a, 0x6b, 261 0x6c, 0x6d, 0x6e, 0x6f, 262 }; 263 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, }; 264 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 265 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, }; 266 static int jz4725b_lcd_generic_pins[] = { 0x75, }; 267 268 static int jz4725b_mmc0_1bit_funcs[] = { 1, 1, 1, }; 269 static int jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, }; 270 static int jz4725b_mmc1_1bit_funcs[] = { 0, 0, 0, }; 271 static int jz4725b_mmc1_4bit_funcs[] = { 0, 0, 0, }; 272 static int jz4725b_uart_data_funcs[] = { 1, 1, }; 273 static int jz4725b_nand_cs1_funcs[] = { 0, }; 274 static int jz4725b_nand_cs2_funcs[] = { 0, }; 275 static int jz4725b_nand_cs3_funcs[] = { 0, }; 276 static int jz4725b_nand_cs4_funcs[] = { 0, }; 277 static int jz4725b_nand_cle_ale_funcs[] = { 0, 0, }; 278 static int jz4725b_nand_fre_fwe_funcs[] = { 0, 0, }; 279 static int jz4725b_pwm_pwm0_funcs[] = { 0, }; 280 static int jz4725b_pwm_pwm1_funcs[] = { 0, }; 281 static int jz4725b_pwm_pwm2_funcs[] = { 0, }; 282 static int jz4725b_pwm_pwm3_funcs[] = { 0, }; 283 static int jz4725b_pwm_pwm4_funcs[] = { 0, }; 284 static int jz4725b_pwm_pwm5_funcs[] = { 0, }; 285 static int jz4725b_lcd_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 286 static int jz4725b_lcd_16bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 287 static int jz4725b_lcd_18bit_funcs[] = { 0, 0, }; 288 static int jz4725b_lcd_24bit_funcs[] = { 1, 1, 1, 1, }; 289 static int jz4725b_lcd_special_funcs[] = { 0, 0, 0, 0, }; 290 static int jz4725b_lcd_generic_funcs[] = { 0, }; 291 292 static const struct group_desc jz4725b_groups[] = { 293 INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit), 294 INGENIC_PIN_GROUP("mmc0-4bit", jz4725b_mmc0_4bit), 295 INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit), 296 INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit), 297 INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data), 298 INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1), 299 INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2), 300 INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3), 301 INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4), 302 INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale), 303 INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe), 304 INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0), 305 INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1), 306 INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2), 307 INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3), 308 INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4), 309 INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5), 310 INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit), 311 INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit), 312 INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit), 313 INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit), 314 INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special), 315 INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic), 316 }; 317 318 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 319 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 320 static const char *jz4725b_uart_groups[] = { "uart-data", }; 321 static const char *jz4725b_nand_groups[] = { 322 "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", 323 "nand-cle-ale", "nand-fre-fwe", 324 }; 325 static const char *jz4725b_pwm0_groups[] = { "pwm0", }; 326 static const char *jz4725b_pwm1_groups[] = { "pwm1", }; 327 static const char *jz4725b_pwm2_groups[] = { "pwm2", }; 328 static const char *jz4725b_pwm3_groups[] = { "pwm3", }; 329 static const char *jz4725b_pwm4_groups[] = { "pwm4", }; 330 static const char *jz4725b_pwm5_groups[] = { "pwm5", }; 331 static const char *jz4725b_lcd_groups[] = { 332 "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit", 333 "lcd-special", "lcd-generic", 334 }; 335 336 static const struct function_desc jz4725b_functions[] = { 337 { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), }, 338 { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), }, 339 { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), }, 340 { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), }, 341 { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), }, 342 { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), }, 343 { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), }, 344 { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), }, 345 { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), }, 346 { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), }, 347 { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), }, 348 }; 349 350 static const struct ingenic_chip_info jz4725b_chip_info = { 351 .num_chips = 4, 352 .reg_offset = 0x100, 353 .version = ID_JZ4725B, 354 .groups = jz4725b_groups, 355 .num_groups = ARRAY_SIZE(jz4725b_groups), 356 .functions = jz4725b_functions, 357 .num_functions = ARRAY_SIZE(jz4725b_functions), 358 .pull_ups = jz4740_pull_ups, 359 .pull_downs = jz4740_pull_downs, 360 }; 361 362 static const u32 jz4760_pull_ups[6] = { 363 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, 364 }; 365 366 static const u32 jz4760_pull_downs[6] = { 367 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, 368 }; 369 370 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; 371 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 372 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; 373 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 374 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; 375 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 376 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; 377 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; 378 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 379 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 380 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 381 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 382 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 383 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 384 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 385 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 386 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 387 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 388 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 389 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 390 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 391 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 392 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 393 static int jz4760_nemc_8bit_data_pins[] = { 394 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 395 }; 396 static int jz4760_nemc_16bit_data_pins[] = { 397 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 398 }; 399 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 400 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 401 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; 402 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 403 static int jz4760_nemc_wait_pins[] = { 0x1b, }; 404 static int jz4760_nemc_cs1_pins[] = { 0x15, }; 405 static int jz4760_nemc_cs2_pins[] = { 0x16, }; 406 static int jz4760_nemc_cs3_pins[] = { 0x17, }; 407 static int jz4760_nemc_cs4_pins[] = { 0x18, }; 408 static int jz4760_nemc_cs5_pins[] = { 0x19, }; 409 static int jz4760_nemc_cs6_pins[] = { 0x1a, }; 410 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; 411 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; 412 static int jz4760_cim_pins[] = { 413 0x26, 0x27, 0x28, 0x29, 414 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 415 }; 416 static int jz4760_lcd_24bit_pins[] = { 417 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 418 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 419 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 420 0x58, 0x59, 0x5a, 0x5b, 421 }; 422 static int jz4760_pwm_pwm0_pins[] = { 0x80, }; 423 static int jz4760_pwm_pwm1_pins[] = { 0x81, }; 424 static int jz4760_pwm_pwm2_pins[] = { 0x82, }; 425 static int jz4760_pwm_pwm3_pins[] = { 0x83, }; 426 static int jz4760_pwm_pwm4_pins[] = { 0x84, }; 427 static int jz4760_pwm_pwm5_pins[] = { 0x85, }; 428 static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; 429 static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; 430 431 static int jz4760_uart0_data_funcs[] = { 0, 0, }; 432 static int jz4760_uart0_hwflow_funcs[] = { 0, 0, }; 433 static int jz4760_uart1_data_funcs[] = { 0, 0, }; 434 static int jz4760_uart1_hwflow_funcs[] = { 0, 0, }; 435 static int jz4760_uart2_data_funcs[] = { 0, 0, }; 436 static int jz4760_uart2_hwflow_funcs[] = { 0, 0, }; 437 static int jz4760_uart3_data_funcs[] = { 0, 1, }; 438 static int jz4760_uart3_hwflow_funcs[] = { 0, 0, }; 439 static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 440 static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; 441 static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; 442 static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; 443 static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; 444 static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; 445 static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; 446 static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; 447 static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; 448 static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; 449 static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; 450 static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; 451 static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; 452 static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; 453 static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; 454 static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 455 static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 456 static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, }; 457 static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, }; 458 static int jz4760_nemc_rd_we_funcs[] = { 0, 0, }; 459 static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, }; 460 static int jz4760_nemc_wait_funcs[] = { 0, }; 461 static int jz4760_nemc_cs1_funcs[] = { 0, }; 462 static int jz4760_nemc_cs2_funcs[] = { 0, }; 463 static int jz4760_nemc_cs3_funcs[] = { 0, }; 464 static int jz4760_nemc_cs4_funcs[] = { 0, }; 465 static int jz4760_nemc_cs5_funcs[] = { 0, }; 466 static int jz4760_nemc_cs6_funcs[] = { 0, }; 467 static int jz4760_i2c0_funcs[] = { 0, 0, }; 468 static int jz4760_i2c1_funcs[] = { 0, 0, }; 469 static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 470 static int jz4760_lcd_24bit_funcs[] = { 471 0, 0, 0, 0, 0, 0, 0, 0, 472 0, 0, 0, 0, 0, 0, 0, 0, 473 0, 0, 0, 0, 0, 0, 0, 0, 474 0, 0, 0, 0, 475 }; 476 static int jz4760_pwm_pwm0_funcs[] = { 0, }; 477 static int jz4760_pwm_pwm1_funcs[] = { 0, }; 478 static int jz4760_pwm_pwm2_funcs[] = { 0, }; 479 static int jz4760_pwm_pwm3_funcs[] = { 0, }; 480 static int jz4760_pwm_pwm4_funcs[] = { 0, }; 481 static int jz4760_pwm_pwm5_funcs[] = { 0, }; 482 static int jz4760_pwm_pwm6_funcs[] = { 0, }; 483 static int jz4760_pwm_pwm7_funcs[] = { 0, }; 484 485 static const struct group_desc jz4760_groups[] = { 486 INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data), 487 INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow), 488 INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data), 489 INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow), 490 INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data), 491 INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow), 492 INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data), 493 INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow), 494 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a), 495 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a), 496 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e), 497 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e), 498 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e), 499 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d), 500 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d), 501 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e), 502 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e), 503 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e), 504 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b), 505 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b), 506 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e), 507 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e), 508 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e), 509 INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data), 510 INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data), 511 INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale), 512 INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr), 513 INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we), 514 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe), 515 INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait), 516 INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1), 517 INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2), 518 INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3), 519 INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4), 520 INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5), 521 INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6), 522 INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0), 523 INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1), 524 INGENIC_PIN_GROUP("cim-data", jz4760_cim), 525 INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit), 526 { "lcd-no-pins", }, 527 INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0), 528 INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1), 529 INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2), 530 INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3), 531 INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4), 532 INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5), 533 INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6), 534 INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7), 535 }; 536 537 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 538 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 539 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 540 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 541 static const char *jz4760_mmc0_groups[] = { 542 "mmc0-1bit-a", "mmc0-4bit-a", 543 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 544 }; 545 static const char *jz4760_mmc1_groups[] = { 546 "mmc1-1bit-d", "mmc1-4bit-d", 547 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 548 }; 549 static const char *jz4760_mmc2_groups[] = { 550 "mmc2-1bit-b", "mmc2-4bit-b", 551 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 552 }; 553 static const char *jz4760_nemc_groups[] = { 554 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 555 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 556 }; 557 static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; 558 static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; 559 static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; 560 static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; 561 static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; 562 static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; 563 static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; 564 static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; 565 static const char *jz4760_cim_groups[] = { "cim-data", }; 566 static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; 567 static const char *jz4760_pwm0_groups[] = { "pwm0", }; 568 static const char *jz4760_pwm1_groups[] = { "pwm1", }; 569 static const char *jz4760_pwm2_groups[] = { "pwm2", }; 570 static const char *jz4760_pwm3_groups[] = { "pwm3", }; 571 static const char *jz4760_pwm4_groups[] = { "pwm4", }; 572 static const char *jz4760_pwm5_groups[] = { "pwm5", }; 573 static const char *jz4760_pwm6_groups[] = { "pwm6", }; 574 static const char *jz4760_pwm7_groups[] = { "pwm7", }; 575 576 static const struct function_desc jz4760_functions[] = { 577 { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, 578 { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, 579 { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, 580 { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, 581 { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, 582 { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, 583 { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, 584 { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, 585 { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, 586 { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, 587 { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, 588 { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, 589 { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, 590 { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, 591 { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, 592 { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, 593 { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, 594 { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, 595 { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, 596 { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, 597 { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, 598 { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, 599 { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, 600 { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, 601 { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, 602 { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, 603 }; 604 605 static const struct ingenic_chip_info jz4760_chip_info = { 606 .num_chips = 6, 607 .reg_offset = 0x100, 608 .version = ID_JZ4760, 609 .groups = jz4760_groups, 610 .num_groups = ARRAY_SIZE(jz4760_groups), 611 .functions = jz4760_functions, 612 .num_functions = ARRAY_SIZE(jz4760_functions), 613 .pull_ups = jz4760_pull_ups, 614 .pull_downs = jz4760_pull_downs, 615 }; 616 617 static const u32 jz4770_pull_ups[6] = { 618 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, 619 }; 620 621 static const u32 jz4770_pull_downs[6] = { 622 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, 623 }; 624 625 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, }; 626 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; 627 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, }; 628 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; 629 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; 630 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; 631 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; 632 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; 633 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; 634 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; 635 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 636 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 637 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 638 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; 639 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; 640 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 641 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 642 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 643 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; 644 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; 645 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; 646 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; 647 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; 648 static int jz4770_nemc_8bit_data_pins[] = { 649 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 650 }; 651 static int jz4770_nemc_16bit_data_pins[] = { 652 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 653 }; 654 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, }; 655 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; 656 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, }; 657 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; 658 static int jz4770_nemc_wait_pins[] = { 0x1b, }; 659 static int jz4770_nemc_cs1_pins[] = { 0x15, }; 660 static int jz4770_nemc_cs2_pins[] = { 0x16, }; 661 static int jz4770_nemc_cs3_pins[] = { 0x17, }; 662 static int jz4770_nemc_cs4_pins[] = { 0x18, }; 663 static int jz4770_nemc_cs5_pins[] = { 0x19, }; 664 static int jz4770_nemc_cs6_pins[] = { 0x1a, }; 665 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, }; 666 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, }; 667 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, }; 668 static int jz4770_cim_8bit_pins[] = { 669 0x26, 0x27, 0x28, 0x29, 670 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 671 }; 672 static int jz4770_cim_12bit_pins[] = { 673 0x32, 0x33, 0xb0, 0xb1, 674 }; 675 static int jz4770_lcd_24bit_pins[] = { 676 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 677 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 678 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 679 0x58, 0x59, 0x5a, 0x5b, 680 }; 681 static int jz4770_pwm_pwm0_pins[] = { 0x80, }; 682 static int jz4770_pwm_pwm1_pins[] = { 0x81, }; 683 static int jz4770_pwm_pwm2_pins[] = { 0x82, }; 684 static int jz4770_pwm_pwm3_pins[] = { 0x83, }; 685 static int jz4770_pwm_pwm4_pins[] = { 0x84, }; 686 static int jz4770_pwm_pwm5_pins[] = { 0x85, }; 687 static int jz4770_pwm_pwm6_pins[] = { 0x6a, }; 688 static int jz4770_pwm_pwm7_pins[] = { 0x6b, }; 689 static int jz4770_mac_rmii_pins[] = { 690 0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8, 691 }; 692 static int jz4770_mac_mii_pins[] = { 0xa7, 0xaf, }; 693 static int jz4770_otg_pins[] = { 0x8a, }; 694 695 static int jz4770_uart0_data_funcs[] = { 0, 0, }; 696 static int jz4770_uart0_hwflow_funcs[] = { 0, 0, }; 697 static int jz4770_uart1_data_funcs[] = { 0, 0, }; 698 static int jz4770_uart1_hwflow_funcs[] = { 0, 0, }; 699 static int jz4770_uart2_data_funcs[] = { 0, 0, }; 700 static int jz4770_uart2_hwflow_funcs[] = { 0, 0, }; 701 static int jz4770_uart3_data_funcs[] = { 0, 1, }; 702 static int jz4770_uart3_hwflow_funcs[] = { 0, 0, }; 703 static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; 704 static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; 705 static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; 706 static int jz4770_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; 707 static int jz4770_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; 708 static int jz4770_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; 709 static int jz4770_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; 710 static int jz4770_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; 711 static int jz4770_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; 712 static int jz4770_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; 713 static int jz4770_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; 714 static int jz4770_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; 715 static int jz4770_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; 716 static int jz4770_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; 717 static int jz4770_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; 718 static int jz4770_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 719 static int jz4770_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 720 static int jz4770_nemc_cle_ale_funcs[] = { 0, 0, }; 721 static int jz4770_nemc_addr_funcs[] = { 0, 0, 0, 0, }; 722 static int jz4770_nemc_rd_we_funcs[] = { 0, 0, }; 723 static int jz4770_nemc_frd_fwe_funcs[] = { 0, 0, }; 724 static int jz4770_nemc_wait_funcs[] = { 0, }; 725 static int jz4770_nemc_cs1_funcs[] = { 0, }; 726 static int jz4770_nemc_cs2_funcs[] = { 0, }; 727 static int jz4770_nemc_cs3_funcs[] = { 0, }; 728 static int jz4770_nemc_cs4_funcs[] = { 0, }; 729 static int jz4770_nemc_cs5_funcs[] = { 0, }; 730 static int jz4770_nemc_cs6_funcs[] = { 0, }; 731 static int jz4770_i2c0_funcs[] = { 0, 0, }; 732 static int jz4770_i2c1_funcs[] = { 0, 0, }; 733 static int jz4770_i2c2_funcs[] = { 2, 2, }; 734 static int jz4770_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 735 static int jz4770_cim_12bit_funcs[] = { 0, 0, 0, 0, }; 736 static int jz4770_lcd_24bit_funcs[] = { 737 0, 0, 0, 0, 0, 0, 0, 0, 738 0, 0, 0, 0, 0, 0, 0, 0, 739 0, 0, 0, 0, 0, 0, 0, 0, 740 0, 0, 0, 0, 741 }; 742 static int jz4770_pwm_pwm0_funcs[] = { 0, }; 743 static int jz4770_pwm_pwm1_funcs[] = { 0, }; 744 static int jz4770_pwm_pwm2_funcs[] = { 0, }; 745 static int jz4770_pwm_pwm3_funcs[] = { 0, }; 746 static int jz4770_pwm_pwm4_funcs[] = { 0, }; 747 static int jz4770_pwm_pwm5_funcs[] = { 0, }; 748 static int jz4770_pwm_pwm6_funcs[] = { 0, }; 749 static int jz4770_pwm_pwm7_funcs[] = { 0, }; 750 static int jz4770_mac_rmii_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 751 static int jz4770_mac_mii_funcs[] = { 0, 0, }; 752 static int jz4770_otg_funcs[] = { 0, }; 753 754 static const struct group_desc jz4770_groups[] = { 755 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), 756 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), 757 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), 758 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), 759 INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data), 760 INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow), 761 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), 762 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), 763 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), 764 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), 765 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), 766 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), 767 INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e), 768 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), 769 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), 770 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), 771 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), 772 INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e), 773 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), 774 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), 775 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), 776 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), 777 INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e), 778 INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data), 779 INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data), 780 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), 781 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), 782 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), 783 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), 784 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), 785 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), 786 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), 787 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), 788 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), 789 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), 790 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), 791 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), 792 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), 793 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), 794 INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit), 795 INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit), 796 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), 797 { "lcd-no-pins", }, 798 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), 799 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), 800 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), 801 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), 802 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), 803 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), 804 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), 805 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), 806 INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii), 807 INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii), 808 INGENIC_PIN_GROUP("otg-vbus", jz4770_otg), 809 }; 810 811 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 812 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; 813 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 814 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; 815 static const char *jz4770_mmc0_groups[] = { 816 "mmc0-1bit-a", "mmc0-4bit-a", 817 "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", 818 }; 819 static const char *jz4770_mmc1_groups[] = { 820 "mmc1-1bit-d", "mmc1-4bit-d", 821 "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", 822 }; 823 static const char *jz4770_mmc2_groups[] = { 824 "mmc2-1bit-b", "mmc2-4bit-b", 825 "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", 826 }; 827 static const char *jz4770_nemc_groups[] = { 828 "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", 829 "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 830 }; 831 static const char *jz4770_cs1_groups[] = { "nemc-cs1", }; 832 static const char *jz4770_cs2_groups[] = { "nemc-cs2", }; 833 static const char *jz4770_cs3_groups[] = { "nemc-cs3", }; 834 static const char *jz4770_cs4_groups[] = { "nemc-cs4", }; 835 static const char *jz4770_cs5_groups[] = { "nemc-cs5", }; 836 static const char *jz4770_cs6_groups[] = { "nemc-cs6", }; 837 static const char *jz4770_i2c0_groups[] = { "i2c0-data", }; 838 static const char *jz4770_i2c1_groups[] = { "i2c1-data", }; 839 static const char *jz4770_i2c2_groups[] = { "i2c2-data", }; 840 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", }; 841 static const char *jz4770_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; 842 static const char *jz4770_pwm0_groups[] = { "pwm0", }; 843 static const char *jz4770_pwm1_groups[] = { "pwm1", }; 844 static const char *jz4770_pwm2_groups[] = { "pwm2", }; 845 static const char *jz4770_pwm3_groups[] = { "pwm3", }; 846 static const char *jz4770_pwm4_groups[] = { "pwm4", }; 847 static const char *jz4770_pwm5_groups[] = { "pwm5", }; 848 static const char *jz4770_pwm6_groups[] = { "pwm6", }; 849 static const char *jz4770_pwm7_groups[] = { "pwm7", }; 850 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", }; 851 static const char *jz4770_otg_groups[] = { "otg-vbus", }; 852 853 static const struct function_desc jz4770_functions[] = { 854 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 855 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 856 { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, 857 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 858 { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, 859 { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, 860 { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, 861 { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), }, 862 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 863 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 864 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 865 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 866 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 867 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 868 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 869 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 870 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 871 { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), }, 872 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 873 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 874 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 875 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 876 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 877 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 878 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 879 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 880 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 881 { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), }, 882 { "otg", jz4770_otg_groups, ARRAY_SIZE(jz4770_otg_groups), }, 883 }; 884 885 static const struct ingenic_chip_info jz4770_chip_info = { 886 .num_chips = 6, 887 .reg_offset = 0x100, 888 .version = ID_JZ4770, 889 .groups = jz4770_groups, 890 .num_groups = ARRAY_SIZE(jz4770_groups), 891 .functions = jz4770_functions, 892 .num_functions = ARRAY_SIZE(jz4770_functions), 893 .pull_ups = jz4770_pull_ups, 894 .pull_downs = jz4770_pull_downs, 895 }; 896 897 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; 898 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; 899 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; 900 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; 901 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; 902 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; 903 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; 904 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; 905 906 static int jz4780_uart2_data_funcs[] = { 1, 1, }; 907 static int jz4780_uart2_hwflow_funcs[] = { 1, 1, }; 908 static int jz4780_uart4_data_funcs[] = { 2, 2, }; 909 static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, }; 910 static int jz4780_i2c3_funcs[] = { 1, 1, }; 911 static int jz4780_i2c4_e_funcs[] = { 1, 1, }; 912 static int jz4780_i2c4_f_funcs[] = { 1, 1, }; 913 static int jz4780_hdmi_ddc_funcs[] = { 0, 0, }; 914 915 static const struct group_desc jz4780_groups[] = { 916 INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data), 917 INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow), 918 INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data), 919 INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow), 920 INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data), 921 INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow), 922 INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), 923 INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), 924 INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data), 925 INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), 926 INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), 927 INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a), 928 INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), 929 INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e), 930 INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d), 931 INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d), 932 INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e), 933 INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e), 934 INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b), 935 INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b), 936 INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e), 937 INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e), 938 INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data), 939 INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale), 940 INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr), 941 INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we), 942 INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe), 943 INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait), 944 INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1), 945 INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2), 946 INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3), 947 INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4), 948 INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5), 949 INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6), 950 INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0), 951 INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1), 952 INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2), 953 INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3), 954 INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e), 955 INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f), 956 INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc), 957 INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit), 958 INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), 959 { "lcd-no-pins", }, 960 INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0), 961 INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1), 962 INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2), 963 INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3), 964 INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4), 965 INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5), 966 INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6), 967 INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7), 968 }; 969 970 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; 971 static const char *jz4780_uart4_groups[] = { "uart4-data", }; 972 static const char *jz4780_mmc0_groups[] = { 973 "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", 974 "mmc0-1bit-e", "mmc0-4bit-e", 975 }; 976 static const char *jz4780_mmc1_groups[] = { 977 "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e", 978 }; 979 static const char *jz4780_mmc2_groups[] = { 980 "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e", 981 }; 982 static const char *jz4780_nemc_groups[] = { 983 "nemc-data", "nemc-cle-ale", "nemc-addr", 984 "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", 985 }; 986 static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; 987 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; 988 static const char *jz4780_cim_groups[] = { "cim-data", }; 989 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; 990 991 static const struct function_desc jz4780_functions[] = { 992 { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), }, 993 { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, 994 { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, 995 { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, 996 { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, 997 { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, 998 { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, 999 { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, 1000 { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), }, 1001 { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), }, 1002 { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), }, 1003 { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), }, 1004 { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), }, 1005 { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), }, 1006 { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), }, 1007 { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), }, 1008 { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), }, 1009 { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, 1010 { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, 1011 { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, 1012 { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, 1013 { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, 1014 { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, 1015 { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), }, 1016 { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), }, 1017 { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), }, 1018 { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), }, 1019 { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), }, 1020 { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), }, 1021 { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), }, 1022 { "hdmi-ddc", jz4780_hdmi_ddc_groups, 1023 ARRAY_SIZE(jz4780_hdmi_ddc_groups), }, 1024 }; 1025 1026 static const struct ingenic_chip_info jz4780_chip_info = { 1027 .num_chips = 6, 1028 .reg_offset = 0x100, 1029 .version = ID_JZ4780, 1030 .groups = jz4780_groups, 1031 .num_groups = ARRAY_SIZE(jz4780_groups), 1032 .functions = jz4780_functions, 1033 .num_functions = ARRAY_SIZE(jz4780_functions), 1034 .pull_ups = jz4770_pull_ups, 1035 .pull_downs = jz4770_pull_downs, 1036 }; 1037 1038 static const u32 x1000_pull_ups[4] = { 1039 0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f, 1040 }; 1041 1042 static const u32 x1000_pull_downs[4] = { 1043 0x00000000, 0x02000000, 0x02000000, 0x00000000, 1044 }; 1045 1046 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; 1047 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1048 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; 1049 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; 1050 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1051 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; 1052 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; 1053 static int x1000_sfc_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, }; 1054 static int x1000_ssi_dt_a_22_pins[] = { 0x16, }; 1055 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, }; 1056 static int x1000_ssi_dt_d_pins[] = { 0x62, }; 1057 static int x1000_ssi_dr_a_23_pins[] = { 0x17, }; 1058 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, }; 1059 static int x1000_ssi_dr_d_pins[] = { 0x63, }; 1060 static int x1000_ssi_clk_a_24_pins[] = { 0x18, }; 1061 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, }; 1062 static int x1000_ssi_clk_d_pins[] = { 0x60, }; 1063 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, }; 1064 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, }; 1065 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, }; 1066 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, }; 1067 static int x1000_ssi_ce0_d_pins[] = { 0x61, }; 1068 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, }; 1069 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, }; 1070 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1071 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1072 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; 1073 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; 1074 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; 1075 static int x1000_emc_8bit_data_pins[] = { 1076 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1077 }; 1078 static int x1000_emc_16bit_data_pins[] = { 1079 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1080 }; 1081 static int x1000_emc_addr_pins[] = { 1082 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 1083 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 1084 }; 1085 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, }; 1086 static int x1000_emc_wait_pins[] = { 0x34, }; 1087 static int x1000_emc_cs1_pins[] = { 0x32, }; 1088 static int x1000_emc_cs2_pins[] = { 0x33, }; 1089 static int x1000_i2c0_pins[] = { 0x38, 0x37, }; 1090 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; 1091 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1092 static int x1000_i2c2_pins[] = { 0x61, 0x60, }; 1093 static int x1000_cim_pins[] = { 1094 0x08, 0x09, 0x0a, 0x0b, 1095 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1096 }; 1097 static int x1000_lcd_8bit_pins[] = { 1098 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 1099 0x30, 0x31, 0x32, 0x33, 0x34, 1100 }; 1101 static int x1000_lcd_16bit_pins[] = { 1102 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 1103 }; 1104 static int x1000_pwm_pwm0_pins[] = { 0x59, }; 1105 static int x1000_pwm_pwm1_pins[] = { 0x5a, }; 1106 static int x1000_pwm_pwm2_pins[] = { 0x5b, }; 1107 static int x1000_pwm_pwm3_pins[] = { 0x26, }; 1108 static int x1000_pwm_pwm4_pins[] = { 0x58, }; 1109 static int x1000_mac_pins[] = { 1110 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, 1111 }; 1112 1113 static int x1000_uart0_data_funcs[] = { 0, 0, }; 1114 static int x1000_uart0_hwflow_funcs[] = { 0, 0, }; 1115 static int x1000_uart1_data_a_funcs[] = { 2, 2, }; 1116 static int x1000_uart1_data_d_funcs[] = { 1, 1, }; 1117 static int x1000_uart1_hwflow_funcs[] = { 1, 1, }; 1118 static int x1000_uart2_data_a_funcs[] = { 2, 2, }; 1119 static int x1000_uart2_data_d_funcs[] = { 0, 0, }; 1120 static int x1000_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; 1121 static int x1000_ssi_dt_a_22_funcs[] = { 2, }; 1122 static int x1000_ssi_dt_a_29_funcs[] = { 2, }; 1123 static int x1000_ssi_dt_d_funcs[] = { 0, }; 1124 static int x1000_ssi_dr_a_23_funcs[] = { 2, }; 1125 static int x1000_ssi_dr_a_28_funcs[] = { 2, }; 1126 static int x1000_ssi_dr_d_funcs[] = { 0, }; 1127 static int x1000_ssi_clk_a_24_funcs[] = { 2, }; 1128 static int x1000_ssi_clk_a_26_funcs[] = { 2, }; 1129 static int x1000_ssi_clk_d_funcs[] = { 0, }; 1130 static int x1000_ssi_gpc_a_20_funcs[] = { 2, }; 1131 static int x1000_ssi_gpc_a_31_funcs[] = { 2, }; 1132 static int x1000_ssi_ce0_a_25_funcs[] = { 2, }; 1133 static int x1000_ssi_ce0_a_27_funcs[] = { 2, }; 1134 static int x1000_ssi_ce0_d_funcs[] = { 0, }; 1135 static int x1000_ssi_ce1_a_21_funcs[] = { 2, }; 1136 static int x1000_ssi_ce1_a_30_funcs[] = { 2, }; 1137 static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; 1138 static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; 1139 static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; 1140 static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, }; 1141 static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, }; 1142 static int x1000_emc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 1143 static int x1000_emc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; 1144 static int x1000_emc_addr_funcs[] = { 1145 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1146 }; 1147 static int x1000_emc_rd_we_funcs[] = { 0, 0, }; 1148 static int x1000_emc_wait_funcs[] = { 0, }; 1149 static int x1000_emc_cs1_funcs[] = { 0, }; 1150 static int x1000_emc_cs2_funcs[] = { 0, }; 1151 static int x1000_i2c0_funcs[] = { 0, 0, }; 1152 static int x1000_i2c1_a_funcs[] = { 2, 2, }; 1153 static int x1000_i2c1_c_funcs[] = { 0, 0, }; 1154 static int x1000_i2c2_funcs[] = { 1, 1, }; 1155 static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 1156 static int x1000_lcd_8bit_funcs[] = { 1157 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1158 }; 1159 static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; 1160 static int x1000_pwm_pwm0_funcs[] = { 0, }; 1161 static int x1000_pwm_pwm1_funcs[] = { 1, }; 1162 static int x1000_pwm_pwm2_funcs[] = { 1, }; 1163 static int x1000_pwm_pwm3_funcs[] = { 2, }; 1164 static int x1000_pwm_pwm4_funcs[] = { 0, }; 1165 static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; 1166 1167 static const struct group_desc x1000_groups[] = { 1168 INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data), 1169 INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow), 1170 INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a), 1171 INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d), 1172 INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow), 1173 INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), 1174 INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), 1175 INGENIC_PIN_GROUP("sfc", x1000_sfc), 1176 INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22), 1177 INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29), 1178 INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d), 1179 INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23), 1180 INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28), 1181 INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d), 1182 INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24), 1183 INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26), 1184 INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d), 1185 INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20), 1186 INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31), 1187 INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25), 1188 INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27), 1189 INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d), 1190 INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21), 1191 INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30), 1192 INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), 1193 INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit), 1194 INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), 1195 INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit), 1196 INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit), 1197 INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data), 1198 INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data), 1199 INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr), 1200 INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we), 1201 INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait), 1202 INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1), 1203 INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2), 1204 INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0), 1205 INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a), 1206 INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c), 1207 INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2), 1208 INGENIC_PIN_GROUP("cim-data", x1000_cim), 1209 INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit), 1210 INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit), 1211 { "lcd-no-pins", }, 1212 INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0), 1213 INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1), 1214 INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2), 1215 INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3), 1216 INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4), 1217 INGENIC_PIN_GROUP("mac", x1000_mac), 1218 }; 1219 1220 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1221 static const char *x1000_uart1_groups[] = { 1222 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1223 }; 1224 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1225 static const char *x1000_sfc_groups[] = { "sfc", }; 1226 static const char *x1000_ssi_groups[] = { 1227 "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d", 1228 "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d", 1229 "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d", 1230 "ssi-gpc-a-20", "ssi-gpc-a-31", 1231 "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d", 1232 "ssi-ce1-a-21", "ssi-ce1-a-30", 1233 }; 1234 static const char *x1000_mmc0_groups[] = { 1235 "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", 1236 }; 1237 static const char *x1000_mmc1_groups[] = { 1238 "mmc1-1bit", "mmc1-4bit", 1239 }; 1240 static const char *x1000_emc_groups[] = { 1241 "emc-8bit-data", "emc-16bit-data", 1242 "emc-addr", "emc-rd-we", "emc-wait", 1243 }; 1244 static const char *x1000_cs1_groups[] = { "emc-cs1", }; 1245 static const char *x1000_cs2_groups[] = { "emc-cs2", }; 1246 static const char *x1000_i2c0_groups[] = { "i2c0-data", }; 1247 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1248 static const char *x1000_i2c2_groups[] = { "i2c2-data", }; 1249 static const char *x1000_cim_groups[] = { "cim-data", }; 1250 static const char *x1000_lcd_groups[] = { 1251 "lcd-8bit", "lcd-16bit", "lcd-no-pins", 1252 }; 1253 static const char *x1000_pwm0_groups[] = { "pwm0", }; 1254 static const char *x1000_pwm1_groups[] = { "pwm1", }; 1255 static const char *x1000_pwm2_groups[] = { "pwm2", }; 1256 static const char *x1000_pwm3_groups[] = { "pwm3", }; 1257 static const char *x1000_pwm4_groups[] = { "pwm4", }; 1258 static const char *x1000_mac_groups[] = { "mac", }; 1259 1260 static const struct function_desc x1000_functions[] = { 1261 { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, 1262 { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, 1263 { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, 1264 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1265 { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), }, 1266 { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, 1267 { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, 1268 { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), }, 1269 { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, 1270 { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, 1271 { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, 1272 { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, 1273 { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, 1274 { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, 1275 { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, 1276 { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, 1277 { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, 1278 { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, 1279 { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, 1280 { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, 1281 { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, 1282 }; 1283 1284 static const struct ingenic_chip_info x1000_chip_info = { 1285 .num_chips = 4, 1286 .reg_offset = 0x100, 1287 .version = ID_X1000, 1288 .groups = x1000_groups, 1289 .num_groups = ARRAY_SIZE(x1000_groups), 1290 .functions = x1000_functions, 1291 .num_functions = ARRAY_SIZE(x1000_functions), 1292 .pull_ups = x1000_pull_ups, 1293 .pull_downs = x1000_pull_downs, 1294 }; 1295 1296 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; 1297 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; 1298 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; 1299 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; 1300 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, }; 1301 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; 1302 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; 1303 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, }; 1304 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, }; 1305 static int x1500_i2c0_pins[] = { 0x38, 0x37, }; 1306 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; 1307 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; 1308 static int x1500_i2c2_pins[] = { 0x61, 0x60, }; 1309 static int x1500_cim_pins[] = { 1310 0x08, 0x09, 0x0a, 0x0b, 1311 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, 1312 }; 1313 static int x1500_pwm_pwm0_pins[] = { 0x59, }; 1314 static int x1500_pwm_pwm1_pins[] = { 0x5a, }; 1315 static int x1500_pwm_pwm2_pins[] = { 0x5b, }; 1316 static int x1500_pwm_pwm3_pins[] = { 0x26, }; 1317 static int x1500_pwm_pwm4_pins[] = { 0x58, }; 1318 1319 static int x1500_uart0_data_funcs[] = { 0, 0, }; 1320 static int x1500_uart0_hwflow_funcs[] = { 0, 0, }; 1321 static int x1500_uart1_data_a_funcs[] = { 2, 2, }; 1322 static int x1500_uart1_data_d_funcs[] = { 1, 1, }; 1323 static int x1500_uart1_hwflow_funcs[] = { 1, 1, }; 1324 static int x1500_uart2_data_a_funcs[] = { 2, 2, }; 1325 static int x1500_uart2_data_d_funcs[] = { 0, 0, }; 1326 static int x1500_mmc_1bit_funcs[] = { 1, 1, 1, }; 1327 static int x1500_mmc_4bit_funcs[] = { 1, 1, 1, }; 1328 static int x1500_i2c0_funcs[] = { 0, 0, }; 1329 static int x1500_i2c1_a_funcs[] = { 2, 2, }; 1330 static int x1500_i2c1_c_funcs[] = { 0, 0, }; 1331 static int x1500_i2c2_funcs[] = { 1, 1, }; 1332 static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 1333 static int x1500_pwm_pwm0_funcs[] = { 0, }; 1334 static int x1500_pwm_pwm1_funcs[] = { 1, }; 1335 static int x1500_pwm_pwm2_funcs[] = { 1, }; 1336 static int x1500_pwm_pwm3_funcs[] = { 2, }; 1337 static int x1500_pwm_pwm4_funcs[] = { 0, }; 1338 1339 static const struct group_desc x1500_groups[] = { 1340 INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data), 1341 INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow), 1342 INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a), 1343 INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d), 1344 INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow), 1345 INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), 1346 INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), 1347 INGENIC_PIN_GROUP("sfc", x1000_sfc), 1348 INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit), 1349 INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit), 1350 INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), 1351 INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a), 1352 INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c), 1353 INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2), 1354 INGENIC_PIN_GROUP("cim-data", x1500_cim), 1355 { "lcd-no-pins", }, 1356 INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0), 1357 INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1), 1358 INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2), 1359 INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3), 1360 INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4), 1361 }; 1362 1363 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1364 static const char *x1500_uart1_groups[] = { 1365 "uart1-data-a", "uart1-data-d", "uart1-hwflow", 1366 }; 1367 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; 1368 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; 1369 static const char *x1500_i2c0_groups[] = { "i2c0-data", }; 1370 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; 1371 static const char *x1500_i2c2_groups[] = { "i2c2-data", }; 1372 static const char *x1500_cim_groups[] = { "cim-data", }; 1373 static const char *x1500_lcd_groups[] = { "lcd-no-pins", }; 1374 static const char *x1500_pwm0_groups[] = { "pwm0", }; 1375 static const char *x1500_pwm1_groups[] = { "pwm1", }; 1376 static const char *x1500_pwm2_groups[] = { "pwm2", }; 1377 static const char *x1500_pwm3_groups[] = { "pwm3", }; 1378 static const char *x1500_pwm4_groups[] = { "pwm4", }; 1379 1380 static const struct function_desc x1500_functions[] = { 1381 { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, 1382 { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, 1383 { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, 1384 { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), }, 1385 { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), }, 1386 { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, 1387 { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, 1388 { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, 1389 { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, 1390 { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), }, 1391 { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, 1392 { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, 1393 { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, 1394 { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, 1395 { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, 1396 }; 1397 1398 static const struct ingenic_chip_info x1500_chip_info = { 1399 .num_chips = 4, 1400 .reg_offset = 0x100, 1401 .version = ID_X1500, 1402 .groups = x1500_groups, 1403 .num_groups = ARRAY_SIZE(x1500_groups), 1404 .functions = x1500_functions, 1405 .num_functions = ARRAY_SIZE(x1500_functions), 1406 .pull_ups = x1000_pull_ups, 1407 .pull_downs = x1000_pull_downs, 1408 }; 1409 1410 static const u32 x1830_pull_ups[4] = { 1411 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1412 }; 1413 1414 static const u32 x1830_pull_downs[4] = { 1415 0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc, 1416 }; 1417 1418 static int x1830_uart0_data_pins[] = { 0x33, 0x36, }; 1419 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, }; 1420 static int x1830_uart1_data_pins[] = { 0x38, 0x37, }; 1421 static int x1830_sfc_pins[] = { 0x17, 0x18, 0x1a, 0x19, 0x1b, 0x1c, }; 1422 static int x1830_ssi0_dt_pins[] = { 0x4c, }; 1423 static int x1830_ssi0_dr_pins[] = { 0x4b, }; 1424 static int x1830_ssi0_clk_pins[] = { 0x4f, }; 1425 static int x1830_ssi0_gpc_pins[] = { 0x4d, }; 1426 static int x1830_ssi0_ce0_pins[] = { 0x50, }; 1427 static int x1830_ssi0_ce1_pins[] = { 0x4e, }; 1428 static int x1830_ssi1_dt_c_pins[] = { 0x53, }; 1429 static int x1830_ssi1_dr_c_pins[] = { 0x54, }; 1430 static int x1830_ssi1_clk_c_pins[] = { 0x57, }; 1431 static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; 1432 static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; 1433 static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; 1434 static int x1830_ssi1_dt_d_pins[] = { 0x62, }; 1435 static int x1830_ssi1_dr_d_pins[] = { 0x63, }; 1436 static int x1830_ssi1_clk_d_pins[] = { 0x66, }; 1437 static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; 1438 static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; 1439 static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; 1440 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; 1441 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; 1442 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, }; 1443 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; 1444 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; 1445 static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; 1446 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; 1447 static int x1830_lcd_rgb_18bit_pins[] = { 1448 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 1449 0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f, 1450 0x70, 0x71, 0x72, 0x73, 0x76, 0x77, 1451 0x78, 0x79, 0x7a, 0x7b, 1452 }; 1453 static int x1830_lcd_slcd_8bit_pins[] = { 1454 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d, 1455 0x69, 0x72, 0x73, 0x7b, 0x7a, 1456 }; 1457 static int x1830_lcd_slcd_16bit_pins[] = { 1458 0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79, 1459 }; 1460 static int x1830_pwm_pwm0_b_pins[] = { 0x31, }; 1461 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, }; 1462 static int x1830_pwm_pwm1_b_pins[] = { 0x32, }; 1463 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, }; 1464 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, }; 1465 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, }; 1466 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, }; 1467 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, }; 1468 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, }; 1469 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, }; 1470 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, }; 1471 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, }; 1472 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, }; 1473 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, }; 1474 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, }; 1475 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, }; 1476 static int x1830_mac_pins[] = { 1477 0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27, 1478 }; 1479 1480 static int x1830_uart0_data_funcs[] = { 0, 0, }; 1481 static int x1830_uart0_hwflow_funcs[] = { 0, 0, }; 1482 static int x1830_uart1_data_funcs[] = { 0, 0, }; 1483 static int x1830_sfc_funcs[] = { 1, 1, 1, 1, 1, 1, }; 1484 static int x1830_ssi0_dt_funcs[] = { 0, }; 1485 static int x1830_ssi0_dr_funcs[] = { 0, }; 1486 static int x1830_ssi0_clk_funcs[] = { 0, }; 1487 static int x1830_ssi0_gpc_funcs[] = { 0, }; 1488 static int x1830_ssi0_ce0_funcs[] = { 0, }; 1489 static int x1830_ssi0_ce1_funcs[] = { 0, }; 1490 static int x1830_ssi1_dt_c_funcs[] = { 1, }; 1491 static int x1830_ssi1_dr_c_funcs[] = { 1, }; 1492 static int x1830_ssi1_clk_c_funcs[] = { 1, }; 1493 static int x1830_ssi1_gpc_c_funcs[] = { 1, }; 1494 static int x1830_ssi1_ce0_c_funcs[] = { 1, }; 1495 static int x1830_ssi1_ce1_c_funcs[] = { 1, }; 1496 static int x1830_ssi1_dt_d_funcs[] = { 2, }; 1497 static int x1830_ssi1_dr_d_funcs[] = { 2, }; 1498 static int x1830_ssi1_clk_d_funcs[] = { 2, }; 1499 static int x1830_ssi1_gpc_d_funcs[] = { 2, }; 1500 static int x1830_ssi1_ce0_d_funcs[] = { 2, }; 1501 static int x1830_ssi1_ce1_d_funcs[] = { 2, }; 1502 static int x1830_mmc0_1bit_funcs[] = { 0, 0, 0, }; 1503 static int x1830_mmc0_4bit_funcs[] = { 0, 0, 0, }; 1504 static int x1830_mmc1_1bit_funcs[] = { 0, 0, 0, }; 1505 static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, }; 1506 static int x1830_i2c0_funcs[] = { 1, 1, }; 1507 static int x1830_i2c1_funcs[] = { 0, 0, }; 1508 static int x1830_i2c2_funcs[] = { 1, 1, }; 1509 static int x1830_lcd_rgb_18bit_funcs[] = { 1510 0, 0, 0, 0, 0, 0, 1511 0, 0, 0, 0, 0, 0, 1512 0, 0, 0, 0, 0, 0, 1513 0, 0, 0, 0, 1514 }; 1515 static int x1830_lcd_slcd_8bit_funcs[] = { 1516 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1517 }; 1518 static int x1830_lcd_slcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; 1519 static int x1830_pwm_pwm0_b_funcs[] = { 0, }; 1520 static int x1830_pwm_pwm0_c_funcs[] = { 1, }; 1521 static int x1830_pwm_pwm1_b_funcs[] = { 0, }; 1522 static int x1830_pwm_pwm1_c_funcs[] = { 1, }; 1523 static int x1830_pwm_pwm2_c_8_funcs[] = { 0, }; 1524 static int x1830_pwm_pwm2_c_13_funcs[] = { 1, }; 1525 static int x1830_pwm_pwm3_c_9_funcs[] = { 0, }; 1526 static int x1830_pwm_pwm3_c_14_funcs[] = { 1, }; 1527 static int x1830_pwm_pwm4_c_15_funcs[] = { 1, }; 1528 static int x1830_pwm_pwm4_c_25_funcs[] = { 0, }; 1529 static int x1830_pwm_pwm5_c_16_funcs[] = { 1, }; 1530 static int x1830_pwm_pwm5_c_26_funcs[] = { 0, }; 1531 static int x1830_pwm_pwm6_c_17_funcs[] = { 1, }; 1532 static int x1830_pwm_pwm6_c_27_funcs[] = { 0, }; 1533 static int x1830_pwm_pwm7_c_18_funcs[] = { 1, }; 1534 static int x1830_pwm_pwm7_c_28_funcs[] = { 0, }; 1535 static int x1830_mac_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; 1536 1537 static const struct group_desc x1830_groups[] = { 1538 INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data), 1539 INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow), 1540 INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data), 1541 INGENIC_PIN_GROUP("sfc", x1830_sfc), 1542 INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt), 1543 INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr), 1544 INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk), 1545 INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc), 1546 INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0), 1547 INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1), 1548 INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c), 1549 INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c), 1550 INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c), 1551 INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c), 1552 INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c), 1553 INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c), 1554 INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d), 1555 INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d), 1556 INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d), 1557 INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d), 1558 INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d), 1559 INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d), 1560 INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit), 1561 INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit), 1562 INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit), 1563 INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit), 1564 INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0), 1565 INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1), 1566 INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2), 1567 INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit), 1568 INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit), 1569 INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit), 1570 { "lcd-no-pins", }, 1571 INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b), 1572 INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c), 1573 INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b), 1574 INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c), 1575 INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8), 1576 INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13), 1577 INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9), 1578 INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14), 1579 INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15), 1580 INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25), 1581 INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16), 1582 INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26), 1583 INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17), 1584 INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27), 1585 INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18), 1586 INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28), 1587 INGENIC_PIN_GROUP("mac", x1830_mac), 1588 }; 1589 1590 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; 1591 static const char *x1830_uart1_groups[] = { "uart1-data", }; 1592 static const char *x1830_sfc_groups[] = { "sfc", }; 1593 static const char *x1830_ssi0_groups[] = { 1594 "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1", 1595 }; 1596 static const char *x1830_ssi1_groups[] = { 1597 "ssi1-dt-c", "ssi1-dt-d", 1598 "ssi1-dr-c", "ssi1-dr-d", 1599 "ssi1-clk-c", "ssi1-clk-d", 1600 "ssi1-gpc-c", "ssi1-gpc-d", 1601 "ssi1-ce0-c", "ssi1-ce0-d", 1602 "ssi1-ce1-c", "ssi1-ce1-d", 1603 }; 1604 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; 1605 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; 1606 static const char *x1830_i2c0_groups[] = { "i2c0-data", }; 1607 static const char *x1830_i2c1_groups[] = { "i2c1-data", }; 1608 static const char *x1830_i2c2_groups[] = { "i2c2-data", }; 1609 static const char *x1830_lcd_groups[] = { 1610 "lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins", 1611 }; 1612 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", }; 1613 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", }; 1614 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", }; 1615 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", }; 1616 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", }; 1617 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", }; 1618 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", }; 1619 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", }; 1620 static const char *x1830_mac_groups[] = { "mac", }; 1621 1622 static const struct function_desc x1830_functions[] = { 1623 { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), }, 1624 { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), }, 1625 { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), }, 1626 { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), }, 1627 { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), }, 1628 { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), }, 1629 { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), }, 1630 { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, 1631 { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, 1632 { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, 1633 { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), }, 1634 { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, 1635 { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, 1636 { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), }, 1637 { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), }, 1638 { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1639 { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1640 { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1641 { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), }, 1642 { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), }, 1643 }; 1644 1645 static const struct ingenic_chip_info x1830_chip_info = { 1646 .num_chips = 4, 1647 .reg_offset = 0x1000, 1648 .version = ID_X1830, 1649 .groups = x1830_groups, 1650 .num_groups = ARRAY_SIZE(x1830_groups), 1651 .functions = x1830_functions, 1652 .num_functions = ARRAY_SIZE(x1830_functions), 1653 .pull_ups = x1830_pull_ups, 1654 .pull_downs = x1830_pull_downs, 1655 }; 1656 1657 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) 1658 { 1659 unsigned int val; 1660 1661 regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val); 1662 1663 return (u32) val; 1664 } 1665 1666 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, 1667 u8 reg, u8 offset, bool set) 1668 { 1669 if (set) 1670 reg = REG_SET(reg); 1671 else 1672 reg = REG_CLEAR(reg); 1673 1674 regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); 1675 } 1676 1677 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, 1678 u8 reg, u8 offset, bool set) 1679 { 1680 if (set) 1681 reg = REG_SET(reg); 1682 else 1683 reg = REG_CLEAR(reg); 1684 1685 regmap_write(jzgc->jzpc->map, REG_PZ_BASE( 1686 jzgc->jzpc->info->reg_offset) + reg, BIT(offset)); 1687 } 1688 1689 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) 1690 { 1691 regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD( 1692 jzgc->jzpc->info->reg_offset), 1693 jzgc->gc.base / PINS_PER_GPIO_CHIP); 1694 } 1695 1696 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, 1697 u8 offset) 1698 { 1699 unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN); 1700 1701 return !!(val & BIT(offset)); 1702 } 1703 1704 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, 1705 u8 offset, int value) 1706 { 1707 if (jzgc->jzpc->info->version >= ID_JZ4760) 1708 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value); 1709 else 1710 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); 1711 } 1712 1713 static void irq_set_type(struct ingenic_gpio_chip *jzgc, 1714 u8 offset, unsigned int type) 1715 { 1716 u8 reg1, reg2; 1717 bool val1, val2; 1718 1719 switch (type) { 1720 case IRQ_TYPE_EDGE_RISING: 1721 val1 = val2 = true; 1722 break; 1723 case IRQ_TYPE_EDGE_FALLING: 1724 val1 = false; 1725 val2 = true; 1726 break; 1727 case IRQ_TYPE_LEVEL_HIGH: 1728 val1 = true; 1729 val2 = false; 1730 break; 1731 case IRQ_TYPE_LEVEL_LOW: 1732 default: 1733 val1 = val2 = false; 1734 break; 1735 } 1736 1737 if (jzgc->jzpc->info->version >= ID_JZ4760) { 1738 reg1 = JZ4760_GPIO_PAT1; 1739 reg2 = JZ4760_GPIO_PAT0; 1740 } else { 1741 reg1 = JZ4740_GPIO_TRIG; 1742 reg2 = JZ4740_GPIO_DIR; 1743 } 1744 1745 if (jzgc->jzpc->info->version >= ID_X1000) { 1746 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1); 1747 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2); 1748 ingenic_gpio_shadow_set_bit_load(jzgc); 1749 } else { 1750 ingenic_gpio_set_bit(jzgc, reg2, offset, val1); 1751 ingenic_gpio_set_bit(jzgc, reg1, offset, val2); 1752 } 1753 } 1754 1755 static void ingenic_gpio_irq_mask(struct irq_data *irqd) 1756 { 1757 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1758 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1759 1760 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, true); 1761 } 1762 1763 static void ingenic_gpio_irq_unmask(struct irq_data *irqd) 1764 { 1765 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1766 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1767 1768 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irqd->hwirq, false); 1769 } 1770 1771 static void ingenic_gpio_irq_enable(struct irq_data *irqd) 1772 { 1773 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1774 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1775 int irq = irqd->hwirq; 1776 1777 if (jzgc->jzpc->info->version >= ID_JZ4760) 1778 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true); 1779 else 1780 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); 1781 1782 ingenic_gpio_irq_unmask(irqd); 1783 } 1784 1785 static void ingenic_gpio_irq_disable(struct irq_data *irqd) 1786 { 1787 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1788 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1789 int irq = irqd->hwirq; 1790 1791 ingenic_gpio_irq_mask(irqd); 1792 1793 if (jzgc->jzpc->info->version >= ID_JZ4760) 1794 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false); 1795 else 1796 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); 1797 } 1798 1799 static void ingenic_gpio_irq_ack(struct irq_data *irqd) 1800 { 1801 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1802 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1803 int irq = irqd->hwirq; 1804 bool high; 1805 1806 if (irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) { 1807 /* 1808 * Switch to an interrupt for the opposite edge to the one that 1809 * triggered the interrupt being ACKed. 1810 */ 1811 high = ingenic_gpio_get_value(jzgc, irq); 1812 if (high) 1813 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_FALLING); 1814 else 1815 irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING); 1816 } 1817 1818 if (jzgc->jzpc->info->version >= ID_JZ4760) 1819 ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false); 1820 else 1821 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); 1822 } 1823 1824 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 1825 { 1826 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1827 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1828 1829 switch (type) { 1830 case IRQ_TYPE_EDGE_BOTH: 1831 case IRQ_TYPE_EDGE_RISING: 1832 case IRQ_TYPE_EDGE_FALLING: 1833 irq_set_handler_locked(irqd, handle_edge_irq); 1834 break; 1835 case IRQ_TYPE_LEVEL_HIGH: 1836 case IRQ_TYPE_LEVEL_LOW: 1837 irq_set_handler_locked(irqd, handle_level_irq); 1838 break; 1839 default: 1840 irq_set_handler_locked(irqd, handle_bad_irq); 1841 } 1842 1843 if (type == IRQ_TYPE_EDGE_BOTH) { 1844 /* 1845 * The hardware does not support interrupts on both edges. The 1846 * best we can do is to set up a single-edge interrupt and then 1847 * switch to the opposing edge when ACKing the interrupt. 1848 */ 1849 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq); 1850 1851 type = high ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING; 1852 } 1853 1854 irq_set_type(jzgc, irqd->hwirq, type); 1855 return 0; 1856 } 1857 1858 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on) 1859 { 1860 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 1861 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1862 1863 return irq_set_irq_wake(jzgc->irq, on); 1864 } 1865 1866 static void ingenic_gpio_irq_handler(struct irq_desc *desc) 1867 { 1868 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1869 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1870 struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data); 1871 unsigned long flag, i; 1872 1873 chained_irq_enter(irq_chip, desc); 1874 1875 if (jzgc->jzpc->info->version >= ID_JZ4760) 1876 flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG); 1877 else 1878 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); 1879 1880 for_each_set_bit(i, &flag, 32) 1881 generic_handle_irq(irq_linear_revmap(gc->irq.domain, i)); 1882 chained_irq_exit(irq_chip, desc); 1883 } 1884 1885 static void ingenic_gpio_set(struct gpio_chip *gc, 1886 unsigned int offset, int value) 1887 { 1888 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1889 1890 ingenic_gpio_set_value(jzgc, offset, value); 1891 } 1892 1893 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset) 1894 { 1895 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1896 1897 return (int) ingenic_gpio_get_value(jzgc, offset); 1898 } 1899 1900 static int ingenic_gpio_direction_input(struct gpio_chip *gc, 1901 unsigned int offset) 1902 { 1903 return pinctrl_gpio_direction_input(gc->base + offset); 1904 } 1905 1906 static int ingenic_gpio_direction_output(struct gpio_chip *gc, 1907 unsigned int offset, int value) 1908 { 1909 ingenic_gpio_set(gc, offset, value); 1910 return pinctrl_gpio_direction_output(gc->base + offset); 1911 } 1912 1913 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, 1914 unsigned int pin, u8 reg, bool set) 1915 { 1916 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1917 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1918 1919 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 1920 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 1921 } 1922 1923 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, 1924 unsigned int pin, u8 reg, bool set) 1925 { 1926 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1927 1928 regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) + 1929 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); 1930 } 1931 1932 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, 1933 unsigned int pin) 1934 { 1935 regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset), 1936 pin / PINS_PER_GPIO_CHIP); 1937 } 1938 1939 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, 1940 unsigned int pin, u8 reg) 1941 { 1942 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 1943 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 1944 unsigned int val; 1945 1946 regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val); 1947 1948 return val & BIT(idx); 1949 } 1950 1951 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1952 { 1953 struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); 1954 struct ingenic_pinctrl *jzpc = jzgc->jzpc; 1955 unsigned int pin = gc->base + offset; 1956 1957 if (jzpc->info->version >= ID_JZ4760) { 1958 if (ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1)) 1959 return GPIO_LINE_DIRECTION_IN; 1960 return GPIO_LINE_DIRECTION_OUT; 1961 } 1962 1963 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) 1964 return GPIO_LINE_DIRECTION_IN; 1965 1966 if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR)) 1967 return GPIO_LINE_DIRECTION_OUT; 1968 1969 return GPIO_LINE_DIRECTION_IN; 1970 } 1971 1972 static const struct pinctrl_ops ingenic_pctlops = { 1973 .get_groups_count = pinctrl_generic_get_group_count, 1974 .get_group_name = pinctrl_generic_get_group_name, 1975 .get_group_pins = pinctrl_generic_get_group_pins, 1976 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 1977 .dt_free_map = pinconf_generic_dt_free_map, 1978 }; 1979 1980 static int ingenic_gpio_irq_request(struct irq_data *data) 1981 { 1982 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 1983 int ret; 1984 1985 ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); 1986 if (ret) 1987 return ret; 1988 1989 return gpiochip_reqres_irq(gpio_chip, data->hwirq); 1990 } 1991 1992 static void ingenic_gpio_irq_release(struct irq_data *data) 1993 { 1994 struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); 1995 1996 return gpiochip_relres_irq(gpio_chip, data->hwirq); 1997 } 1998 1999 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, 2000 int pin, int func) 2001 { 2002 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2003 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2004 2005 dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 2006 'A' + offt, idx, func); 2007 2008 if (jzpc->info->version >= ID_X1000) { 2009 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2010 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); 2011 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 2012 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 2013 ingenic_shadow_config_pin_load(jzpc, pin); 2014 } else if (jzpc->info->version >= ID_JZ4760) { 2015 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2016 ingenic_config_pin(jzpc, pin, GPIO_MSK, false); 2017 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); 2018 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); 2019 } else { 2020 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); 2021 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); 2022 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func > 0); 2023 } 2024 2025 return 0; 2026 } 2027 2028 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev, 2029 unsigned int selector, unsigned int group) 2030 { 2031 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2032 struct function_desc *func; 2033 struct group_desc *grp; 2034 unsigned int i; 2035 2036 func = pinmux_generic_get_function(pctldev, selector); 2037 if (!func) 2038 return -EINVAL; 2039 2040 grp = pinctrl_generic_get_group(pctldev, group); 2041 if (!grp) 2042 return -EINVAL; 2043 2044 dev_dbg(pctldev->dev, "enable function %s group %s\n", 2045 func->name, grp->name); 2046 2047 for (i = 0; i < grp->num_pins; i++) { 2048 int *pin_modes = grp->data; 2049 2050 ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]); 2051 } 2052 2053 return 0; 2054 } 2055 2056 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, 2057 struct pinctrl_gpio_range *range, 2058 unsigned int pin, bool input) 2059 { 2060 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2061 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2062 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2063 2064 dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 2065 'A' + offt, idx, input ? "in" : "out"); 2066 2067 if (jzpc->info->version >= ID_X1000) { 2068 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2069 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); 2070 ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2071 ingenic_shadow_config_pin_load(jzpc, pin); 2072 } else if (jzpc->info->version >= ID_JZ4760) { 2073 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); 2074 ingenic_config_pin(jzpc, pin, GPIO_MSK, true); 2075 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); 2076 } else { 2077 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); 2078 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); 2079 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false); 2080 } 2081 2082 return 0; 2083 } 2084 2085 static const struct pinmux_ops ingenic_pmxops = { 2086 .get_functions_count = pinmux_generic_get_function_count, 2087 .get_function_name = pinmux_generic_get_function_name, 2088 .get_function_groups = pinmux_generic_get_function_groups, 2089 .set_mux = ingenic_pinmux_set_mux, 2090 .gpio_set_direction = ingenic_pinmux_gpio_set_direction, 2091 }; 2092 2093 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, 2094 unsigned int pin, unsigned long *config) 2095 { 2096 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2097 enum pin_config_param param = pinconf_to_config_param(*config); 2098 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2099 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2100 bool pull; 2101 2102 if (jzpc->info->version >= ID_JZ4760) 2103 pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN); 2104 else 2105 pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); 2106 2107 switch (param) { 2108 case PIN_CONFIG_BIAS_DISABLE: 2109 if (pull) 2110 return -EINVAL; 2111 break; 2112 2113 case PIN_CONFIG_BIAS_PULL_UP: 2114 if (!pull || !(jzpc->info->pull_ups[offt] & BIT(idx))) 2115 return -EINVAL; 2116 break; 2117 2118 case PIN_CONFIG_BIAS_PULL_DOWN: 2119 if (!pull || !(jzpc->info->pull_downs[offt] & BIT(idx))) 2120 return -EINVAL; 2121 break; 2122 2123 default: 2124 return -ENOTSUPP; 2125 } 2126 2127 *config = pinconf_to_config_packed(param, 1); 2128 return 0; 2129 } 2130 2131 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, 2132 unsigned int pin, unsigned int bias) 2133 { 2134 if (jzpc->info->version >= ID_X1830) { 2135 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2136 unsigned int half = PINS_PER_GPIO_CHIP / 2; 2137 unsigned int idxh = pin % half * 2; 2138 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2139 2140 if (idx < half) { 2141 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2142 REG_CLEAR(X1830_GPIO_PEL), 3 << idxh); 2143 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2144 REG_SET(X1830_GPIO_PEL), bias << idxh); 2145 } else { 2146 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2147 REG_CLEAR(X1830_GPIO_PEH), 3 << idxh); 2148 regmap_write(jzpc->map, offt * jzpc->info->reg_offset + 2149 REG_SET(X1830_GPIO_PEH), bias << idxh); 2150 } 2151 2152 } else if (jzpc->info->version >= ID_JZ4760) { 2153 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !bias); 2154 } else { 2155 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias); 2156 } 2157 } 2158 2159 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc, 2160 unsigned int pin, bool high) 2161 { 2162 if (jzpc->info->version >= ID_JZ4760) 2163 ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, high); 2164 else 2165 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high); 2166 } 2167 2168 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 2169 unsigned long *configs, unsigned int num_configs) 2170 { 2171 struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev); 2172 unsigned int idx = pin % PINS_PER_GPIO_CHIP; 2173 unsigned int offt = pin / PINS_PER_GPIO_CHIP; 2174 unsigned int cfg, arg; 2175 int ret; 2176 2177 for (cfg = 0; cfg < num_configs; cfg++) { 2178 switch (pinconf_to_config_param(configs[cfg])) { 2179 case PIN_CONFIG_BIAS_DISABLE: 2180 case PIN_CONFIG_BIAS_PULL_UP: 2181 case PIN_CONFIG_BIAS_PULL_DOWN: 2182 case PIN_CONFIG_OUTPUT: 2183 continue; 2184 default: 2185 return -ENOTSUPP; 2186 } 2187 } 2188 2189 for (cfg = 0; cfg < num_configs; cfg++) { 2190 arg = pinconf_to_config_argument(configs[cfg]); 2191 2192 switch (pinconf_to_config_param(configs[cfg])) { 2193 case PIN_CONFIG_BIAS_DISABLE: 2194 dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n", 2195 'A' + offt, idx); 2196 ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS); 2197 break; 2198 2199 case PIN_CONFIG_BIAS_PULL_UP: 2200 if (!(jzpc->info->pull_ups[offt] & BIT(idx))) 2201 return -EINVAL; 2202 dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n", 2203 'A' + offt, idx); 2204 ingenic_set_bias(jzpc, pin, GPIO_PULL_UP); 2205 break; 2206 2207 case PIN_CONFIG_BIAS_PULL_DOWN: 2208 if (!(jzpc->info->pull_downs[offt] & BIT(idx))) 2209 return -EINVAL; 2210 dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n", 2211 'A' + offt, idx); 2212 ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN); 2213 break; 2214 2215 case PIN_CONFIG_OUTPUT: 2216 ret = pinctrl_gpio_direction_output(pin); 2217 if (ret) 2218 return ret; 2219 2220 ingenic_set_output_level(jzpc, pin, arg); 2221 break; 2222 2223 default: 2224 /* unreachable */ 2225 break; 2226 } 2227 } 2228 2229 return 0; 2230 } 2231 2232 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev, 2233 unsigned int group, unsigned long *config) 2234 { 2235 const unsigned int *pins; 2236 unsigned int i, npins, old = 0; 2237 int ret; 2238 2239 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2240 if (ret) 2241 return ret; 2242 2243 for (i = 0; i < npins; i++) { 2244 if (ingenic_pinconf_get(pctldev, pins[i], config)) 2245 return -ENOTSUPP; 2246 2247 /* configs do not match between two pins */ 2248 if (i && (old != *config)) 2249 return -ENOTSUPP; 2250 2251 old = *config; 2252 } 2253 2254 return 0; 2255 } 2256 2257 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev, 2258 unsigned int group, unsigned long *configs, 2259 unsigned int num_configs) 2260 { 2261 const unsigned int *pins; 2262 unsigned int i, npins; 2263 int ret; 2264 2265 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 2266 if (ret) 2267 return ret; 2268 2269 for (i = 0; i < npins; i++) { 2270 ret = ingenic_pinconf_set(pctldev, 2271 pins[i], configs, num_configs); 2272 if (ret) 2273 return ret; 2274 } 2275 2276 return 0; 2277 } 2278 2279 static const struct pinconf_ops ingenic_confops = { 2280 .is_generic = true, 2281 .pin_config_get = ingenic_pinconf_get, 2282 .pin_config_set = ingenic_pinconf_set, 2283 .pin_config_group_get = ingenic_pinconf_group_get, 2284 .pin_config_group_set = ingenic_pinconf_group_set, 2285 }; 2286 2287 static const struct regmap_config ingenic_pinctrl_regmap_config = { 2288 .reg_bits = 32, 2289 .val_bits = 32, 2290 .reg_stride = 4, 2291 }; 2292 2293 static const struct of_device_id ingenic_gpio_of_match[] __initconst = { 2294 { .compatible = "ingenic,jz4740-gpio", }, 2295 { .compatible = "ingenic,jz4760-gpio", }, 2296 { .compatible = "ingenic,jz4770-gpio", }, 2297 { .compatible = "ingenic,jz4780-gpio", }, 2298 { .compatible = "ingenic,x1000-gpio", }, 2299 { .compatible = "ingenic,x1830-gpio", }, 2300 {}, 2301 }; 2302 2303 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, 2304 struct device_node *node) 2305 { 2306 struct ingenic_gpio_chip *jzgc; 2307 struct device *dev = jzpc->dev; 2308 struct gpio_irq_chip *girq; 2309 unsigned int bank; 2310 int err; 2311 2312 err = of_property_read_u32(node, "reg", &bank); 2313 if (err) { 2314 dev_err(dev, "Cannot read \"reg\" property: %i\n", err); 2315 return err; 2316 } 2317 2318 jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL); 2319 if (!jzgc) 2320 return -ENOMEM; 2321 2322 jzgc->jzpc = jzpc; 2323 jzgc->reg_base = bank * jzpc->info->reg_offset; 2324 2325 jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank); 2326 if (!jzgc->gc.label) 2327 return -ENOMEM; 2328 2329 /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY 2330 * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN 2331 * <linux/gpio/consumer.h> INSTEAD. 2332 */ 2333 jzgc->gc.base = bank * 32; 2334 2335 jzgc->gc.ngpio = 32; 2336 jzgc->gc.parent = dev; 2337 jzgc->gc.of_node = node; 2338 jzgc->gc.owner = THIS_MODULE; 2339 2340 jzgc->gc.set = ingenic_gpio_set; 2341 jzgc->gc.get = ingenic_gpio_get; 2342 jzgc->gc.direction_input = ingenic_gpio_direction_input; 2343 jzgc->gc.direction_output = ingenic_gpio_direction_output; 2344 jzgc->gc.get_direction = ingenic_gpio_get_direction; 2345 jzgc->gc.request = gpiochip_generic_request; 2346 jzgc->gc.free = gpiochip_generic_free; 2347 2348 jzgc->irq = irq_of_parse_and_map(node, 0); 2349 if (!jzgc->irq) 2350 return -EINVAL; 2351 2352 jzgc->irq_chip.name = jzgc->gc.label; 2353 jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable; 2354 jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable; 2355 jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask; 2356 jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask; 2357 jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; 2358 jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; 2359 jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; 2360 jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; 2361 jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; 2362 jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; 2363 2364 girq = &jzgc->gc.irq; 2365 girq->chip = &jzgc->irq_chip; 2366 girq->parent_handler = ingenic_gpio_irq_handler; 2367 girq->num_parents = 1; 2368 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 2369 GFP_KERNEL); 2370 if (!girq->parents) 2371 return -ENOMEM; 2372 girq->parents[0] = jzgc->irq; 2373 girq->default_type = IRQ_TYPE_NONE; 2374 girq->handler = handle_level_irq; 2375 2376 err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc); 2377 if (err) 2378 return err; 2379 2380 return 0; 2381 } 2382 2383 static int __init ingenic_pinctrl_probe(struct platform_device *pdev) 2384 { 2385 struct device *dev = &pdev->dev; 2386 struct ingenic_pinctrl *jzpc; 2387 struct pinctrl_desc *pctl_desc; 2388 void __iomem *base; 2389 const struct ingenic_chip_info *chip_info; 2390 struct device_node *node; 2391 unsigned int i; 2392 int err; 2393 2394 jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL); 2395 if (!jzpc) 2396 return -ENOMEM; 2397 2398 base = devm_platform_ioremap_resource(pdev, 0); 2399 if (IS_ERR(base)) 2400 return PTR_ERR(base); 2401 2402 jzpc->map = devm_regmap_init_mmio(dev, base, 2403 &ingenic_pinctrl_regmap_config); 2404 if (IS_ERR(jzpc->map)) { 2405 dev_err(dev, "Failed to create regmap\n"); 2406 return PTR_ERR(jzpc->map); 2407 } 2408 2409 jzpc->dev = dev; 2410 jzpc->info = chip_info = of_device_get_match_data(dev); 2411 2412 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL); 2413 if (!pctl_desc) 2414 return -ENOMEM; 2415 2416 /* fill in pinctrl_desc structure */ 2417 pctl_desc->name = dev_name(dev); 2418 pctl_desc->owner = THIS_MODULE; 2419 pctl_desc->pctlops = &ingenic_pctlops; 2420 pctl_desc->pmxops = &ingenic_pmxops; 2421 pctl_desc->confops = &ingenic_confops; 2422 pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP; 2423 pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev, 2424 pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL); 2425 if (!jzpc->pdesc) 2426 return -ENOMEM; 2427 2428 for (i = 0; i < pctl_desc->npins; i++) { 2429 jzpc->pdesc[i].number = i; 2430 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d", 2431 'A' + (i / PINS_PER_GPIO_CHIP), 2432 i % PINS_PER_GPIO_CHIP); 2433 } 2434 2435 jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc); 2436 if (IS_ERR(jzpc->pctl)) { 2437 dev_err(dev, "Failed to register pinctrl\n"); 2438 return PTR_ERR(jzpc->pctl); 2439 } 2440 2441 for (i = 0; i < chip_info->num_groups; i++) { 2442 const struct group_desc *group = &chip_info->groups[i]; 2443 2444 err = pinctrl_generic_add_group(jzpc->pctl, group->name, 2445 group->pins, group->num_pins, group->data); 2446 if (err < 0) { 2447 dev_err(dev, "Failed to register group %s\n", 2448 group->name); 2449 return err; 2450 } 2451 } 2452 2453 for (i = 0; i < chip_info->num_functions; i++) { 2454 const struct function_desc *func = &chip_info->functions[i]; 2455 2456 err = pinmux_generic_add_function(jzpc->pctl, func->name, 2457 func->group_names, func->num_group_names, 2458 func->data); 2459 if (err < 0) { 2460 dev_err(dev, "Failed to register function %s\n", 2461 func->name); 2462 return err; 2463 } 2464 } 2465 2466 dev_set_drvdata(dev, jzpc->map); 2467 2468 for_each_child_of_node(dev->of_node, node) { 2469 if (of_match_node(ingenic_gpio_of_match, node)) { 2470 err = ingenic_gpio_probe(jzpc, node); 2471 if (err) 2472 return err; 2473 } 2474 } 2475 2476 return 0; 2477 } 2478 2479 static const struct of_device_id ingenic_pinctrl_of_match[] = { 2480 { .compatible = "ingenic,jz4740-pinctrl", .data = &jz4740_chip_info }, 2481 { .compatible = "ingenic,jz4725b-pinctrl", .data = &jz4725b_chip_info }, 2482 { .compatible = "ingenic,jz4760-pinctrl", .data = &jz4760_chip_info }, 2483 { .compatible = "ingenic,jz4760b-pinctrl", .data = &jz4760_chip_info }, 2484 { .compatible = "ingenic,jz4770-pinctrl", .data = &jz4770_chip_info }, 2485 { .compatible = "ingenic,jz4780-pinctrl", .data = &jz4780_chip_info }, 2486 { .compatible = "ingenic,x1000-pinctrl", .data = &x1000_chip_info }, 2487 { .compatible = "ingenic,x1000e-pinctrl", .data = &x1000_chip_info }, 2488 { .compatible = "ingenic,x1500-pinctrl", .data = &x1500_chip_info }, 2489 { .compatible = "ingenic,x1830-pinctrl", .data = &x1830_chip_info }, 2490 {}, 2491 }; 2492 2493 static struct platform_driver ingenic_pinctrl_driver = { 2494 .driver = { 2495 .name = "pinctrl-ingenic", 2496 .of_match_table = ingenic_pinctrl_of_match, 2497 }, 2498 }; 2499 2500 static int __init ingenic_pinctrl_drv_register(void) 2501 { 2502 return platform_driver_probe(&ingenic_pinctrl_driver, 2503 ingenic_pinctrl_probe); 2504 } 2505 subsys_initcall(ingenic_pinctrl_drv_register); 2506