1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * (c) Copyright 2002-2010, Ralink Technology, Inc. 4 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org> 5 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl> 6 * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl> 7 */ 8 9 #include "mt76x0.h" 10 #include "eeprom.h" 11 #include "mcu.h" 12 #include "initvals.h" 13 #include "../mt76x02_phy.h" 14 15 static void 16 mt76x0_set_wlan_state(struct mt76x02_dev *dev, u32 val, bool enable) 17 { 18 u32 mask = MT_CMB_CTRL_XTAL_RDY | MT_CMB_CTRL_PLL_LD; 19 20 /* Note: we don't turn off WLAN_CLK because that makes the device 21 * not respond properly on the probe path. 22 * In case anyone (PSM?) wants to use this function we can 23 * bring the clock stuff back and fixup the probe path. 24 */ 25 26 if (enable) 27 val |= (MT_WLAN_FUN_CTRL_WLAN_EN | 28 MT_WLAN_FUN_CTRL_WLAN_CLK_EN); 29 else 30 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN); 31 32 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 33 udelay(20); 34 35 /* Note: vendor driver tries to disable/enable wlan here and retry 36 * but the code which does it is so buggy it must have never 37 * triggered, so don't bother. 38 */ 39 if (enable && !mt76_poll(dev, MT_CMB_CTRL, mask, mask, 2000)) 40 dev_err(dev->mt76.dev, "PLL and XTAL check failed\n"); 41 } 42 43 void mt76x0_chip_onoff(struct mt76x02_dev *dev, bool enable, bool reset) 44 { 45 u32 val; 46 47 val = mt76_rr(dev, MT_WLAN_FUN_CTRL); 48 49 if (reset) { 50 val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN; 51 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL; 52 53 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) { 54 val |= (MT_WLAN_FUN_CTRL_WLAN_RESET | 55 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 56 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 57 udelay(20); 58 59 val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET | 60 MT_WLAN_FUN_CTRL_WLAN_RESET_RF); 61 } 62 } 63 64 mt76_wr(dev, MT_WLAN_FUN_CTRL, val); 65 udelay(20); 66 67 mt76x0_set_wlan_state(dev, val, enable); 68 } 69 EXPORT_SYMBOL_GPL(mt76x0_chip_onoff); 70 71 static void mt76x0_reset_csr_bbp(struct mt76x02_dev *dev) 72 { 73 mt76_wr(dev, MT_MAC_SYS_CTRL, 74 MT_MAC_SYS_CTRL_RESET_CSR | 75 MT_MAC_SYS_CTRL_RESET_BBP); 76 msleep(200); 77 mt76_clear(dev, MT_MAC_SYS_CTRL, 78 MT_MAC_SYS_CTRL_RESET_CSR | 79 MT_MAC_SYS_CTRL_RESET_BBP); 80 } 81 82 #define RANDOM_WRITE(dev, tab) \ 83 mt76_wr_rp(dev, MT_MCU_MEMMAP_WLAN, \ 84 tab, ARRAY_SIZE(tab)) 85 86 static int mt76x0_init_bbp(struct mt76x02_dev *dev) 87 { 88 int ret, i; 89 90 ret = mt76x0_phy_wait_bbp_ready(dev); 91 if (ret) 92 return ret; 93 94 RANDOM_WRITE(dev, mt76x0_bbp_init_tab); 95 96 for (i = 0; i < ARRAY_SIZE(mt76x0_bbp_switch_tab); i++) { 97 const struct mt76x0_bbp_switch_item *item = &mt76x0_bbp_switch_tab[i]; 98 const struct mt76_reg_pair *pair = &item->reg_pair; 99 100 if (((RF_G_BAND | RF_BW_20) & item->bw_band) == (RF_G_BAND | RF_BW_20)) 101 mt76_wr(dev, pair->reg, pair->value); 102 } 103 104 RANDOM_WRITE(dev, mt76x0_dcoc_tab); 105 106 return 0; 107 } 108 109 static void mt76x0_init_mac_registers(struct mt76x02_dev *dev) 110 { 111 RANDOM_WRITE(dev, common_mac_reg_table); 112 113 /* Enable PBF and MAC clock SYS_CTRL[11:10] = 0x3 */ 114 RANDOM_WRITE(dev, mt76x0_mac_reg_table); 115 116 /* Release BBP and MAC reset MAC_SYS_CTRL[1:0] = 0x0 */ 117 mt76_clear(dev, MT_MAC_SYS_CTRL, 0x3); 118 119 /* Set 0x141C[15:12]=0xF */ 120 mt76_set(dev, MT_EXT_CCA_CFG, 0xf000); 121 122 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN); 123 124 /* 125 * tx_ring 9 is for mgmt frame 126 * tx_ring 8 is for in-band command frame. 127 * WMM_RG0_TXQMA: this register setting is for FCE to 128 * define the rule of tx_ring 9 129 * WMM_RG1_TXQMA: this register setting is for FCE to 130 * define the rule of tx_ring 8 131 */ 132 mt76_rmw(dev, MT_WMM_CTRL, 0x3ff, 0x201); 133 } 134 135 void mt76x0_mac_stop(struct mt76x02_dev *dev) 136 { 137 int i = 200, ok = 0; 138 139 mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN); 140 141 /* Page count on TxQ */ 142 while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) || 143 (mt76_rr(dev, 0x0a30) & 0x000000ff) || 144 (mt76_rr(dev, 0x0a34) & 0x00ff00ff))) 145 msleep(10); 146 147 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000)) 148 dev_warn(dev->mt76.dev, "Warning: MAC TX did not stop!\n"); 149 150 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX | 151 MT_MAC_SYS_CTRL_ENABLE_TX); 152 153 /* Page count on RxQ */ 154 for (i = 0; i < 200; i++) { 155 if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) && 156 !mt76_rr(dev, 0x0a30) && 157 !mt76_rr(dev, 0x0a34)) { 158 if (ok++ > 5) 159 break; 160 continue; 161 } 162 msleep(1); 163 } 164 165 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000)) 166 dev_warn(dev->mt76.dev, "Warning: MAC RX did not stop!\n"); 167 } 168 EXPORT_SYMBOL_GPL(mt76x0_mac_stop); 169 170 int mt76x0_init_hardware(struct mt76x02_dev *dev) 171 { 172 int ret, i, k; 173 174 if (!mt76x02_wait_for_wpdma(&dev->mt76, 1000)) 175 return -EIO; 176 177 /* Wait for ASIC ready after FW load. */ 178 if (!mt76x02_wait_for_mac(&dev->mt76)) 179 return -ETIMEDOUT; 180 181 mt76x0_reset_csr_bbp(dev); 182 ret = mt76x02_mcu_function_select(dev, Q_SELECT, 1); 183 if (ret) 184 return ret; 185 186 mt76x0_init_mac_registers(dev); 187 188 if (!mt76x02_wait_for_txrx_idle(&dev->mt76)) 189 return -EIO; 190 191 ret = mt76x0_init_bbp(dev); 192 if (ret) 193 return ret; 194 195 dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); 196 197 for (i = 0; i < 16; i++) 198 for (k = 0; k < 4; k++) 199 mt76x02_mac_shared_key_setup(dev, i, k, NULL); 200 201 for (i = 0; i < 256; i++) 202 mt76x02_mac_wcid_setup(dev, i, 0, NULL); 203 204 ret = mt76x0_eeprom_init(dev); 205 if (ret) 206 return ret; 207 208 mt76x0_phy_init(dev); 209 210 return 0; 211 } 212 EXPORT_SYMBOL_GPL(mt76x0_init_hardware); 213 214 static void 215 mt76x0_init_txpower(struct mt76x02_dev *dev, 216 struct ieee80211_supported_band *sband) 217 { 218 struct ieee80211_channel *chan; 219 struct mt76_rate_power t; 220 s8 tp; 221 int i; 222 223 for (i = 0; i < sband->n_channels; i++) { 224 chan = &sband->channels[i]; 225 226 mt76x0_get_tx_power_per_rate(dev, chan, &t); 227 mt76x0_get_power_info(dev, chan, &tp); 228 229 chan->orig_mpwr = (mt76x02_get_max_rate_power(&t) + tp) / 2; 230 chan->max_power = min_t(int, chan->max_reg_power, 231 chan->orig_mpwr); 232 } 233 } 234 235 int mt76x0_register_device(struct mt76x02_dev *dev) 236 { 237 int ret; 238 239 mt76x02_init_device(dev); 240 mt76x02_config_mac_addr_list(dev); 241 242 ret = mt76_register_device(&dev->mt76, true, mt76x02_rates, 243 ARRAY_SIZE(mt76x02_rates)); 244 if (ret) 245 return ret; 246 247 if (dev->mt76.cap.has_5ghz) { 248 struct ieee80211_supported_band *sband; 249 250 sband = &dev->mphy.sband_5g.sband; 251 sband->vht_cap.cap &= ~IEEE80211_VHT_CAP_RXLDPC; 252 mt76x0_init_txpower(dev, sband); 253 } 254 255 if (dev->mt76.cap.has_2ghz) 256 mt76x0_init_txpower(dev, &dev->mphy.sband_2g.sband); 257 258 mt76x02_init_debugfs(dev); 259 260 return 0; 261 } 262 EXPORT_SYMBOL_GPL(mt76x0_register_device); 263