1Spreadtrum PWM controller
2
3Spreadtrum SoCs PWM controller provides 4 PWM channels.
4
5Required properties:
6- compatible : Should be "sprd,ums512-pwm".
7- reg: Physical base address and length of the controller's registers.
8- clocks: The phandle and specifier referencing the controller's clocks.
9- clock-names: Should contain following entries:
10  "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
11  "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
12- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of
13  the cells format.
14
15Optional properties:
16- assigned-clocks: Reference to the PWM clock entries.
17- assigned-clock-parents: The phandle of the parent clock of PWM clock.
18
19Example:
20	pwms: pwm@32260000 {
21		compatible = "sprd,ums512-pwm";
22		reg = <0 0x32260000 0 0x10000>;
23		clock-names = "pwm0", "enable0",
24			"pwm1", "enable1",
25			"pwm2", "enable2",
26			"pwm3", "enable3";
27		clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
28		       <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
29		       <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
30		       <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
31		assigned-clocks = <&aon_clk CLK_PWM0>,
32			<&aon_clk CLK_PWM1>,
33			<&aon_clk CLK_PWM2>,
34			<&aon_clk CLK_PWM3>;
35		assigned-clock-parents = <&ext_26m>,
36			<&ext_26m>,
37			<&ext_26m>,
38			<&ext_26m>;
39		#pwm-cells = <2>;
40	};
41