1 /* 2 * Copyright © 2018 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Madhav Chauhan <madhav.chauhan@intel.com> 25 * Jani Nikula <jani.nikula@intel.com> 26 */ 27 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_mipi_dsi.h> 30 31 #include "intel_atomic.h" 32 #include "intel_combo_phy.h" 33 #include "intel_connector.h" 34 #include "intel_ddi.h" 35 #include "intel_dsi.h" 36 #include "intel_panel.h" 37 #include "intel_vdsc.h" 38 39 static inline int header_credits_available(struct drm_i915_private *dev_priv, 40 enum transcoder dsi_trans) 41 { 42 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) 43 >> FREE_HEADER_CREDIT_SHIFT; 44 } 45 46 static inline int payload_credits_available(struct drm_i915_private *dev_priv, 47 enum transcoder dsi_trans) 48 { 49 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) 50 >> FREE_PLOAD_CREDIT_SHIFT; 51 } 52 53 static void wait_for_header_credits(struct drm_i915_private *dev_priv, 54 enum transcoder dsi_trans) 55 { 56 if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >= 57 MAX_HEADER_CREDIT, 100)) 58 drm_err(&dev_priv->drm, "DSI header credits not released\n"); 59 } 60 61 static void wait_for_payload_credits(struct drm_i915_private *dev_priv, 62 enum transcoder dsi_trans) 63 { 64 if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >= 65 MAX_PLOAD_CREDIT, 100)) 66 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); 67 } 68 69 static enum transcoder dsi_port_to_transcoder(enum port port) 70 { 71 if (port == PORT_A) 72 return TRANSCODER_DSI_0; 73 else 74 return TRANSCODER_DSI_1; 75 } 76 77 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder) 78 { 79 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 80 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 81 struct mipi_dsi_device *dsi; 82 enum port port; 83 enum transcoder dsi_trans; 84 int ret; 85 86 /* wait for header/payload credits to be released */ 87 for_each_dsi_port(port, intel_dsi->ports) { 88 dsi_trans = dsi_port_to_transcoder(port); 89 wait_for_header_credits(dev_priv, dsi_trans); 90 wait_for_payload_credits(dev_priv, dsi_trans); 91 } 92 93 /* send nop DCS command */ 94 for_each_dsi_port(port, intel_dsi->ports) { 95 dsi = intel_dsi->dsi_hosts[port]->device; 96 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 97 dsi->channel = 0; 98 ret = mipi_dsi_dcs_nop(dsi); 99 if (ret < 0) 100 drm_err(&dev_priv->drm, 101 "error sending DCS NOP command\n"); 102 } 103 104 /* wait for header credits to be released */ 105 for_each_dsi_port(port, intel_dsi->ports) { 106 dsi_trans = dsi_port_to_transcoder(port); 107 wait_for_header_credits(dev_priv, dsi_trans); 108 } 109 110 /* wait for LP TX in progress bit to be cleared */ 111 for_each_dsi_port(port, intel_dsi->ports) { 112 dsi_trans = dsi_port_to_transcoder(port); 113 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 114 LPTX_IN_PROGRESS), 20)) 115 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); 116 } 117 } 118 119 static bool add_payld_to_queue(struct intel_dsi_host *host, const u8 *data, 120 u32 len) 121 { 122 struct intel_dsi *intel_dsi = host->intel_dsi; 123 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 124 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 125 int free_credits; 126 int i, j; 127 128 for (i = 0; i < len; i += 4) { 129 u32 tmp = 0; 130 131 free_credits = payload_credits_available(dev_priv, dsi_trans); 132 if (free_credits < 1) { 133 drm_err(&dev_priv->drm, 134 "Payload credit not available\n"); 135 return false; 136 } 137 138 for (j = 0; j < min_t(u32, len - i, 4); j++) 139 tmp |= *data++ << 8 * j; 140 141 intel_de_write(dev_priv, DSI_CMD_TXPYLD(dsi_trans), tmp); 142 } 143 144 return true; 145 } 146 147 static int dsi_send_pkt_hdr(struct intel_dsi_host *host, 148 struct mipi_dsi_packet pkt, bool enable_lpdt) 149 { 150 struct intel_dsi *intel_dsi = host->intel_dsi; 151 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 152 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); 153 u32 tmp; 154 int free_credits; 155 156 /* check if header credit available */ 157 free_credits = header_credits_available(dev_priv, dsi_trans); 158 if (free_credits < 1) { 159 drm_err(&dev_priv->drm, 160 "send pkt header failed, not enough hdr credits\n"); 161 return -1; 162 } 163 164 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); 165 166 if (pkt.payload) 167 tmp |= PAYLOAD_PRESENT; 168 else 169 tmp &= ~PAYLOAD_PRESENT; 170 171 tmp &= ~VBLANK_FENCE; 172 173 if (enable_lpdt) 174 tmp |= LP_DATA_TRANSFER; 175 176 tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK); 177 tmp |= ((pkt.header[0] & VC_MASK) << VC_SHIFT); 178 tmp |= ((pkt.header[0] & DT_MASK) << DT_SHIFT); 179 tmp |= (pkt.header[1] << PARAM_WC_LOWER_SHIFT); 180 tmp |= (pkt.header[2] << PARAM_WC_UPPER_SHIFT); 181 intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp); 182 183 return 0; 184 } 185 186 static int dsi_send_pkt_payld(struct intel_dsi_host *host, 187 struct mipi_dsi_packet pkt) 188 { 189 /* payload queue can accept *256 bytes*, check limit */ 190 if (pkt.payload_length > MAX_PLOAD_CREDIT * 4) { 191 DRM_ERROR("payload size exceeds max queue limit\n"); 192 return -1; 193 } 194 195 /* load data into command payload queue */ 196 if (!add_payld_to_queue(host, pkt.payload, 197 pkt.payload_length)) { 198 DRM_ERROR("adding payload to queue failed\n"); 199 return -1; 200 } 201 202 return 0; 203 } 204 205 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) 206 { 207 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 208 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 209 enum phy phy; 210 u32 tmp; 211 int lane; 212 213 for_each_dsi_phy(phy, intel_dsi->phys) { 214 /* 215 * Program voltage swing and pre-emphasis level values as per 216 * table in BSPEC under DDI buffer programing 217 */ 218 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 219 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 220 tmp |= SCALING_MODE_SEL(0x2); 221 tmp |= TAP2_DISABLE | TAP3_DISABLE; 222 tmp |= RTERM_SELECT(0x6); 223 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 224 225 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 226 tmp &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK); 227 tmp |= SCALING_MODE_SEL(0x2); 228 tmp |= TAP2_DISABLE | TAP3_DISABLE; 229 tmp |= RTERM_SELECT(0x6); 230 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 231 232 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 233 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 234 RCOMP_SCALAR_MASK); 235 tmp |= SWING_SEL_UPPER(0x2); 236 tmp |= SWING_SEL_LOWER(0x2); 237 tmp |= RCOMP_SCALAR(0x98); 238 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 239 240 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 241 tmp &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK | 242 RCOMP_SCALAR_MASK); 243 tmp |= SWING_SEL_UPPER(0x2); 244 tmp |= SWING_SEL_LOWER(0x2); 245 tmp |= RCOMP_SCALAR(0x98); 246 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 247 248 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 249 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 250 CURSOR_COEFF_MASK); 251 tmp |= POST_CURSOR_1(0x0); 252 tmp |= POST_CURSOR_2(0x0); 253 tmp |= CURSOR_COEFF(0x3f); 254 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 255 256 for (lane = 0; lane <= 3; lane++) { 257 /* Bspec: must not use GRP register for write */ 258 tmp = intel_de_read(dev_priv, 259 ICL_PORT_TX_DW4_LN(lane, phy)); 260 tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | 261 CURSOR_COEFF_MASK); 262 tmp |= POST_CURSOR_1(0x0); 263 tmp |= POST_CURSOR_2(0x0); 264 tmp |= CURSOR_COEFF(0x3f); 265 intel_de_write(dev_priv, 266 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 267 } 268 } 269 } 270 271 static void configure_dual_link_mode(struct intel_encoder *encoder, 272 const struct intel_crtc_state *pipe_config) 273 { 274 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 275 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 276 u32 dss_ctl1; 277 278 dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); 279 dss_ctl1 |= SPLITTER_ENABLE; 280 dss_ctl1 &= ~OVERLAP_PIXELS_MASK; 281 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); 282 283 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 284 const struct drm_display_mode *adjusted_mode = 285 &pipe_config->hw.adjusted_mode; 286 u32 dss_ctl2; 287 u16 hactive = adjusted_mode->crtc_hdisplay; 288 u16 dl_buffer_depth; 289 290 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE; 291 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; 292 293 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH) 294 drm_err(&dev_priv->drm, 295 "DL buffer depth exceed max value\n"); 296 297 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; 298 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 299 dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); 300 dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; 301 dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); 302 intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); 303 } else { 304 /* Interleave */ 305 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; 306 } 307 308 intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); 309 } 310 311 /* aka DSI 8X clock */ 312 static int afe_clk(struct intel_encoder *encoder, 313 const struct intel_crtc_state *crtc_state) 314 { 315 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 316 int bpp; 317 318 if (crtc_state->dsc.compression_enable) 319 bpp = crtc_state->dsc.compressed_bpp; 320 else 321 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 322 323 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); 324 } 325 326 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, 327 const struct intel_crtc_state *crtc_state) 328 { 329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 330 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 331 enum port port; 332 int afe_clk_khz; 333 u32 esc_clk_div_m; 334 335 afe_clk_khz = afe_clk(encoder, crtc_state); 336 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK); 337 338 for_each_dsi_port(port, intel_dsi->ports) { 339 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), 340 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 341 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port)); 342 } 343 344 for_each_dsi_port(port, intel_dsi->ports) { 345 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port), 346 esc_clk_div_m & ICL_ESC_CLK_DIV_MASK); 347 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port)); 348 } 349 } 350 351 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv, 352 struct intel_dsi *intel_dsi) 353 { 354 enum port port; 355 356 for_each_dsi_port(port, intel_dsi->ports) { 357 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); 358 intel_dsi->io_wakeref[port] = 359 intel_display_power_get(dev_priv, 360 port == PORT_A ? 361 POWER_DOMAIN_PORT_DDI_A_IO : 362 POWER_DOMAIN_PORT_DDI_B_IO); 363 } 364 } 365 366 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder) 367 { 368 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 369 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 370 enum port port; 371 u32 tmp; 372 373 for_each_dsi_port(port, intel_dsi->ports) { 374 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 375 tmp |= COMBO_PHY_MODE_DSI; 376 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 377 } 378 379 get_dsi_io_power_domains(dev_priv, intel_dsi); 380 } 381 382 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder) 383 { 384 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 385 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 386 enum phy phy; 387 388 for_each_dsi_phy(phy, intel_dsi->phys) 389 intel_combo_phy_power_up_lanes(dev_priv, phy, true, 390 intel_dsi->lane_count, false); 391 } 392 393 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) 394 { 395 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 396 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 397 enum phy phy; 398 u32 tmp; 399 int lane; 400 401 /* Step 4b(i) set loadgen select for transmit and aux lanes */ 402 for_each_dsi_phy(phy, intel_dsi->phys) { 403 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW4_AUX(phy)); 404 tmp &= ~LOADGEN_SELECT; 405 intel_de_write(dev_priv, ICL_PORT_TX_DW4_AUX(phy), tmp); 406 for (lane = 0; lane <= 3; lane++) { 407 tmp = intel_de_read(dev_priv, 408 ICL_PORT_TX_DW4_LN(lane, phy)); 409 tmp &= ~LOADGEN_SELECT; 410 if (lane != 2) 411 tmp |= LOADGEN_SELECT; 412 intel_de_write(dev_priv, 413 ICL_PORT_TX_DW4_LN(lane, phy), tmp); 414 } 415 } 416 417 /* Step 4b(ii) set latency optimization for transmit and aux lanes */ 418 for_each_dsi_phy(phy, intel_dsi->phys) { 419 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_AUX(phy)); 420 tmp &= ~FRC_LATENCY_OPTIM_MASK; 421 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 422 intel_de_write(dev_priv, ICL_PORT_TX_DW2_AUX(phy), tmp); 423 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy)); 424 tmp &= ~FRC_LATENCY_OPTIM_MASK; 425 tmp |= FRC_LATENCY_OPTIM_VAL(0x5); 426 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp); 427 428 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */ 429 if (IS_ELKHARTLAKE(dev_priv) || (INTEL_GEN(dev_priv) >= 12)) { 430 tmp = intel_de_read(dev_priv, 431 ICL_PORT_PCS_DW1_AUX(phy)); 432 tmp &= ~LATENCY_OPTIM_MASK; 433 tmp |= LATENCY_OPTIM_VAL(0); 434 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), 435 tmp); 436 437 tmp = intel_de_read(dev_priv, 438 ICL_PORT_PCS_DW1_LN0(phy)); 439 tmp &= ~LATENCY_OPTIM_MASK; 440 tmp |= LATENCY_OPTIM_VAL(0x1); 441 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), 442 tmp); 443 } 444 } 445 446 } 447 448 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder) 449 { 450 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 451 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 452 u32 tmp; 453 enum phy phy; 454 455 /* clear common keeper enable bit */ 456 for_each_dsi_phy(phy, intel_dsi->phys) { 457 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy)); 458 tmp &= ~COMMON_KEEPER_EN; 459 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp); 460 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_AUX(phy)); 461 tmp &= ~COMMON_KEEPER_EN; 462 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), tmp); 463 } 464 465 /* 466 * Set SUS Clock Config bitfield to 11b 467 * Note: loadgen select program is done 468 * as part of lane phy sequence configuration 469 */ 470 for_each_dsi_phy(phy, intel_dsi->phys) { 471 tmp = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy)); 472 tmp |= SUS_CLOCK_CONFIG; 473 intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), tmp); 474 } 475 476 /* Clear training enable to change swing values */ 477 for_each_dsi_phy(phy, intel_dsi->phys) { 478 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 479 tmp &= ~TX_TRAINING_EN; 480 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 481 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 482 tmp &= ~TX_TRAINING_EN; 483 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 484 } 485 486 /* Program swing and de-emphasis */ 487 dsi_program_swing_and_deemphasis(encoder); 488 489 /* Set training enable to trigger update */ 490 for_each_dsi_phy(phy, intel_dsi->phys) { 491 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy)); 492 tmp |= TX_TRAINING_EN; 493 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp); 494 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_AUX(phy)); 495 tmp |= TX_TRAINING_EN; 496 intel_de_write(dev_priv, ICL_PORT_TX_DW5_AUX(phy), tmp); 497 } 498 } 499 500 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder) 501 { 502 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 503 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 504 u32 tmp; 505 enum port port; 506 507 for_each_dsi_port(port, intel_dsi->ports) { 508 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 509 tmp |= DDI_BUF_CTL_ENABLE; 510 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 511 512 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 513 DDI_BUF_IS_IDLE), 514 500)) 515 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", 516 port_name(port)); 517 } 518 } 519 520 static void 521 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, 522 const struct intel_crtc_state *crtc_state) 523 { 524 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 525 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 526 u32 tmp; 527 enum port port; 528 enum phy phy; 529 530 /* Program T-INIT master registers */ 531 for_each_dsi_port(port, intel_dsi->ports) { 532 tmp = intel_de_read(dev_priv, ICL_DSI_T_INIT_MASTER(port)); 533 tmp &= ~MASTER_INIT_TIMER_MASK; 534 tmp |= intel_dsi->init_count; 535 intel_de_write(dev_priv, ICL_DSI_T_INIT_MASTER(port), tmp); 536 } 537 538 /* Program DPHY clock lanes timings */ 539 for_each_dsi_port(port, intel_dsi->ports) { 540 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port), 541 intel_dsi->dphy_reg); 542 543 /* shadow register inside display core */ 544 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port), 545 intel_dsi->dphy_reg); 546 } 547 548 /* Program DPHY data lanes timings */ 549 for_each_dsi_port(port, intel_dsi->ports) { 550 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port), 551 intel_dsi->dphy_data_lane_reg); 552 553 /* shadow register inside display core */ 554 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port), 555 intel_dsi->dphy_data_lane_reg); 556 } 557 558 /* 559 * If DSI link operating at or below an 800 MHz, 560 * TA_SURE should be override and programmed to 561 * a value '0' inside TA_PARAM_REGISTERS otherwise 562 * leave all fields at HW default values. 563 */ 564 if (IS_GEN(dev_priv, 11)) { 565 if (afe_clk(encoder, crtc_state) <= 800000) { 566 for_each_dsi_port(port, intel_dsi->ports) { 567 tmp = intel_de_read(dev_priv, 568 DPHY_TA_TIMING_PARAM(port)); 569 tmp &= ~TA_SURE_MASK; 570 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 571 intel_de_write(dev_priv, 572 DPHY_TA_TIMING_PARAM(port), 573 tmp); 574 575 /* shadow register inside display core */ 576 tmp = intel_de_read(dev_priv, 577 DSI_TA_TIMING_PARAM(port)); 578 tmp &= ~TA_SURE_MASK; 579 tmp |= TA_SURE_OVERRIDE | TA_SURE(0); 580 intel_de_write(dev_priv, 581 DSI_TA_TIMING_PARAM(port), tmp); 582 } 583 } 584 } 585 586 if (IS_ELKHARTLAKE(dev_priv)) { 587 for_each_dsi_phy(phy, intel_dsi->phys) { 588 tmp = intel_de_read(dev_priv, ICL_DPHY_CHKN(phy)); 589 tmp |= ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP; 590 intel_de_write(dev_priv, ICL_DPHY_CHKN(phy), tmp); 591 } 592 } 593 } 594 595 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder) 596 { 597 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 598 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 599 u32 tmp; 600 enum phy phy; 601 602 mutex_lock(&dev_priv->dpll.lock); 603 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 604 for_each_dsi_phy(phy, intel_dsi->phys) 605 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 606 607 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 608 mutex_unlock(&dev_priv->dpll.lock); 609 } 610 611 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 612 { 613 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 614 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 615 u32 tmp; 616 enum phy phy; 617 618 mutex_lock(&dev_priv->dpll.lock); 619 tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 620 for_each_dsi_phy(phy, intel_dsi->phys) 621 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 622 623 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp); 624 mutex_unlock(&dev_priv->dpll.lock); 625 } 626 627 static void gen11_dsi_map_pll(struct intel_encoder *encoder, 628 const struct intel_crtc_state *crtc_state) 629 { 630 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 631 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 632 struct intel_shared_dpll *pll = crtc_state->shared_dpll; 633 enum phy phy; 634 u32 val; 635 636 mutex_lock(&dev_priv->dpll.lock); 637 638 val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0); 639 for_each_dsi_phy(phy, intel_dsi->phys) { 640 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy); 641 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); 642 } 643 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 644 645 for_each_dsi_phy(phy, intel_dsi->phys) { 646 if (INTEL_GEN(dev_priv) >= 12) 647 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 648 else 649 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy); 650 } 651 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val); 652 653 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0); 654 655 mutex_unlock(&dev_priv->dpll.lock); 656 } 657 658 static void 659 gen11_dsi_configure_transcoder(struct intel_encoder *encoder, 660 const struct intel_crtc_state *pipe_config) 661 { 662 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 663 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 664 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); 665 enum pipe pipe = intel_crtc->pipe; 666 u32 tmp; 667 enum port port; 668 enum transcoder dsi_trans; 669 670 for_each_dsi_port(port, intel_dsi->ports) { 671 dsi_trans = dsi_port_to_transcoder(port); 672 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)); 673 674 if (intel_dsi->eotp_pkt) 675 tmp &= ~EOTP_DISABLED; 676 else 677 tmp |= EOTP_DISABLED; 678 679 /* enable link calibration if freq > 1.5Gbps */ 680 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { 681 tmp &= ~LINK_CALIBRATION_MASK; 682 tmp |= CALIBRATION_ENABLED_INITIAL_ONLY; 683 } 684 685 /* configure continuous clock */ 686 tmp &= ~CONTINUOUS_CLK_MASK; 687 if (intel_dsi->clock_stop) 688 tmp |= CLK_ENTER_LP_AFTER_DATA; 689 else 690 tmp |= CLK_HS_CONTINUOUS; 691 692 /* configure buffer threshold limit to minimum */ 693 tmp &= ~PIX_BUF_THRESHOLD_MASK; 694 tmp |= PIX_BUF_THRESHOLD_1_4; 695 696 /* set virtual channel to '0' */ 697 tmp &= ~PIX_VIRT_CHAN_MASK; 698 tmp |= PIX_VIRT_CHAN(0); 699 700 /* program BGR transmission */ 701 if (intel_dsi->bgr_enabled) 702 tmp |= BGR_TRANSMISSION; 703 704 /* select pixel format */ 705 tmp &= ~PIX_FMT_MASK; 706 if (pipe_config->dsc.compression_enable) { 707 tmp |= PIX_FMT_COMPRESSED; 708 } else { 709 switch (intel_dsi->pixel_format) { 710 default: 711 MISSING_CASE(intel_dsi->pixel_format); 712 /* fallthrough */ 713 case MIPI_DSI_FMT_RGB565: 714 tmp |= PIX_FMT_RGB565; 715 break; 716 case MIPI_DSI_FMT_RGB666_PACKED: 717 tmp |= PIX_FMT_RGB666_PACKED; 718 break; 719 case MIPI_DSI_FMT_RGB666: 720 tmp |= PIX_FMT_RGB666_LOOSE; 721 break; 722 case MIPI_DSI_FMT_RGB888: 723 tmp |= PIX_FMT_RGB888; 724 break; 725 } 726 } 727 728 if (INTEL_GEN(dev_priv) >= 12) { 729 if (is_vid_mode(intel_dsi)) 730 tmp |= BLANKING_PACKET_ENABLE; 731 } 732 733 /* program DSI operation mode */ 734 if (is_vid_mode(intel_dsi)) { 735 tmp &= ~OP_MODE_MASK; 736 switch (intel_dsi->video_mode_format) { 737 default: 738 MISSING_CASE(intel_dsi->video_mode_format); 739 /* fallthrough */ 740 case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS: 741 tmp |= VIDEO_MODE_SYNC_EVENT; 742 break; 743 case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE: 744 tmp |= VIDEO_MODE_SYNC_PULSE; 745 break; 746 } 747 } 748 749 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp); 750 } 751 752 /* enable port sync mode if dual link */ 753 if (intel_dsi->dual_link) { 754 for_each_dsi_port(port, intel_dsi->ports) { 755 dsi_trans = dsi_port_to_transcoder(port); 756 tmp = intel_de_read(dev_priv, 757 TRANS_DDI_FUNC_CTL2(dsi_trans)); 758 tmp |= PORT_SYNC_MODE_ENABLE; 759 intel_de_write(dev_priv, 760 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 761 } 762 763 /* configure stream splitting */ 764 configure_dual_link_mode(encoder, pipe_config); 765 } 766 767 for_each_dsi_port(port, intel_dsi->ports) { 768 dsi_trans = dsi_port_to_transcoder(port); 769 770 /* select data lane width */ 771 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 772 tmp &= ~DDI_PORT_WIDTH_MASK; 773 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); 774 775 /* select input pipe */ 776 tmp &= ~TRANS_DDI_EDP_INPUT_MASK; 777 switch (pipe) { 778 default: 779 MISSING_CASE(pipe); 780 /* fallthrough */ 781 case PIPE_A: 782 tmp |= TRANS_DDI_EDP_INPUT_A_ON; 783 break; 784 case PIPE_B: 785 tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF; 786 break; 787 case PIPE_C: 788 tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF; 789 break; 790 case PIPE_D: 791 tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF; 792 break; 793 } 794 795 /* enable DDI buffer */ 796 tmp |= TRANS_DDI_FUNC_ENABLE; 797 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 798 } 799 800 /* wait for link ready */ 801 for_each_dsi_port(port, intel_dsi->ports) { 802 dsi_trans = dsi_port_to_transcoder(port); 803 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) & 804 LINK_READY), 2500)) 805 drm_err(&dev_priv->drm, "DSI link not ready\n"); 806 } 807 } 808 809 static void 810 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, 811 const struct intel_crtc_state *crtc_state) 812 { 813 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 814 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 815 const struct drm_display_mode *adjusted_mode = 816 &crtc_state->hw.adjusted_mode; 817 enum port port; 818 enum transcoder dsi_trans; 819 /* horizontal timings */ 820 u16 htotal, hactive, hsync_start, hsync_end, hsync_size; 821 u16 hback_porch; 822 /* vertical timings */ 823 u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift; 824 int mul = 1, div = 1; 825 826 /* 827 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account 828 * for slower link speed if DSC is enabled. 829 * 830 * The compression frequency ratio is the ratio between compressed and 831 * non-compressed link speeds, and simplifies down to the ratio between 832 * compressed and non-compressed bpp. 833 */ 834 if (crtc_state->dsc.compression_enable) { 835 mul = crtc_state->dsc.compressed_bpp; 836 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 837 } 838 839 hactive = adjusted_mode->crtc_hdisplay; 840 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 841 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 842 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 843 hsync_size = hsync_end - hsync_start; 844 hback_porch = (adjusted_mode->crtc_htotal - 845 adjusted_mode->crtc_hsync_end); 846 vactive = adjusted_mode->crtc_vdisplay; 847 vtotal = adjusted_mode->crtc_vtotal; 848 vsync_start = adjusted_mode->crtc_vsync_start; 849 vsync_end = adjusted_mode->crtc_vsync_end; 850 vsync_shift = hsync_start - htotal / 2; 851 852 if (intel_dsi->dual_link) { 853 hactive /= 2; 854 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 855 hactive += intel_dsi->pixel_overlap; 856 htotal /= 2; 857 } 858 859 /* minimum hactive as per bspec: 256 pixels */ 860 if (adjusted_mode->crtc_hdisplay < 256) 861 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); 862 863 /* if RGB666 format, then hactive must be multiple of 4 pixels */ 864 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) 865 drm_err(&dev_priv->drm, 866 "hactive pixels are not multiple of 4\n"); 867 868 /* program TRANS_HTOTAL register */ 869 for_each_dsi_port(port, intel_dsi->ports) { 870 dsi_trans = dsi_port_to_transcoder(port); 871 intel_de_write(dev_priv, HTOTAL(dsi_trans), 872 (hactive - 1) | ((htotal - 1) << 16)); 873 } 874 875 /* TRANS_HSYNC register to be programmed only for video mode */ 876 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 877 if (intel_dsi->video_mode_format == 878 VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE) { 879 /* BSPEC: hsync size should be atleast 16 pixels */ 880 if (hsync_size < 16) 881 drm_err(&dev_priv->drm, 882 "hsync size < 16 pixels\n"); 883 } 884 885 if (hback_porch < 16) 886 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); 887 888 if (intel_dsi->dual_link) { 889 hsync_start /= 2; 890 hsync_end /= 2; 891 } 892 893 for_each_dsi_port(port, intel_dsi->ports) { 894 dsi_trans = dsi_port_to_transcoder(port); 895 intel_de_write(dev_priv, HSYNC(dsi_trans), 896 (hsync_start - 1) | ((hsync_end - 1) << 16)); 897 } 898 } 899 900 /* program TRANS_VTOTAL register */ 901 for_each_dsi_port(port, intel_dsi->ports) { 902 dsi_trans = dsi_port_to_transcoder(port); 903 /* 904 * FIXME: Programing this by assuming progressive mode, since 905 * non-interlaced info from VBT is not saved inside 906 * struct drm_display_mode. 907 * For interlace mode: program required pixel minus 2 908 */ 909 intel_de_write(dev_priv, VTOTAL(dsi_trans), 910 (vactive - 1) | ((vtotal - 1) << 16)); 911 } 912 913 if (vsync_end < vsync_start || vsync_end > vtotal) 914 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); 915 916 if (vsync_start < vactive) 917 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); 918 919 /* program TRANS_VSYNC register */ 920 for_each_dsi_port(port, intel_dsi->ports) { 921 dsi_trans = dsi_port_to_transcoder(port); 922 intel_de_write(dev_priv, VSYNC(dsi_trans), 923 (vsync_start - 1) | ((vsync_end - 1) << 16)); 924 } 925 926 /* 927 * FIXME: It has to be programmed only for interlaced 928 * modes. Put the check condition here once interlaced 929 * info available as described above. 930 * program TRANS_VSYNCSHIFT register 931 */ 932 for_each_dsi_port(port, intel_dsi->ports) { 933 dsi_trans = dsi_port_to_transcoder(port); 934 intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans), vsync_shift); 935 } 936 937 /* program TRANS_VBLANK register, should be same as vtotal programmed */ 938 if (INTEL_GEN(dev_priv) >= 12) { 939 for_each_dsi_port(port, intel_dsi->ports) { 940 dsi_trans = dsi_port_to_transcoder(port); 941 intel_de_write(dev_priv, VBLANK(dsi_trans), 942 (vactive - 1) | ((vtotal - 1) << 16)); 943 } 944 } 945 } 946 947 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) 948 { 949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 950 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 951 enum port port; 952 enum transcoder dsi_trans; 953 u32 tmp; 954 955 for_each_dsi_port(port, intel_dsi->ports) { 956 dsi_trans = dsi_port_to_transcoder(port); 957 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 958 tmp |= PIPECONF_ENABLE; 959 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 960 961 /* wait for transcoder to be enabled */ 962 if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans), 963 I965_PIPECONF_ACTIVE, 10)) 964 drm_err(&dev_priv->drm, 965 "DSI transcoder not enabled\n"); 966 } 967 } 968 969 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, 970 const struct intel_crtc_state *crtc_state) 971 { 972 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 973 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 974 enum port port; 975 enum transcoder dsi_trans; 976 u32 tmp, hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul; 977 978 /* 979 * escape clock count calculation: 980 * BYTE_CLK_COUNT = TIME_NS/(8 * UI) 981 * UI (nsec) = (10^6)/Bitrate 982 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate 983 * ESCAPE_CLK_COUNT = TIME_NS/ESC_CLK_NS 984 */ 985 divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; 986 mul = 8 * 1000000; 987 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, 988 divisor); 989 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); 990 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); 991 992 for_each_dsi_port(port, intel_dsi->ports) { 993 dsi_trans = dsi_port_to_transcoder(port); 994 995 /* program hst_tx_timeout */ 996 tmp = intel_de_read(dev_priv, DSI_HSTX_TO(dsi_trans)); 997 tmp &= ~HSTX_TIMEOUT_VALUE_MASK; 998 tmp |= HSTX_TIMEOUT_VALUE(hs_tx_timeout); 999 intel_de_write(dev_priv, DSI_HSTX_TO(dsi_trans), tmp); 1000 1001 /* FIXME: DSI_CALIB_TO */ 1002 1003 /* program lp_rx_host timeout */ 1004 tmp = intel_de_read(dev_priv, DSI_LPRX_HOST_TO(dsi_trans)); 1005 tmp &= ~LPRX_TIMEOUT_VALUE_MASK; 1006 tmp |= LPRX_TIMEOUT_VALUE(lp_rx_timeout); 1007 intel_de_write(dev_priv, DSI_LPRX_HOST_TO(dsi_trans), tmp); 1008 1009 /* FIXME: DSI_PWAIT_TO */ 1010 1011 /* program turn around timeout */ 1012 tmp = intel_de_read(dev_priv, DSI_TA_TO(dsi_trans)); 1013 tmp &= ~TA_TIMEOUT_VALUE_MASK; 1014 tmp |= TA_TIMEOUT_VALUE(ta_timeout); 1015 intel_de_write(dev_priv, DSI_TA_TO(dsi_trans), tmp); 1016 } 1017 } 1018 1019 static void 1020 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder, 1021 const struct intel_crtc_state *crtc_state) 1022 { 1023 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1024 1025 /* step 4a: power up all lanes of the DDI used by DSI */ 1026 gen11_dsi_power_up_lanes(encoder); 1027 1028 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ 1029 gen11_dsi_config_phy_lanes_sequence(encoder); 1030 1031 /* step 4c: configure voltage swing and skew */ 1032 gen11_dsi_voltage_swing_program_seq(encoder); 1033 1034 /* enable DDI buffer */ 1035 gen11_dsi_enable_ddi_buffer(encoder); 1036 1037 /* setup D-PHY timings */ 1038 gen11_dsi_setup_dphy_timings(encoder, crtc_state); 1039 1040 /* step 4h: setup DSI protocol timeouts */ 1041 gen11_dsi_setup_timeouts(encoder, crtc_state); 1042 1043 /* Step (4h, 4i, 4j, 4k): Configure transcoder */ 1044 gen11_dsi_configure_transcoder(encoder, crtc_state); 1045 1046 /* Step 4l: Gate DDI clocks */ 1047 if (IS_GEN(dev_priv, 11)) 1048 gen11_dsi_gate_clocks(encoder); 1049 } 1050 1051 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder) 1052 { 1053 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1054 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1055 struct mipi_dsi_device *dsi; 1056 enum port port; 1057 enum transcoder dsi_trans; 1058 u32 tmp; 1059 int ret; 1060 1061 /* set maximum return packet size */ 1062 for_each_dsi_port(port, intel_dsi->ports) { 1063 dsi_trans = dsi_port_to_transcoder(port); 1064 1065 /* 1066 * FIXME: This uses the number of DW's currently in the payload 1067 * receive queue. This is probably not what we want here. 1068 */ 1069 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans)); 1070 tmp &= NUMBER_RX_PLOAD_DW_MASK; 1071 /* multiply "Number Rx Payload DW" by 4 to get max value */ 1072 tmp = tmp * 4; 1073 dsi = intel_dsi->dsi_hosts[port]->device; 1074 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp); 1075 if (ret < 0) 1076 drm_err(&dev_priv->drm, 1077 "error setting max return pkt size%d\n", tmp); 1078 } 1079 1080 /* panel power on related mipi dsi vbt sequences */ 1081 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON); 1082 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); 1083 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET); 1084 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP); 1085 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON); 1086 1087 /* ensure all panel commands dispatched before enabling transcoder */ 1088 wait_for_cmds_dispatched_to_panel(encoder); 1089 } 1090 1091 static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder, 1092 const struct intel_crtc_state *crtc_state, 1093 const struct drm_connector_state *conn_state) 1094 { 1095 /* step2: enable IO power */ 1096 gen11_dsi_enable_io_power(encoder); 1097 1098 /* step3: enable DSI PLL */ 1099 gen11_dsi_program_esc_clk_div(encoder, crtc_state); 1100 } 1101 1102 static void gen11_dsi_pre_enable(struct intel_encoder *encoder, 1103 const struct intel_crtc_state *pipe_config, 1104 const struct drm_connector_state *conn_state) 1105 { 1106 /* step3b */ 1107 gen11_dsi_map_pll(encoder, pipe_config); 1108 1109 /* step4: enable DSI port and DPHY */ 1110 gen11_dsi_enable_port_and_phy(encoder, pipe_config); 1111 1112 /* step5: program and powerup panel */ 1113 gen11_dsi_powerup_panel(encoder); 1114 1115 intel_dsc_enable(encoder, pipe_config); 1116 1117 /* step6c: configure transcoder timings */ 1118 gen11_dsi_set_transcoder_timings(encoder, pipe_config); 1119 } 1120 1121 static void gen11_dsi_enable(struct intel_encoder *encoder, 1122 const struct intel_crtc_state *crtc_state, 1123 const struct drm_connector_state *conn_state) 1124 { 1125 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1126 1127 WARN_ON(crtc_state->has_pch_encoder); 1128 1129 /* step6d: enable dsi transcoder */ 1130 gen11_dsi_enable_transcoder(encoder); 1131 1132 /* step7: enable backlight */ 1133 intel_panel_enable_backlight(crtc_state, conn_state); 1134 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON); 1135 1136 intel_crtc_vblank_on(crtc_state); 1137 } 1138 1139 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) 1140 { 1141 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1142 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1143 enum port port; 1144 enum transcoder dsi_trans; 1145 u32 tmp; 1146 1147 for_each_dsi_port(port, intel_dsi->ports) { 1148 dsi_trans = dsi_port_to_transcoder(port); 1149 1150 /* disable transcoder */ 1151 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1152 tmp &= ~PIPECONF_ENABLE; 1153 intel_de_write(dev_priv, PIPECONF(dsi_trans), tmp); 1154 1155 /* wait for transcoder to be disabled */ 1156 if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans), 1157 I965_PIPECONF_ACTIVE, 50)) 1158 drm_err(&dev_priv->drm, 1159 "DSI trancoder not disabled\n"); 1160 } 1161 } 1162 1163 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder) 1164 { 1165 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1166 1167 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF); 1168 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET); 1169 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF); 1170 1171 /* ensure cmds dispatched to panel */ 1172 wait_for_cmds_dispatched_to_panel(encoder); 1173 } 1174 1175 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) 1176 { 1177 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1178 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1179 enum port port; 1180 enum transcoder dsi_trans; 1181 u32 tmp; 1182 1183 /* put dsi link in ULPS */ 1184 for_each_dsi_port(port, intel_dsi->ports) { 1185 dsi_trans = dsi_port_to_transcoder(port); 1186 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)); 1187 tmp |= LINK_ENTER_ULPS; 1188 tmp &= ~LINK_ULPS_TYPE_LP11; 1189 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp); 1190 1191 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & 1192 LINK_IN_ULPS), 1193 10)) 1194 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); 1195 } 1196 1197 /* disable ddi function */ 1198 for_each_dsi_port(port, intel_dsi->ports) { 1199 dsi_trans = dsi_port_to_transcoder(port); 1200 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1201 tmp &= ~TRANS_DDI_FUNC_ENABLE; 1202 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); 1203 } 1204 1205 /* disable port sync mode if dual link */ 1206 if (intel_dsi->dual_link) { 1207 for_each_dsi_port(port, intel_dsi->ports) { 1208 dsi_trans = dsi_port_to_transcoder(port); 1209 tmp = intel_de_read(dev_priv, 1210 TRANS_DDI_FUNC_CTL2(dsi_trans)); 1211 tmp &= ~PORT_SYNC_MODE_ENABLE; 1212 intel_de_write(dev_priv, 1213 TRANS_DDI_FUNC_CTL2(dsi_trans), tmp); 1214 } 1215 } 1216 } 1217 1218 static void gen11_dsi_disable_port(struct intel_encoder *encoder) 1219 { 1220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1221 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1222 u32 tmp; 1223 enum port port; 1224 1225 gen11_dsi_ungate_clocks(encoder); 1226 for_each_dsi_port(port, intel_dsi->ports) { 1227 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); 1228 tmp &= ~DDI_BUF_CTL_ENABLE; 1229 intel_de_write(dev_priv, DDI_BUF_CTL(port), tmp); 1230 1231 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & 1232 DDI_BUF_IS_IDLE), 1233 8)) 1234 drm_err(&dev_priv->drm, 1235 "DDI port:%c buffer not idle\n", 1236 port_name(port)); 1237 } 1238 gen11_dsi_gate_clocks(encoder); 1239 } 1240 1241 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder) 1242 { 1243 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1244 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1245 enum port port; 1246 u32 tmp; 1247 1248 for_each_dsi_port(port, intel_dsi->ports) { 1249 intel_wakeref_t wakeref; 1250 1251 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); 1252 intel_display_power_put(dev_priv, 1253 port == PORT_A ? 1254 POWER_DOMAIN_PORT_DDI_A_IO : 1255 POWER_DOMAIN_PORT_DDI_B_IO, 1256 wakeref); 1257 } 1258 1259 /* set mode to DDI */ 1260 for_each_dsi_port(port, intel_dsi->ports) { 1261 tmp = intel_de_read(dev_priv, ICL_DSI_IO_MODECTL(port)); 1262 tmp &= ~COMBO_PHY_MODE_DSI; 1263 intel_de_write(dev_priv, ICL_DSI_IO_MODECTL(port), tmp); 1264 } 1265 } 1266 1267 static void gen11_dsi_disable(struct intel_encoder *encoder, 1268 const struct intel_crtc_state *old_crtc_state, 1269 const struct drm_connector_state *old_conn_state) 1270 { 1271 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1272 1273 /* step1: turn off backlight */ 1274 intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF); 1275 intel_panel_disable_backlight(old_conn_state); 1276 1277 /* step2d,e: disable transcoder and wait */ 1278 gen11_dsi_disable_transcoder(encoder); 1279 1280 /* step2f,g: powerdown panel */ 1281 gen11_dsi_powerdown_panel(encoder); 1282 1283 /* step2h,i,j: deconfig trancoder */ 1284 gen11_dsi_deconfigure_trancoder(encoder); 1285 1286 /* step3: disable port */ 1287 gen11_dsi_disable_port(encoder); 1288 1289 /* step4: disable IO power */ 1290 gen11_dsi_disable_io_power(encoder); 1291 } 1292 1293 static void gen11_dsi_post_disable(struct intel_encoder *encoder, 1294 const struct intel_crtc_state *old_crtc_state, 1295 const struct drm_connector_state *old_conn_state) 1296 { 1297 intel_crtc_vblank_off(old_crtc_state); 1298 1299 intel_dsc_disable(old_crtc_state); 1300 1301 skl_scaler_disable(old_crtc_state); 1302 } 1303 1304 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, 1305 struct drm_display_mode *mode) 1306 { 1307 /* FIXME: DSC? */ 1308 return intel_dsi_mode_valid(connector, mode); 1309 } 1310 1311 static void gen11_dsi_get_timings(struct intel_encoder *encoder, 1312 struct intel_crtc_state *pipe_config) 1313 { 1314 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1315 struct drm_display_mode *adjusted_mode = 1316 &pipe_config->hw.adjusted_mode; 1317 1318 if (pipe_config->dsc.compressed_bpp) { 1319 int div = pipe_config->dsc.compressed_bpp; 1320 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); 1321 1322 adjusted_mode->crtc_htotal = 1323 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); 1324 adjusted_mode->crtc_hsync_start = 1325 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); 1326 adjusted_mode->crtc_hsync_end = 1327 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); 1328 } 1329 1330 if (intel_dsi->dual_link) { 1331 adjusted_mode->crtc_hdisplay *= 2; 1332 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 1333 adjusted_mode->crtc_hdisplay -= 1334 intel_dsi->pixel_overlap; 1335 adjusted_mode->crtc_htotal *= 2; 1336 } 1337 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; 1338 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; 1339 1340 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { 1341 if (intel_dsi->dual_link) { 1342 adjusted_mode->crtc_hsync_start *= 2; 1343 adjusted_mode->crtc_hsync_end *= 2; 1344 } 1345 } 1346 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; 1347 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; 1348 } 1349 1350 static void gen11_dsi_get_config(struct intel_encoder *encoder, 1351 struct intel_crtc_state *pipe_config) 1352 { 1353 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1354 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1355 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1356 1357 intel_dsc_get_config(encoder, pipe_config); 1358 1359 /* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */ 1360 pipe_config->port_clock = intel_dpll_get_freq(i915, 1361 pipe_config->shared_dpll); 1362 1363 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; 1364 if (intel_dsi->dual_link) 1365 pipe_config->hw.adjusted_mode.crtc_clock *= 2; 1366 1367 gen11_dsi_get_timings(encoder, pipe_config); 1368 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); 1369 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); 1370 } 1371 1372 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, 1373 struct intel_crtc_state *crtc_state) 1374 { 1375 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1376 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1377 int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10; 1378 bool use_dsc; 1379 int ret; 1380 1381 use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); 1382 if (!use_dsc) 1383 return 0; 1384 1385 if (crtc_state->pipe_bpp < 8 * 3) 1386 return -EINVAL; 1387 1388 /* FIXME: split only when necessary */ 1389 if (crtc_state->dsc.slice_count > 1) 1390 crtc_state->dsc.dsc_split = true; 1391 1392 vdsc_cfg->convert_rgb = true; 1393 1394 ret = intel_dsc_compute_params(encoder, crtc_state); 1395 if (ret) 1396 return ret; 1397 1398 /* DSI specific sanity checks on the common code */ 1399 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); 1400 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); 1401 drm_WARN_ON(&dev_priv->drm, 1402 vdsc_cfg->pic_width % vdsc_cfg->slice_width); 1403 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); 1404 drm_WARN_ON(&dev_priv->drm, 1405 vdsc_cfg->pic_height % vdsc_cfg->slice_height); 1406 1407 ret = drm_dsc_compute_rc_parameters(vdsc_cfg); 1408 if (ret) 1409 return ret; 1410 1411 crtc_state->dsc.compression_enable = true; 1412 1413 return 0; 1414 } 1415 1416 static int gen11_dsi_compute_config(struct intel_encoder *encoder, 1417 struct intel_crtc_state *pipe_config, 1418 struct drm_connector_state *conn_state) 1419 { 1420 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, 1421 base); 1422 struct intel_connector *intel_connector = intel_dsi->attached_connector; 1423 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1424 const struct drm_display_mode *fixed_mode = 1425 intel_connector->panel.fixed_mode; 1426 struct drm_display_mode *adjusted_mode = 1427 &pipe_config->hw.adjusted_mode; 1428 1429 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1430 intel_fixed_panel_mode(fixed_mode, adjusted_mode); 1431 intel_pch_panel_fitting(crtc, pipe_config, conn_state->scaling_mode); 1432 1433 adjusted_mode->flags = 0; 1434 1435 /* Dual link goes to trancoder DSI'0' */ 1436 if (intel_dsi->ports == BIT(PORT_B)) 1437 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; 1438 else 1439 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; 1440 1441 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) 1442 pipe_config->pipe_bpp = 24; 1443 else 1444 pipe_config->pipe_bpp = 18; 1445 1446 pipe_config->clock_set = true; 1447 1448 if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) 1449 DRM_DEBUG_KMS("Attempting to use DSC failed\n"); 1450 1451 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; 1452 1453 return 0; 1454 } 1455 1456 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder, 1457 struct intel_crtc_state *crtc_state) 1458 { 1459 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1460 1461 get_dsi_io_power_domains(i915, 1462 enc_to_intel_dsi(encoder)); 1463 1464 if (crtc_state->dsc.compression_enable) 1465 intel_display_power_get(i915, 1466 intel_dsc_power_domain(crtc_state)); 1467 } 1468 1469 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, 1470 enum pipe *pipe) 1471 { 1472 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1473 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); 1474 enum transcoder dsi_trans; 1475 intel_wakeref_t wakeref; 1476 enum port port; 1477 bool ret = false; 1478 u32 tmp; 1479 1480 wakeref = intel_display_power_get_if_enabled(dev_priv, 1481 encoder->power_domain); 1482 if (!wakeref) 1483 return false; 1484 1485 for_each_dsi_port(port, intel_dsi->ports) { 1486 dsi_trans = dsi_port_to_transcoder(port); 1487 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); 1488 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { 1489 case TRANS_DDI_EDP_INPUT_A_ON: 1490 *pipe = PIPE_A; 1491 break; 1492 case TRANS_DDI_EDP_INPUT_B_ONOFF: 1493 *pipe = PIPE_B; 1494 break; 1495 case TRANS_DDI_EDP_INPUT_C_ONOFF: 1496 *pipe = PIPE_C; 1497 break; 1498 case TRANS_DDI_EDP_INPUT_D_ONOFF: 1499 *pipe = PIPE_D; 1500 break; 1501 default: 1502 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); 1503 goto out; 1504 } 1505 1506 tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans)); 1507 ret = tmp & PIPECONF_ENABLE; 1508 } 1509 out: 1510 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 1511 return ret; 1512 } 1513 1514 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder) 1515 { 1516 intel_encoder_destroy(encoder); 1517 } 1518 1519 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = { 1520 .destroy = gen11_dsi_encoder_destroy, 1521 }; 1522 1523 static const struct drm_connector_funcs gen11_dsi_connector_funcs = { 1524 .late_register = intel_connector_register, 1525 .early_unregister = intel_connector_unregister, 1526 .destroy = intel_connector_destroy, 1527 .fill_modes = drm_helper_probe_single_connector_modes, 1528 .atomic_get_property = intel_digital_connector_atomic_get_property, 1529 .atomic_set_property = intel_digital_connector_atomic_set_property, 1530 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1531 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 1532 }; 1533 1534 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = { 1535 .get_modes = intel_dsi_get_modes, 1536 .mode_valid = gen11_dsi_mode_valid, 1537 .atomic_check = intel_digital_connector_atomic_check, 1538 }; 1539 1540 static int gen11_dsi_host_attach(struct mipi_dsi_host *host, 1541 struct mipi_dsi_device *dsi) 1542 { 1543 return 0; 1544 } 1545 1546 static int gen11_dsi_host_detach(struct mipi_dsi_host *host, 1547 struct mipi_dsi_device *dsi) 1548 { 1549 return 0; 1550 } 1551 1552 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host, 1553 const struct mipi_dsi_msg *msg) 1554 { 1555 struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); 1556 struct mipi_dsi_packet dsi_pkt; 1557 ssize_t ret; 1558 bool enable_lpdt = false; 1559 1560 ret = mipi_dsi_create_packet(&dsi_pkt, msg); 1561 if (ret < 0) 1562 return ret; 1563 1564 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1565 enable_lpdt = true; 1566 1567 /* send packet header */ 1568 ret = dsi_send_pkt_hdr(intel_dsi_host, dsi_pkt, enable_lpdt); 1569 if (ret < 0) 1570 return ret; 1571 1572 /* only long packet contains payload */ 1573 if (mipi_dsi_packet_format_is_long(msg->type)) { 1574 ret = dsi_send_pkt_payld(intel_dsi_host, dsi_pkt); 1575 if (ret < 0) 1576 return ret; 1577 } 1578 1579 //TODO: add payload receive code if needed 1580 1581 ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length; 1582 1583 return ret; 1584 } 1585 1586 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = { 1587 .attach = gen11_dsi_host_attach, 1588 .detach = gen11_dsi_host_detach, 1589 .transfer = gen11_dsi_host_transfer, 1590 }; 1591 1592 #define ICL_PREPARE_CNT_MAX 0x7 1593 #define ICL_CLK_ZERO_CNT_MAX 0xf 1594 #define ICL_TRAIL_CNT_MAX 0x7 1595 #define ICL_TCLK_PRE_CNT_MAX 0x3 1596 #define ICL_TCLK_POST_CNT_MAX 0x7 1597 #define ICL_HS_ZERO_CNT_MAX 0xf 1598 #define ICL_EXIT_ZERO_CNT_MAX 0x7 1599 1600 static void icl_dphy_param_init(struct intel_dsi *intel_dsi) 1601 { 1602 struct drm_device *dev = intel_dsi->base.base.dev; 1603 struct drm_i915_private *dev_priv = to_i915(dev); 1604 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 1605 u32 tlpx_ns; 1606 u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt; 1607 u32 ths_prepare_ns, tclk_trail_ns; 1608 u32 hs_zero_cnt; 1609 u32 tclk_pre_cnt, tclk_post_cnt; 1610 1611 tlpx_ns = intel_dsi_tlpx_ns(intel_dsi); 1612 1613 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); 1614 ths_prepare_ns = max(mipi_config->ths_prepare, 1615 mipi_config->tclk_prepare); 1616 1617 /* 1618 * prepare cnt in escape clocks 1619 * this field represents a hexadecimal value with a precision 1620 * of 1.2 – i.e. the most significant bit is the integer 1621 * and the least significant 2 bits are fraction bits. 1622 * so, the field can represent a range of 0.25 to 1.75 1623 */ 1624 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns); 1625 if (prepare_cnt > ICL_PREPARE_CNT_MAX) { 1626 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", 1627 prepare_cnt); 1628 prepare_cnt = ICL_PREPARE_CNT_MAX; 1629 } 1630 1631 /* clk zero count in escape clocks */ 1632 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - 1633 ths_prepare_ns, tlpx_ns); 1634 if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) { 1635 drm_dbg_kms(&dev_priv->drm, 1636 "clk_zero_cnt out of range (%d)\n", clk_zero_cnt); 1637 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX; 1638 } 1639 1640 /* trail cnt in escape clocks*/ 1641 trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns); 1642 if (trail_cnt > ICL_TRAIL_CNT_MAX) { 1643 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", 1644 trail_cnt); 1645 trail_cnt = ICL_TRAIL_CNT_MAX; 1646 } 1647 1648 /* tclk pre count in escape clocks */ 1649 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); 1650 if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) { 1651 drm_dbg_kms(&dev_priv->drm, 1652 "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt); 1653 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX; 1654 } 1655 1656 /* tclk post count in escape clocks */ 1657 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); 1658 if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) { 1659 drm_dbg_kms(&dev_priv->drm, 1660 "tclk_post_cnt out of range (%d)\n", 1661 tclk_post_cnt); 1662 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX; 1663 } 1664 1665 /* hs zero cnt in escape clocks */ 1666 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - 1667 ths_prepare_ns, tlpx_ns); 1668 if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) { 1669 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", 1670 hs_zero_cnt); 1671 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX; 1672 } 1673 1674 /* hs exit zero cnt in escape clocks */ 1675 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); 1676 if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) { 1677 drm_dbg_kms(&dev_priv->drm, 1678 "exit_zero_cnt out of range (%d)\n", 1679 exit_zero_cnt); 1680 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX; 1681 } 1682 1683 /* clock lane dphy timings */ 1684 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | 1685 CLK_PREPARE(prepare_cnt) | 1686 CLK_ZERO_OVERRIDE | 1687 CLK_ZERO(clk_zero_cnt) | 1688 CLK_PRE_OVERRIDE | 1689 CLK_PRE(tclk_pre_cnt) | 1690 CLK_POST_OVERRIDE | 1691 CLK_POST(tclk_post_cnt) | 1692 CLK_TRAIL_OVERRIDE | 1693 CLK_TRAIL(trail_cnt)); 1694 1695 /* data lanes dphy timings */ 1696 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | 1697 HS_PREPARE(prepare_cnt) | 1698 HS_ZERO_OVERRIDE | 1699 HS_ZERO(hs_zero_cnt) | 1700 HS_TRAIL_OVERRIDE | 1701 HS_TRAIL(trail_cnt) | 1702 HS_EXIT_OVERRIDE | 1703 HS_EXIT(exit_zero_cnt)); 1704 1705 intel_dsi_log_params(intel_dsi); 1706 } 1707 1708 static void icl_dsi_add_properties(struct intel_connector *connector) 1709 { 1710 u32 allowed_scalers; 1711 1712 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | 1713 BIT(DRM_MODE_SCALE_FULLSCREEN) | 1714 BIT(DRM_MODE_SCALE_CENTER); 1715 1716 drm_connector_attach_scaling_mode_property(&connector->base, 1717 allowed_scalers); 1718 1719 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; 1720 1721 drm_connector_set_panel_orientation_with_quirk(&connector->base, 1722 intel_dsi_get_panel_orientation(connector), 1723 connector->panel.fixed_mode->hdisplay, 1724 connector->panel.fixed_mode->vdisplay); 1725 } 1726 1727 void icl_dsi_init(struct drm_i915_private *dev_priv) 1728 { 1729 struct drm_device *dev = &dev_priv->drm; 1730 struct intel_dsi *intel_dsi; 1731 struct intel_encoder *encoder; 1732 struct intel_connector *intel_connector; 1733 struct drm_connector *connector; 1734 struct drm_display_mode *fixed_mode; 1735 enum port port; 1736 1737 if (!intel_bios_is_dsi_present(dev_priv, &port)) 1738 return; 1739 1740 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); 1741 if (!intel_dsi) 1742 return; 1743 1744 intel_connector = intel_connector_alloc(); 1745 if (!intel_connector) { 1746 kfree(intel_dsi); 1747 return; 1748 } 1749 1750 encoder = &intel_dsi->base; 1751 intel_dsi->attached_connector = intel_connector; 1752 connector = &intel_connector->base; 1753 1754 /* register DSI encoder with DRM subsystem */ 1755 drm_encoder_init(dev, &encoder->base, &gen11_dsi_encoder_funcs, 1756 DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port)); 1757 1758 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; 1759 encoder->pre_enable = gen11_dsi_pre_enable; 1760 encoder->enable = gen11_dsi_enable; 1761 encoder->disable = gen11_dsi_disable; 1762 encoder->post_disable = gen11_dsi_post_disable; 1763 encoder->port = port; 1764 encoder->get_config = gen11_dsi_get_config; 1765 encoder->update_pipe = intel_panel_update_backlight; 1766 encoder->compute_config = gen11_dsi_compute_config; 1767 encoder->get_hw_state = gen11_dsi_get_hw_state; 1768 encoder->type = INTEL_OUTPUT_DSI; 1769 encoder->cloneable = 0; 1770 encoder->pipe_mask = ~0; 1771 encoder->power_domain = POWER_DOMAIN_PORT_DSI; 1772 encoder->get_power_domains = gen11_dsi_get_power_domains; 1773 1774 /* register DSI connector with DRM subsystem */ 1775 drm_connector_init(dev, connector, &gen11_dsi_connector_funcs, 1776 DRM_MODE_CONNECTOR_DSI); 1777 drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs); 1778 connector->display_info.subpixel_order = SubPixelHorizontalRGB; 1779 connector->interlace_allowed = false; 1780 connector->doublescan_allowed = false; 1781 intel_connector->get_hw_state = intel_connector_get_hw_state; 1782 1783 /* attach connector to encoder */ 1784 intel_connector_attach_encoder(intel_connector, encoder); 1785 1786 mutex_lock(&dev->mode_config.mutex); 1787 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 1788 mutex_unlock(&dev->mode_config.mutex); 1789 1790 if (!fixed_mode) { 1791 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); 1792 goto err; 1793 } 1794 1795 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); 1796 intel_panel_setup_backlight(connector, INVALID_PIPE); 1797 1798 if (dev_priv->vbt.dsi.config->dual_link) 1799 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); 1800 else 1801 intel_dsi->ports = BIT(port); 1802 1803 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; 1804 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; 1805 1806 for_each_dsi_port(port, intel_dsi->ports) { 1807 struct intel_dsi_host *host; 1808 1809 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port); 1810 if (!host) 1811 goto err; 1812 1813 intel_dsi->dsi_hosts[port] = host; 1814 } 1815 1816 if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) { 1817 drm_dbg_kms(&dev_priv->drm, "no device found\n"); 1818 goto err; 1819 } 1820 1821 icl_dphy_param_init(intel_dsi); 1822 1823 icl_dsi_add_properties(intel_connector); 1824 return; 1825 1826 err: 1827 drm_encoder_cleanup(&encoder->base); 1828 kfree(intel_dsi); 1829 kfree(intel_connector); 1830 } 1831