1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Freescale eSDHC controller driver. 4 * 5 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 6 * Copyright (c) 2009 MontaVista Software, Inc. 7 * 8 * Authors: Xiaobo Xie <X.Xie@freescale.com> 9 * Anton Vorontsov <avorontsov@ru.mvista.com> 10 */ 11 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/sys_soc.h> 19 #include <linux/clk.h> 20 #include <linux/ktime.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/mmc/host.h> 23 #include <linux/mmc/mmc.h> 24 #include "sdhci-pltfm.h" 25 #include "sdhci-esdhc.h" 26 27 #define VENDOR_V_22 0x12 28 #define VENDOR_V_23 0x13 29 30 #define MMC_TIMING_NUM (MMC_TIMING_MMC_HS400 + 1) 31 32 struct esdhc_clk_fixup { 33 const unsigned int sd_dflt_max_clk; 34 const unsigned int max_clk[MMC_TIMING_NUM]; 35 }; 36 37 static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { 38 .sd_dflt_max_clk = 25000000, 39 .max_clk[MMC_TIMING_MMC_HS] = 46500000, 40 .max_clk[MMC_TIMING_SD_HS] = 46500000, 41 }; 42 43 static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { 44 .sd_dflt_max_clk = 25000000, 45 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, 46 .max_clk[MMC_TIMING_MMC_HS200] = 167000000, 47 }; 48 49 static const struct esdhc_clk_fixup ls1012a_esdhc_clk = { 50 .sd_dflt_max_clk = 25000000, 51 .max_clk[MMC_TIMING_UHS_SDR104] = 125000000, 52 .max_clk[MMC_TIMING_MMC_HS200] = 125000000, 53 }; 54 55 static const struct esdhc_clk_fixup p1010_esdhc_clk = { 56 .sd_dflt_max_clk = 20000000, 57 .max_clk[MMC_TIMING_LEGACY] = 20000000, 58 .max_clk[MMC_TIMING_MMC_HS] = 42000000, 59 .max_clk[MMC_TIMING_SD_HS] = 40000000, 60 }; 61 62 static const struct of_device_id sdhci_esdhc_of_match[] = { 63 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, 64 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, 65 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, 66 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, 67 { .compatible = "fsl,mpc8379-esdhc" }, 68 { .compatible = "fsl,mpc8536-esdhc" }, 69 { .compatible = "fsl,esdhc" }, 70 { } 71 }; 72 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 73 74 struct sdhci_esdhc { 75 u8 vendor_ver; 76 u8 spec_ver; 77 bool quirk_incorrect_hostver; 78 bool quirk_limited_clk_division; 79 bool quirk_unreliable_pulse_detection; 80 bool quirk_fixup_tuning; 81 bool quirk_ignore_data_inhibit; 82 unsigned int peripheral_clock; 83 const struct esdhc_clk_fixup *clk_fixup; 84 u32 div_ratio; 85 }; 86 87 /** 88 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 89 * to make it compatible with SD spec. 90 * 91 * @host: pointer to sdhci_host 92 * @spec_reg: SD spec register address 93 * @value: 32bit eSDHC register value on spec_reg address 94 * 95 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 96 * registers are 32 bits. There are differences in register size, register 97 * address, register function, bit position and function between eSDHC spec 98 * and SD spec. 99 * 100 * Return a fixed up register value 101 */ 102 static u32 esdhc_readl_fixup(struct sdhci_host *host, 103 int spec_reg, u32 value) 104 { 105 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 106 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 107 u32 ret; 108 109 /* 110 * The bit of ADMA flag in eSDHC is not compatible with standard 111 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 112 * supported by eSDHC. 113 * And for many FSL eSDHC controller, the reset value of field 114 * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 115 * only these vendor version is greater than 2.2/0x12 support ADMA. 116 */ 117 if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 118 if (esdhc->vendor_ver > VENDOR_V_22) { 119 ret = value | SDHCI_CAN_DO_ADMA2; 120 return ret; 121 } 122 } 123 /* 124 * The DAT[3:0] line signal levels and the CMD line signal level are 125 * not compatible with standard SDHC register. The line signal levels 126 * DAT[7:0] are at bits 31:24 and the command line signal level is at 127 * bit 23. All other bits are the same as in the standard SDHC 128 * register. 129 */ 130 if (spec_reg == SDHCI_PRESENT_STATE) { 131 ret = value & 0x000fffff; 132 ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 133 ret |= (value << 1) & SDHCI_CMD_LVL; 134 return ret; 135 } 136 137 /* 138 * DTS properties of mmc host are used to enable each speed mode 139 * according to soc and board capability. So clean up 140 * SDR50/SDR104/DDR50 support bits here. 141 */ 142 if (spec_reg == SDHCI_CAPABILITIES_1) { 143 ret = value & ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 144 SDHCI_SUPPORT_DDR50); 145 return ret; 146 } 147 148 /* 149 * Some controllers have unreliable Data Line Active 150 * bit for commands with busy signal. This affects 151 * Command Inhibit (data) bit. Just ignore it since 152 * MMC core driver has already polled card status 153 * with CMD13 after any command with busy siganl. 154 */ 155 if ((spec_reg == SDHCI_PRESENT_STATE) && 156 (esdhc->quirk_ignore_data_inhibit == true)) { 157 ret = value & ~SDHCI_DATA_INHIBIT; 158 return ret; 159 } 160 161 ret = value; 162 return ret; 163 } 164 165 static u16 esdhc_readw_fixup(struct sdhci_host *host, 166 int spec_reg, u32 value) 167 { 168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 169 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 170 u16 ret; 171 int shift = (spec_reg & 0x2) * 8; 172 173 if (spec_reg == SDHCI_HOST_VERSION) 174 ret = value & 0xffff; 175 else 176 ret = (value >> shift) & 0xffff; 177 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 178 * vendor version and spec version information. 179 */ 180 if ((spec_reg == SDHCI_HOST_VERSION) && 181 (esdhc->quirk_incorrect_hostver)) 182 ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 183 return ret; 184 } 185 186 static u8 esdhc_readb_fixup(struct sdhci_host *host, 187 int spec_reg, u32 value) 188 { 189 u8 ret; 190 u8 dma_bits; 191 int shift = (spec_reg & 0x3) * 8; 192 193 ret = (value >> shift) & 0xff; 194 195 /* 196 * "DMA select" locates at offset 0x28 in SD specification, but on 197 * P5020 or P3041, it locates at 0x29. 198 */ 199 if (spec_reg == SDHCI_HOST_CONTROL) { 200 /* DMA select is 22,23 bits in Protocol Control Register */ 201 dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 202 /* fixup the result */ 203 ret &= ~SDHCI_CTRL_DMA_MASK; 204 ret |= dma_bits; 205 } 206 return ret; 207 } 208 209 /** 210 * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 211 * written into eSDHC register. 212 * 213 * @host: pointer to sdhci_host 214 * @spec_reg: SD spec register address 215 * @value: 8/16/32bit SD spec register value that would be written 216 * @old_value: 32bit eSDHC register value on spec_reg address 217 * 218 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 219 * registers are 32 bits. There are differences in register size, register 220 * address, register function, bit position and function between eSDHC spec 221 * and SD spec. 222 * 223 * Return a fixed up register value 224 */ 225 static u32 esdhc_writel_fixup(struct sdhci_host *host, 226 int spec_reg, u32 value, u32 old_value) 227 { 228 u32 ret; 229 230 /* 231 * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 232 * when SYSCTL[RSTD] is set for some special operations. 233 * No any impact on other operation. 234 */ 235 if (spec_reg == SDHCI_INT_ENABLE) 236 ret = value | SDHCI_INT_BLK_GAP; 237 else 238 ret = value; 239 240 return ret; 241 } 242 243 static u32 esdhc_writew_fixup(struct sdhci_host *host, 244 int spec_reg, u16 value, u32 old_value) 245 { 246 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 247 int shift = (spec_reg & 0x2) * 8; 248 u32 ret; 249 250 switch (spec_reg) { 251 case SDHCI_TRANSFER_MODE: 252 /* 253 * Postpone this write, we must do it together with a 254 * command write that is down below. Return old value. 255 */ 256 pltfm_host->xfer_mode_shadow = value; 257 return old_value; 258 case SDHCI_COMMAND: 259 ret = (value << 16) | pltfm_host->xfer_mode_shadow; 260 return ret; 261 } 262 263 ret = old_value & (~(0xffff << shift)); 264 ret |= (value << shift); 265 266 if (spec_reg == SDHCI_BLOCK_SIZE) { 267 /* 268 * Two last DMA bits are reserved, and first one is used for 269 * non-standard blksz of 4096 bytes that we don't support 270 * yet. So clear the DMA boundary bits. 271 */ 272 ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 273 } 274 return ret; 275 } 276 277 static u32 esdhc_writeb_fixup(struct sdhci_host *host, 278 int spec_reg, u8 value, u32 old_value) 279 { 280 u32 ret; 281 u32 dma_bits; 282 u8 tmp; 283 int shift = (spec_reg & 0x3) * 8; 284 285 /* 286 * eSDHC doesn't have a standard power control register, so we do 287 * nothing here to avoid incorrect operation. 288 */ 289 if (spec_reg == SDHCI_POWER_CONTROL) 290 return old_value; 291 /* 292 * "DMA select" location is offset 0x28 in SD specification, but on 293 * P5020 or P3041, it's located at 0x29. 294 */ 295 if (spec_reg == SDHCI_HOST_CONTROL) { 296 /* 297 * If host control register is not standard, exit 298 * this function 299 */ 300 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 301 return old_value; 302 303 /* DMA select is 22,23 bits in Protocol Control Register */ 304 dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 305 ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 306 tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 307 (old_value & SDHCI_CTRL_DMA_MASK); 308 ret = (ret & (~0xff)) | tmp; 309 310 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 311 ret &= ~ESDHC_HOST_CONTROL_RES; 312 return ret; 313 } 314 315 ret = (old_value & (~(0xff << shift))) | (value << shift); 316 return ret; 317 } 318 319 static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 320 { 321 u32 ret; 322 u32 value; 323 324 if (reg == SDHCI_CAPABILITIES_1) 325 value = ioread32be(host->ioaddr + ESDHC_CAPABILITIES_1); 326 else 327 value = ioread32be(host->ioaddr + reg); 328 329 ret = esdhc_readl_fixup(host, reg, value); 330 331 return ret; 332 } 333 334 static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 335 { 336 u32 ret; 337 u32 value; 338 339 if (reg == SDHCI_CAPABILITIES_1) 340 value = ioread32(host->ioaddr + ESDHC_CAPABILITIES_1); 341 else 342 value = ioread32(host->ioaddr + reg); 343 344 ret = esdhc_readl_fixup(host, reg, value); 345 346 return ret; 347 } 348 349 static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 350 { 351 u16 ret; 352 u32 value; 353 int base = reg & ~0x3; 354 355 value = ioread32be(host->ioaddr + base); 356 ret = esdhc_readw_fixup(host, reg, value); 357 return ret; 358 } 359 360 static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 361 { 362 u16 ret; 363 u32 value; 364 int base = reg & ~0x3; 365 366 value = ioread32(host->ioaddr + base); 367 ret = esdhc_readw_fixup(host, reg, value); 368 return ret; 369 } 370 371 static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 372 { 373 u8 ret; 374 u32 value; 375 int base = reg & ~0x3; 376 377 value = ioread32be(host->ioaddr + base); 378 ret = esdhc_readb_fixup(host, reg, value); 379 return ret; 380 } 381 382 static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 383 { 384 u8 ret; 385 u32 value; 386 int base = reg & ~0x3; 387 388 value = ioread32(host->ioaddr + base); 389 ret = esdhc_readb_fixup(host, reg, value); 390 return ret; 391 } 392 393 static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 394 { 395 u32 value; 396 397 value = esdhc_writel_fixup(host, reg, val, 0); 398 iowrite32be(value, host->ioaddr + reg); 399 } 400 401 static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 402 { 403 u32 value; 404 405 value = esdhc_writel_fixup(host, reg, val, 0); 406 iowrite32(value, host->ioaddr + reg); 407 } 408 409 static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 410 { 411 int base = reg & ~0x3; 412 u32 value; 413 u32 ret; 414 415 value = ioread32be(host->ioaddr + base); 416 ret = esdhc_writew_fixup(host, reg, val, value); 417 if (reg != SDHCI_TRANSFER_MODE) 418 iowrite32be(ret, host->ioaddr + base); 419 } 420 421 static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 422 { 423 int base = reg & ~0x3; 424 u32 value; 425 u32 ret; 426 427 value = ioread32(host->ioaddr + base); 428 ret = esdhc_writew_fixup(host, reg, val, value); 429 if (reg != SDHCI_TRANSFER_MODE) 430 iowrite32(ret, host->ioaddr + base); 431 } 432 433 static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 434 { 435 int base = reg & ~0x3; 436 u32 value; 437 u32 ret; 438 439 value = ioread32be(host->ioaddr + base); 440 ret = esdhc_writeb_fixup(host, reg, val, value); 441 iowrite32be(ret, host->ioaddr + base); 442 } 443 444 static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 445 { 446 int base = reg & ~0x3; 447 u32 value; 448 u32 ret; 449 450 value = ioread32(host->ioaddr + base); 451 ret = esdhc_writeb_fixup(host, reg, val, value); 452 iowrite32(ret, host->ioaddr + base); 453 } 454 455 /* 456 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 457 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 458 * and Block Gap Event(IRQSTAT[BGE]) are also set. 459 * For Continue, apply soft reset for data(SYSCTL[RSTD]); 460 * and re-issue the entire read transaction from beginning. 461 */ 462 static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 463 { 464 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 465 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 466 bool applicable; 467 dma_addr_t dmastart; 468 dma_addr_t dmanow; 469 470 applicable = (intmask & SDHCI_INT_DATA_END) && 471 (intmask & SDHCI_INT_BLK_GAP) && 472 (esdhc->vendor_ver == VENDOR_V_23); 473 if (!applicable) 474 return; 475 476 host->data->error = 0; 477 dmastart = sg_dma_address(host->data->sg); 478 dmanow = dmastart + host->data->bytes_xfered; 479 /* 480 * Force update to the next DMA block boundary. 481 */ 482 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 483 SDHCI_DEFAULT_BOUNDARY_SIZE; 484 host->data->bytes_xfered = dmanow - dmastart; 485 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 486 } 487 488 static int esdhc_of_enable_dma(struct sdhci_host *host) 489 { 490 u32 value; 491 struct device *dev = mmc_dev(host->mmc); 492 493 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || 494 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) 495 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40)); 496 497 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 498 499 if (of_dma_is_coherent(dev->of_node)) 500 value |= ESDHC_DMA_SNOOP; 501 else 502 value &= ~ESDHC_DMA_SNOOP; 503 504 sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 505 return 0; 506 } 507 508 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 509 { 510 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 511 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 512 513 if (esdhc->peripheral_clock) 514 return esdhc->peripheral_clock; 515 else 516 return pltfm_host->clock; 517 } 518 519 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 520 { 521 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 522 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 523 unsigned int clock; 524 525 if (esdhc->peripheral_clock) 526 clock = esdhc->peripheral_clock; 527 else 528 clock = pltfm_host->clock; 529 return clock / 256 / 16; 530 } 531 532 static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 533 { 534 u32 val; 535 ktime_t timeout; 536 537 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 538 539 if (enable) 540 val |= ESDHC_CLOCK_SDCLKEN; 541 else 542 val &= ~ESDHC_CLOCK_SDCLKEN; 543 544 sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 545 546 /* Wait max 20 ms */ 547 timeout = ktime_add_ms(ktime_get(), 20); 548 val = ESDHC_CLOCK_STABLE; 549 while (1) { 550 bool timedout = ktime_after(ktime_get(), timeout); 551 552 if (sdhci_readl(host, ESDHC_PRSSTAT) & val) 553 break; 554 if (timedout) { 555 pr_err("%s: Internal clock never stabilised.\n", 556 mmc_hostname(host->mmc)); 557 break; 558 } 559 udelay(10); 560 } 561 } 562 563 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 564 { 565 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 566 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 567 int pre_div = 1; 568 int div = 1; 569 int division; 570 ktime_t timeout; 571 long fixup = 0; 572 u32 temp; 573 574 host->mmc->actual_clock = 0; 575 576 if (clock == 0) { 577 esdhc_clock_enable(host, false); 578 return; 579 } 580 581 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 582 if (esdhc->vendor_ver < VENDOR_V_23) 583 pre_div = 2; 584 585 if (host->mmc->card && mmc_card_sd(host->mmc->card) && 586 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) 587 fixup = esdhc->clk_fixup->sd_dflt_max_clk; 588 else if (esdhc->clk_fixup) 589 fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; 590 591 if (fixup && clock > fixup) 592 clock = fixup; 593 594 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 595 temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 596 ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 597 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 598 599 while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 600 pre_div *= 2; 601 602 while (host->max_clk / pre_div / div > clock && div < 16) 603 div++; 604 605 if (esdhc->quirk_limited_clk_division && 606 clock == MMC_HS200_MAX_DTR && 607 (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 || 608 host->flags & SDHCI_HS400_TUNING)) { 609 division = pre_div * div; 610 if (division <= 4) { 611 pre_div = 4; 612 div = 1; 613 } else if (division <= 8) { 614 pre_div = 4; 615 div = 2; 616 } else if (division <= 12) { 617 pre_div = 4; 618 div = 3; 619 } else { 620 pr_warn("%s: using unsupported clock division.\n", 621 mmc_hostname(host->mmc)); 622 } 623 } 624 625 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 626 clock, host->max_clk / pre_div / div); 627 host->mmc->actual_clock = host->max_clk / pre_div / div; 628 esdhc->div_ratio = pre_div * div; 629 pre_div >>= 1; 630 div--; 631 632 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 633 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 634 | (div << ESDHC_DIVIDER_SHIFT) 635 | (pre_div << ESDHC_PREDIV_SHIFT)); 636 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 637 638 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && 639 clock == MMC_HS200_MAX_DTR) { 640 temp = sdhci_readl(host, ESDHC_TBCTL); 641 sdhci_writel(host, temp | ESDHC_HS400_MODE, ESDHC_TBCTL); 642 temp = sdhci_readl(host, ESDHC_SDCLKCTL); 643 sdhci_writel(host, temp | ESDHC_CMD_CLK_CTL, ESDHC_SDCLKCTL); 644 esdhc_clock_enable(host, true); 645 646 temp = sdhci_readl(host, ESDHC_DLLCFG0); 647 temp |= ESDHC_DLL_ENABLE; 648 if (host->mmc->actual_clock == MMC_HS200_MAX_DTR) 649 temp |= ESDHC_DLL_FREQ_SEL; 650 sdhci_writel(host, temp, ESDHC_DLLCFG0); 651 temp = sdhci_readl(host, ESDHC_TBCTL); 652 sdhci_writel(host, temp | ESDHC_HS400_WNDW_ADJUST, ESDHC_TBCTL); 653 654 esdhc_clock_enable(host, false); 655 temp = sdhci_readl(host, ESDHC_DMA_SYSCTL); 656 temp |= ESDHC_FLUSH_ASYNC_FIFO; 657 sdhci_writel(host, temp, ESDHC_DMA_SYSCTL); 658 } 659 660 /* Wait max 20 ms */ 661 timeout = ktime_add_ms(ktime_get(), 20); 662 while (1) { 663 bool timedout = ktime_after(ktime_get(), timeout); 664 665 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) 666 break; 667 if (timedout) { 668 pr_err("%s: Internal clock never stabilised.\n", 669 mmc_hostname(host->mmc)); 670 return; 671 } 672 udelay(10); 673 } 674 675 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 676 temp |= ESDHC_CLOCK_SDCLKEN; 677 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 678 } 679 680 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 681 { 682 u32 ctrl; 683 684 ctrl = sdhci_readl(host, ESDHC_PROCTL); 685 ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 686 switch (width) { 687 case MMC_BUS_WIDTH_8: 688 ctrl |= ESDHC_CTRL_8BITBUS; 689 break; 690 691 case MMC_BUS_WIDTH_4: 692 ctrl |= ESDHC_CTRL_4BITBUS; 693 break; 694 695 default: 696 break; 697 } 698 699 sdhci_writel(host, ctrl, ESDHC_PROCTL); 700 } 701 702 static void esdhc_reset(struct sdhci_host *host, u8 mask) 703 { 704 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 705 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 706 u32 val; 707 708 sdhci_reset(host, mask); 709 710 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 711 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 712 713 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) 714 mdelay(5); 715 716 if (mask & SDHCI_RESET_ALL) { 717 val = sdhci_readl(host, ESDHC_TBCTL); 718 val &= ~ESDHC_TB_EN; 719 sdhci_writel(host, val, ESDHC_TBCTL); 720 721 if (esdhc->quirk_unreliable_pulse_detection) { 722 val = sdhci_readl(host, ESDHC_DLLCFG1); 723 val &= ~ESDHC_DLL_PD_PULSE_STRETCH_SEL; 724 sdhci_writel(host, val, ESDHC_DLLCFG1); 725 } 726 } 727 } 728 729 /* The SCFG, Supplemental Configuration Unit, provides SoC specific 730 * configuration and status registers for the device. There is a 731 * SDHC IO VSEL control register on SCFG for some platforms. It's 732 * used to support SDHC IO voltage switching. 733 */ 734 static const struct of_device_id scfg_device_ids[] = { 735 { .compatible = "fsl,t1040-scfg", }, 736 { .compatible = "fsl,ls1012a-scfg", }, 737 { .compatible = "fsl,ls1046a-scfg", }, 738 {} 739 }; 740 741 /* SDHC IO VSEL control register definition */ 742 #define SCFG_SDHCIOVSELCR 0x408 743 #define SDHCIOVSELCR_TGLEN 0x80000000 744 #define SDHCIOVSELCR_VSELVAL 0x60000000 745 #define SDHCIOVSELCR_SDHC_VS 0x00000001 746 747 static int esdhc_signal_voltage_switch(struct mmc_host *mmc, 748 struct mmc_ios *ios) 749 { 750 struct sdhci_host *host = mmc_priv(mmc); 751 struct device_node *scfg_node; 752 void __iomem *scfg_base = NULL; 753 u32 sdhciovselcr; 754 u32 val; 755 756 /* 757 * Signal Voltage Switching is only applicable for Host Controllers 758 * v3.00 and above. 759 */ 760 if (host->version < SDHCI_SPEC_300) 761 return 0; 762 763 val = sdhci_readl(host, ESDHC_PROCTL); 764 765 switch (ios->signal_voltage) { 766 case MMC_SIGNAL_VOLTAGE_330: 767 val &= ~ESDHC_VOLT_SEL; 768 sdhci_writel(host, val, ESDHC_PROCTL); 769 return 0; 770 case MMC_SIGNAL_VOLTAGE_180: 771 scfg_node = of_find_matching_node(NULL, scfg_device_ids); 772 if (scfg_node) 773 scfg_base = of_iomap(scfg_node, 0); 774 if (scfg_base) { 775 sdhciovselcr = SDHCIOVSELCR_TGLEN | 776 SDHCIOVSELCR_VSELVAL; 777 iowrite32be(sdhciovselcr, 778 scfg_base + SCFG_SDHCIOVSELCR); 779 780 val |= ESDHC_VOLT_SEL; 781 sdhci_writel(host, val, ESDHC_PROCTL); 782 mdelay(5); 783 784 sdhciovselcr = SDHCIOVSELCR_TGLEN | 785 SDHCIOVSELCR_SDHC_VS; 786 iowrite32be(sdhciovselcr, 787 scfg_base + SCFG_SDHCIOVSELCR); 788 iounmap(scfg_base); 789 } else { 790 val |= ESDHC_VOLT_SEL; 791 sdhci_writel(host, val, ESDHC_PROCTL); 792 } 793 return 0; 794 default: 795 return 0; 796 } 797 } 798 799 static struct soc_device_attribute soc_fixup_tuning[] = { 800 { .family = "QorIQ T1040", .revision = "1.0", }, 801 { .family = "QorIQ T2080", .revision = "1.0", }, 802 { .family = "QorIQ T1023", .revision = "1.0", }, 803 { .family = "QorIQ LS1021A", .revision = "1.0", }, 804 { .family = "QorIQ LS1080A", .revision = "1.0", }, 805 { .family = "QorIQ LS2080A", .revision = "1.0", }, 806 { .family = "QorIQ LS1012A", .revision = "1.0", }, 807 { .family = "QorIQ LS1043A", .revision = "1.*", }, 808 { .family = "QorIQ LS1046A", .revision = "1.0", }, 809 { }, 810 }; 811 812 static void esdhc_tuning_block_enable(struct sdhci_host *host, bool enable) 813 { 814 u32 val; 815 816 esdhc_clock_enable(host, false); 817 818 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 819 val |= ESDHC_FLUSH_ASYNC_FIFO; 820 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 821 822 val = sdhci_readl(host, ESDHC_TBCTL); 823 if (enable) 824 val |= ESDHC_TB_EN; 825 else 826 val &= ~ESDHC_TB_EN; 827 sdhci_writel(host, val, ESDHC_TBCTL); 828 829 esdhc_clock_enable(host, true); 830 } 831 832 static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 833 { 834 struct sdhci_host *host = mmc_priv(mmc); 835 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 836 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 837 bool hs400_tuning; 838 unsigned int clk; 839 u32 val; 840 int ret; 841 842 /* For tuning mode, the sd clock divisor value 843 * must be larger than 3 according to reference manual. 844 */ 845 clk = esdhc->peripheral_clock / 3; 846 if (host->clock > clk) 847 esdhc_of_set_clock(host, clk); 848 849 if (esdhc->quirk_limited_clk_division && 850 host->flags & SDHCI_HS400_TUNING) 851 esdhc_of_set_clock(host, host->clock); 852 853 esdhc_tuning_block_enable(host, true); 854 855 hs400_tuning = host->flags & SDHCI_HS400_TUNING; 856 ret = sdhci_execute_tuning(mmc, opcode); 857 858 if (hs400_tuning) { 859 val = sdhci_readl(host, ESDHC_SDTIMNGCTL); 860 val |= ESDHC_FLW_CTL_BG; 861 sdhci_writel(host, val, ESDHC_SDTIMNGCTL); 862 } 863 864 if (host->tuning_err == -EAGAIN && esdhc->quirk_fixup_tuning) { 865 866 /* program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and 867 * program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO 868 */ 869 val = sdhci_readl(host, ESDHC_TBPTR); 870 val = (val & ~((0x7f << 8) | 0x7f)) | 871 (3 * esdhc->div_ratio) | ((5 * esdhc->div_ratio) << 8); 872 sdhci_writel(host, val, ESDHC_TBPTR); 873 874 /* program the software tuning mode by setting 875 * TBCTL[TB_MODE]=2'h3 876 */ 877 val = sdhci_readl(host, ESDHC_TBCTL); 878 val |= 0x3; 879 sdhci_writel(host, val, ESDHC_TBCTL); 880 sdhci_execute_tuning(mmc, opcode); 881 } 882 return ret; 883 } 884 885 static void esdhc_set_uhs_signaling(struct sdhci_host *host, 886 unsigned int timing) 887 { 888 if (timing == MMC_TIMING_MMC_HS400) 889 esdhc_tuning_block_enable(host, true); 890 else 891 sdhci_set_uhs_signaling(host, timing); 892 } 893 894 static u32 esdhc_irq(struct sdhci_host *host, u32 intmask) 895 { 896 u32 command; 897 898 if (of_find_compatible_node(NULL, NULL, 899 "fsl,p2020-esdhc")) { 900 command = SDHCI_GET_CMD(sdhci_readw(host, 901 SDHCI_COMMAND)); 902 if (command == MMC_WRITE_MULTIPLE_BLOCK && 903 sdhci_readw(host, SDHCI_BLOCK_COUNT) && 904 intmask & SDHCI_INT_DATA_END) { 905 intmask &= ~SDHCI_INT_DATA_END; 906 sdhci_writel(host, SDHCI_INT_DATA_END, 907 SDHCI_INT_STATUS); 908 } 909 } 910 return intmask; 911 } 912 913 #ifdef CONFIG_PM_SLEEP 914 static u32 esdhc_proctl; 915 static int esdhc_of_suspend(struct device *dev) 916 { 917 struct sdhci_host *host = dev_get_drvdata(dev); 918 919 esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 920 921 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 922 mmc_retune_needed(host->mmc); 923 924 return sdhci_suspend_host(host); 925 } 926 927 static int esdhc_of_resume(struct device *dev) 928 { 929 struct sdhci_host *host = dev_get_drvdata(dev); 930 int ret = sdhci_resume_host(host); 931 932 if (ret == 0) { 933 /* Isn't this already done by sdhci_resume_host() ? --rmk */ 934 esdhc_of_enable_dma(host); 935 sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 936 } 937 return ret; 938 } 939 #endif 940 941 static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 942 esdhc_of_suspend, 943 esdhc_of_resume); 944 945 static const struct sdhci_ops sdhci_esdhc_be_ops = { 946 .read_l = esdhc_be_readl, 947 .read_w = esdhc_be_readw, 948 .read_b = esdhc_be_readb, 949 .write_l = esdhc_be_writel, 950 .write_w = esdhc_be_writew, 951 .write_b = esdhc_be_writeb, 952 .set_clock = esdhc_of_set_clock, 953 .enable_dma = esdhc_of_enable_dma, 954 .get_max_clock = esdhc_of_get_max_clock, 955 .get_min_clock = esdhc_of_get_min_clock, 956 .adma_workaround = esdhc_of_adma_workaround, 957 .set_bus_width = esdhc_pltfm_set_bus_width, 958 .reset = esdhc_reset, 959 .set_uhs_signaling = esdhc_set_uhs_signaling, 960 .irq = esdhc_irq, 961 }; 962 963 static const struct sdhci_ops sdhci_esdhc_le_ops = { 964 .read_l = esdhc_le_readl, 965 .read_w = esdhc_le_readw, 966 .read_b = esdhc_le_readb, 967 .write_l = esdhc_le_writel, 968 .write_w = esdhc_le_writew, 969 .write_b = esdhc_le_writeb, 970 .set_clock = esdhc_of_set_clock, 971 .enable_dma = esdhc_of_enable_dma, 972 .get_max_clock = esdhc_of_get_max_clock, 973 .get_min_clock = esdhc_of_get_min_clock, 974 .adma_workaround = esdhc_of_adma_workaround, 975 .set_bus_width = esdhc_pltfm_set_bus_width, 976 .reset = esdhc_reset, 977 .set_uhs_signaling = esdhc_set_uhs_signaling, 978 .irq = esdhc_irq, 979 }; 980 981 static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 982 .quirks = ESDHC_DEFAULT_QUIRKS | 983 #ifdef CONFIG_PPC 984 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 985 #endif 986 SDHCI_QUIRK_NO_CARD_NO_RESET | 987 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 988 .ops = &sdhci_esdhc_be_ops, 989 }; 990 991 static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 992 .quirks = ESDHC_DEFAULT_QUIRKS | 993 SDHCI_QUIRK_NO_CARD_NO_RESET | 994 SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 995 .ops = &sdhci_esdhc_le_ops, 996 }; 997 998 static struct soc_device_attribute soc_incorrect_hostver[] = { 999 { .family = "QorIQ T4240", .revision = "1.0", }, 1000 { .family = "QorIQ T4240", .revision = "2.0", }, 1001 { }, 1002 }; 1003 1004 static struct soc_device_attribute soc_fixup_sdhc_clkdivs[] = { 1005 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1006 { .family = "QorIQ LX2160A", .revision = "2.0", }, 1007 { .family = "QorIQ LS1028A", .revision = "1.0", }, 1008 { }, 1009 }; 1010 1011 static struct soc_device_attribute soc_unreliable_pulse_detection[] = { 1012 { .family = "QorIQ LX2160A", .revision = "1.0", }, 1013 { }, 1014 }; 1015 1016 static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 1017 { 1018 const struct of_device_id *match; 1019 struct sdhci_pltfm_host *pltfm_host; 1020 struct sdhci_esdhc *esdhc; 1021 struct device_node *np; 1022 struct clk *clk; 1023 u32 val; 1024 u16 host_ver; 1025 1026 pltfm_host = sdhci_priv(host); 1027 esdhc = sdhci_pltfm_priv(pltfm_host); 1028 1029 host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 1030 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 1031 SDHCI_VENDOR_VER_SHIFT; 1032 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 1033 if (soc_device_match(soc_incorrect_hostver)) 1034 esdhc->quirk_incorrect_hostver = true; 1035 else 1036 esdhc->quirk_incorrect_hostver = false; 1037 1038 if (soc_device_match(soc_fixup_sdhc_clkdivs)) 1039 esdhc->quirk_limited_clk_division = true; 1040 else 1041 esdhc->quirk_limited_clk_division = false; 1042 1043 if (soc_device_match(soc_unreliable_pulse_detection)) 1044 esdhc->quirk_unreliable_pulse_detection = true; 1045 else 1046 esdhc->quirk_unreliable_pulse_detection = false; 1047 1048 match = of_match_node(sdhci_esdhc_of_match, pdev->dev.of_node); 1049 if (match) 1050 esdhc->clk_fixup = match->data; 1051 np = pdev->dev.of_node; 1052 clk = of_clk_get(np, 0); 1053 if (!IS_ERR(clk)) { 1054 /* 1055 * esdhc->peripheral_clock would be assigned with a value 1056 * which is eSDHC base clock when use periperal clock. 1057 * For some platforms, the clock value got by common clk 1058 * API is peripheral clock while the eSDHC base clock is 1059 * 1/2 peripheral clock. 1060 */ 1061 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") || 1062 of_device_is_compatible(np, "fsl,ls1028a-esdhc")) 1063 esdhc->peripheral_clock = clk_get_rate(clk) / 2; 1064 else 1065 esdhc->peripheral_clock = clk_get_rate(clk); 1066 1067 clk_put(clk); 1068 } 1069 1070 if (esdhc->peripheral_clock) { 1071 esdhc_clock_enable(host, false); 1072 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 1073 val |= ESDHC_PERIPHERAL_CLK_SEL; 1074 sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 1075 esdhc_clock_enable(host, true); 1076 } 1077 } 1078 1079 static int esdhc_hs400_prepare_ddr(struct mmc_host *mmc) 1080 { 1081 esdhc_tuning_block_enable(mmc_priv(mmc), false); 1082 return 0; 1083 } 1084 1085 static int sdhci_esdhc_probe(struct platform_device *pdev) 1086 { 1087 struct sdhci_host *host; 1088 struct device_node *np; 1089 struct sdhci_pltfm_host *pltfm_host; 1090 struct sdhci_esdhc *esdhc; 1091 int ret; 1092 1093 np = pdev->dev.of_node; 1094 1095 if (of_property_read_bool(np, "little-endian")) 1096 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 1097 sizeof(struct sdhci_esdhc)); 1098 else 1099 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 1100 sizeof(struct sdhci_esdhc)); 1101 1102 if (IS_ERR(host)) 1103 return PTR_ERR(host); 1104 1105 host->mmc_host_ops.start_signal_voltage_switch = 1106 esdhc_signal_voltage_switch; 1107 host->mmc_host_ops.execute_tuning = esdhc_execute_tuning; 1108 host->mmc_host_ops.hs400_prepare_ddr = esdhc_hs400_prepare_ddr; 1109 host->tuning_delay = 1; 1110 1111 esdhc_init(pdev, host); 1112 1113 sdhci_get_of_property(pdev); 1114 1115 pltfm_host = sdhci_priv(host); 1116 esdhc = sdhci_pltfm_priv(pltfm_host); 1117 if (soc_device_match(soc_fixup_tuning)) 1118 esdhc->quirk_fixup_tuning = true; 1119 else 1120 esdhc->quirk_fixup_tuning = false; 1121 1122 if (esdhc->vendor_ver == VENDOR_V_22) 1123 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 1124 1125 if (esdhc->vendor_ver > VENDOR_V_22) 1126 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1127 1128 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) { 1129 host->quirks2 |= SDHCI_QUIRK_RESET_AFTER_REQUEST; 1130 host->quirks2 |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1131 } 1132 1133 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 1134 of_device_is_compatible(np, "fsl,p5020-esdhc") || 1135 of_device_is_compatible(np, "fsl,p4080-esdhc") || 1136 of_device_is_compatible(np, "fsl,p1020-esdhc") || 1137 of_device_is_compatible(np, "fsl,t1040-esdhc")) 1138 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1139 1140 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 1141 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 1142 1143 esdhc->quirk_ignore_data_inhibit = false; 1144 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 1145 /* 1146 * Freescale messed up with P2020 as it has a non-standard 1147 * host control register 1148 */ 1149 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 1150 esdhc->quirk_ignore_data_inhibit = true; 1151 } 1152 1153 /* call to generic mmc_of_parse to support additional capabilities */ 1154 ret = mmc_of_parse(host->mmc); 1155 if (ret) 1156 goto err; 1157 1158 mmc_of_parse_voltage(np, &host->ocr_mask); 1159 1160 ret = sdhci_add_host(host); 1161 if (ret) 1162 goto err; 1163 1164 return 0; 1165 err: 1166 sdhci_pltfm_free(pdev); 1167 return ret; 1168 } 1169 1170 static struct platform_driver sdhci_esdhc_driver = { 1171 .driver = { 1172 .name = "sdhci-esdhc", 1173 .of_match_table = sdhci_esdhc_of_match, 1174 .pm = &esdhc_of_dev_pm_ops, 1175 }, 1176 .probe = sdhci_esdhc_probe, 1177 .remove = sdhci_pltfm_unregister, 1178 }; 1179 1180 module_platform_driver(sdhci_esdhc_driver); 1181 1182 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 1183 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 1184 "Anton Vorontsov <avorontsov@ru.mvista.com>"); 1185 MODULE_LICENSE("GPL v2"); 1186