1 /* 2 * Linux driver for VMware's vmxnet3 ethernet NIC. 3 * 4 * Copyright (C) 2008-2016, VMware, Inc. All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; version 2 of the License and no later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 13 * NON INFRINGEMENT. See the GNU General Public License for more 14 * details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 * 23 * Maintained by: pv-drivers@vmware.com 24 * 25 */ 26 27 #include <linux/module.h> 28 #include <net/ip6_checksum.h> 29 30 #include "vmxnet3_int.h" 31 32 char vmxnet3_driver_name[] = "vmxnet3"; 33 #define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver" 34 35 /* 36 * PCI Device ID Table 37 * Last entry must be all 0s 38 */ 39 static const struct pci_device_id vmxnet3_pciid_table[] = { 40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)}, 41 {0} 42 }; 43 44 MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table); 45 46 static int enable_mq = 1; 47 48 static void 49 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac); 50 51 /* 52 * Enable/Disable the given intr 53 */ 54 static void 55 vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 56 { 57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0); 58 } 59 60 61 static void 62 vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx) 63 { 64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1); 65 } 66 67 68 /* 69 * Enable/Disable all intrs used by the device 70 */ 71 static void 72 vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter) 73 { 74 int i; 75 76 for (i = 0; i < adapter->intr.num_intrs; i++) 77 vmxnet3_enable_intr(adapter, i); 78 adapter->shared->devRead.intrConf.intrCtrl &= 79 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL); 80 } 81 82 83 static void 84 vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter) 85 { 86 int i; 87 88 adapter->shared->devRead.intrConf.intrCtrl |= 89 cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 90 for (i = 0; i < adapter->intr.num_intrs; i++) 91 vmxnet3_disable_intr(adapter, i); 92 } 93 94 95 static void 96 vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events) 97 { 98 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events); 99 } 100 101 102 static bool 103 vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 104 { 105 return tq->stopped; 106 } 107 108 109 static void 110 vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 111 { 112 tq->stopped = false; 113 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue); 114 } 115 116 117 static void 118 vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 119 { 120 tq->stopped = false; 121 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 122 } 123 124 125 static void 126 vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter) 127 { 128 tq->stopped = true; 129 tq->num_stop++; 130 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue)); 131 } 132 133 134 /* 135 * Check the link state. This may start or stop the tx queue. 136 */ 137 static void 138 vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue) 139 { 140 u32 ret; 141 int i; 142 unsigned long flags; 143 144 spin_lock_irqsave(&adapter->cmd_lock, flags); 145 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK); 146 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 147 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 148 149 adapter->link_speed = ret >> 16; 150 if (ret & 1) { /* Link is up. */ 151 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n", 152 adapter->link_speed); 153 netif_carrier_on(adapter->netdev); 154 155 if (affectTxQueue) { 156 for (i = 0; i < adapter->num_tx_queues; i++) 157 vmxnet3_tq_start(&adapter->tx_queue[i], 158 adapter); 159 } 160 } else { 161 netdev_info(adapter->netdev, "NIC Link is Down\n"); 162 netif_carrier_off(adapter->netdev); 163 164 if (affectTxQueue) { 165 for (i = 0; i < adapter->num_tx_queues; i++) 166 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter); 167 } 168 } 169 } 170 171 static void 172 vmxnet3_process_events(struct vmxnet3_adapter *adapter) 173 { 174 int i; 175 unsigned long flags; 176 u32 events = le32_to_cpu(adapter->shared->ecr); 177 if (!events) 178 return; 179 180 vmxnet3_ack_events(adapter, events); 181 182 /* Check if link state has changed */ 183 if (events & VMXNET3_ECR_LINK) 184 vmxnet3_check_link(adapter, true); 185 186 /* Check if there is an error on xmit/recv queues */ 187 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) { 188 spin_lock_irqsave(&adapter->cmd_lock, flags); 189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 190 VMXNET3_CMD_GET_QUEUE_STATUS); 191 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 192 193 for (i = 0; i < adapter->num_tx_queues; i++) 194 if (adapter->tqd_start[i].status.stopped) 195 dev_err(&adapter->netdev->dev, 196 "%s: tq[%d] error 0x%x\n", 197 adapter->netdev->name, i, le32_to_cpu( 198 adapter->tqd_start[i].status.error)); 199 for (i = 0; i < adapter->num_rx_queues; i++) 200 if (adapter->rqd_start[i].status.stopped) 201 dev_err(&adapter->netdev->dev, 202 "%s: rq[%d] error 0x%x\n", 203 adapter->netdev->name, i, 204 adapter->rqd_start[i].status.error); 205 206 schedule_work(&adapter->work); 207 } 208 } 209 210 #ifdef __BIG_ENDIAN_BITFIELD 211 /* 212 * The device expects the bitfields in shared structures to be written in 213 * little endian. When CPU is big endian, the following routines are used to 214 * correctly read and write into ABI. 215 * The general technique used here is : double word bitfields are defined in 216 * opposite order for big endian architecture. Then before reading them in 217 * driver the complete double word is translated using le32_to_cpu. Similarly 218 * After the driver writes into bitfields, cpu_to_le32 is used to translate the 219 * double words into required format. 220 * In order to avoid touching bits in shared structure more than once, temporary 221 * descriptors are used. These are passed as srcDesc to following functions. 222 */ 223 static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc, 224 struct Vmxnet3_RxDesc *dstDesc) 225 { 226 u32 *src = (u32 *)srcDesc + 2; 227 u32 *dst = (u32 *)dstDesc + 2; 228 dstDesc->addr = le64_to_cpu(srcDesc->addr); 229 *dst = le32_to_cpu(*src); 230 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1); 231 } 232 233 static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc, 234 struct Vmxnet3_TxDesc *dstDesc) 235 { 236 int i; 237 u32 *src = (u32 *)(srcDesc + 1); 238 u32 *dst = (u32 *)(dstDesc + 1); 239 240 /* Working backwards so that the gen bit is set at the end. */ 241 for (i = 2; i > 0; i--) { 242 src--; 243 dst--; 244 *dst = cpu_to_le32(*src); 245 } 246 } 247 248 249 static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc, 250 struct Vmxnet3_RxCompDesc *dstDesc) 251 { 252 int i = 0; 253 u32 *src = (u32 *)srcDesc; 254 u32 *dst = (u32 *)dstDesc; 255 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) { 256 *dst = le32_to_cpu(*src); 257 src++; 258 dst++; 259 } 260 } 261 262 263 /* Used to read bitfield values from double words. */ 264 static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size) 265 { 266 u32 temp = le32_to_cpu(*bitfield); 267 u32 mask = ((1 << size) - 1) << pos; 268 temp &= mask; 269 temp >>= pos; 270 return temp; 271 } 272 273 274 275 #endif /* __BIG_ENDIAN_BITFIELD */ 276 277 #ifdef __BIG_ENDIAN_BITFIELD 278 279 # define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \ 280 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \ 281 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE) 282 # define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \ 283 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \ 284 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE) 285 # define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \ 286 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \ 287 VMXNET3_TCD_GEN_SIZE) 288 # define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \ 289 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE) 290 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \ 291 (dstrcd) = (tmp); \ 292 vmxnet3_RxCompToCPU((rcd), (tmp)); \ 293 } while (0) 294 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \ 295 (dstrxd) = (tmp); \ 296 vmxnet3_RxDescToCPU((rxd), (tmp)); \ 297 } while (0) 298 299 #else 300 301 # define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen) 302 # define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop) 303 # define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen) 304 # define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx) 305 # define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd) 306 # define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd) 307 308 #endif /* __BIG_ENDIAN_BITFIELD */ 309 310 311 static void 312 vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi, 313 struct pci_dev *pdev) 314 { 315 if (tbi->map_type == VMXNET3_MAP_SINGLE) 316 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len, 317 PCI_DMA_TODEVICE); 318 else if (tbi->map_type == VMXNET3_MAP_PAGE) 319 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len, 320 PCI_DMA_TODEVICE); 321 else 322 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE); 323 324 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */ 325 } 326 327 328 static int 329 vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq, 330 struct pci_dev *pdev, struct vmxnet3_adapter *adapter) 331 { 332 struct sk_buff *skb; 333 int entries = 0; 334 335 /* no out of order completion */ 336 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp); 337 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1); 338 339 skb = tq->buf_info[eop_idx].skb; 340 BUG_ON(skb == NULL); 341 tq->buf_info[eop_idx].skb = NULL; 342 343 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size); 344 345 while (tq->tx_ring.next2comp != eop_idx) { 346 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp, 347 pdev); 348 349 /* update next2comp w/o tx_lock. Since we are marking more, 350 * instead of less, tx ring entries avail, the worst case is 351 * that the tx routine incorrectly re-queues a pkt due to 352 * insufficient tx ring entries. 353 */ 354 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 355 entries++; 356 } 357 358 dev_kfree_skb_any(skb); 359 return entries; 360 } 361 362 363 static int 364 vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq, 365 struct vmxnet3_adapter *adapter) 366 { 367 int completed = 0; 368 union Vmxnet3_GenericDesc *gdesc; 369 370 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 371 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) { 372 /* Prevent any &gdesc->tcd field from being (speculatively) 373 * read before (&gdesc->tcd)->gen is read. 374 */ 375 dma_rmb(); 376 377 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX( 378 &gdesc->tcd), tq, adapter->pdev, 379 adapter); 380 381 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring); 382 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc; 383 } 384 385 if (completed) { 386 spin_lock(&tq->tx_lock); 387 if (unlikely(vmxnet3_tq_stopped(tq, adapter) && 388 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) > 389 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) && 390 netif_carrier_ok(adapter->netdev))) { 391 vmxnet3_tq_wake(tq, adapter); 392 } 393 spin_unlock(&tq->tx_lock); 394 } 395 return completed; 396 } 397 398 399 static void 400 vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq, 401 struct vmxnet3_adapter *adapter) 402 { 403 int i; 404 405 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) { 406 struct vmxnet3_tx_buf_info *tbi; 407 408 tbi = tq->buf_info + tq->tx_ring.next2comp; 409 410 vmxnet3_unmap_tx_buf(tbi, adapter->pdev); 411 if (tbi->skb) { 412 dev_kfree_skb_any(tbi->skb); 413 tbi->skb = NULL; 414 } 415 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring); 416 } 417 418 /* sanity check, verify all buffers are indeed unmapped and freed */ 419 for (i = 0; i < tq->tx_ring.size; i++) { 420 BUG_ON(tq->buf_info[i].skb != NULL || 421 tq->buf_info[i].map_type != VMXNET3_MAP_NONE); 422 } 423 424 tq->tx_ring.gen = VMXNET3_INIT_GEN; 425 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 426 427 tq->comp_ring.gen = VMXNET3_INIT_GEN; 428 tq->comp_ring.next2proc = 0; 429 } 430 431 432 static void 433 vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq, 434 struct vmxnet3_adapter *adapter) 435 { 436 if (tq->tx_ring.base) { 437 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size * 438 sizeof(struct Vmxnet3_TxDesc), 439 tq->tx_ring.base, tq->tx_ring.basePA); 440 tq->tx_ring.base = NULL; 441 } 442 if (tq->data_ring.base) { 443 dma_free_coherent(&adapter->pdev->dev, 444 tq->data_ring.size * tq->txdata_desc_size, 445 tq->data_ring.base, tq->data_ring.basePA); 446 tq->data_ring.base = NULL; 447 } 448 if (tq->comp_ring.base) { 449 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size * 450 sizeof(struct Vmxnet3_TxCompDesc), 451 tq->comp_ring.base, tq->comp_ring.basePA); 452 tq->comp_ring.base = NULL; 453 } 454 if (tq->buf_info) { 455 dma_free_coherent(&adapter->pdev->dev, 456 tq->tx_ring.size * sizeof(tq->buf_info[0]), 457 tq->buf_info, tq->buf_info_pa); 458 tq->buf_info = NULL; 459 } 460 } 461 462 463 /* Destroy all tx queues */ 464 void 465 vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter) 466 { 467 int i; 468 469 for (i = 0; i < adapter->num_tx_queues; i++) 470 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter); 471 } 472 473 474 static void 475 vmxnet3_tq_init(struct vmxnet3_tx_queue *tq, 476 struct vmxnet3_adapter *adapter) 477 { 478 int i; 479 480 /* reset the tx ring contents to 0 and reset the tx ring states */ 481 memset(tq->tx_ring.base, 0, tq->tx_ring.size * 482 sizeof(struct Vmxnet3_TxDesc)); 483 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0; 484 tq->tx_ring.gen = VMXNET3_INIT_GEN; 485 486 memset(tq->data_ring.base, 0, 487 tq->data_ring.size * tq->txdata_desc_size); 488 489 /* reset the tx comp ring contents to 0 and reset comp ring states */ 490 memset(tq->comp_ring.base, 0, tq->comp_ring.size * 491 sizeof(struct Vmxnet3_TxCompDesc)); 492 tq->comp_ring.next2proc = 0; 493 tq->comp_ring.gen = VMXNET3_INIT_GEN; 494 495 /* reset the bookkeeping data */ 496 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size); 497 for (i = 0; i < tq->tx_ring.size; i++) 498 tq->buf_info[i].map_type = VMXNET3_MAP_NONE; 499 500 /* stats are not reset */ 501 } 502 503 504 static int 505 vmxnet3_tq_create(struct vmxnet3_tx_queue *tq, 506 struct vmxnet3_adapter *adapter) 507 { 508 size_t sz; 509 510 BUG_ON(tq->tx_ring.base || tq->data_ring.base || 511 tq->comp_ring.base || tq->buf_info); 512 513 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 514 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc), 515 &tq->tx_ring.basePA, GFP_KERNEL); 516 if (!tq->tx_ring.base) { 517 netdev_err(adapter->netdev, "failed to allocate tx ring\n"); 518 goto err; 519 } 520 521 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 522 tq->data_ring.size * tq->txdata_desc_size, 523 &tq->data_ring.basePA, GFP_KERNEL); 524 if (!tq->data_ring.base) { 525 netdev_err(adapter->netdev, "failed to allocate tx data ring\n"); 526 goto err; 527 } 528 529 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, 530 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc), 531 &tq->comp_ring.basePA, GFP_KERNEL); 532 if (!tq->comp_ring.base) { 533 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n"); 534 goto err; 535 } 536 537 sz = tq->tx_ring.size * sizeof(tq->buf_info[0]); 538 tq->buf_info = dma_alloc_coherent(&adapter->pdev->dev, sz, 539 &tq->buf_info_pa, GFP_KERNEL); 540 if (!tq->buf_info) 541 goto err; 542 543 return 0; 544 545 err: 546 vmxnet3_tq_destroy(tq, adapter); 547 return -ENOMEM; 548 } 549 550 static void 551 vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter) 552 { 553 int i; 554 555 for (i = 0; i < adapter->num_tx_queues; i++) 556 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter); 557 } 558 559 /* 560 * starting from ring->next2fill, allocate rx buffers for the given ring 561 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers 562 * are allocated or allocation fails 563 */ 564 565 static int 566 vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx, 567 int num_to_alloc, struct vmxnet3_adapter *adapter) 568 { 569 int num_allocated = 0; 570 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx]; 571 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx]; 572 u32 val; 573 574 while (num_allocated <= num_to_alloc) { 575 struct vmxnet3_rx_buf_info *rbi; 576 union Vmxnet3_GenericDesc *gd; 577 578 rbi = rbi_base + ring->next2fill; 579 gd = ring->base + ring->next2fill; 580 581 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) { 582 if (rbi->skb == NULL) { 583 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev, 584 rbi->len, 585 GFP_KERNEL); 586 if (unlikely(rbi->skb == NULL)) { 587 rq->stats.rx_buf_alloc_failure++; 588 break; 589 } 590 591 rbi->dma_addr = dma_map_single( 592 &adapter->pdev->dev, 593 rbi->skb->data, rbi->len, 594 PCI_DMA_FROMDEVICE); 595 if (dma_mapping_error(&adapter->pdev->dev, 596 rbi->dma_addr)) { 597 dev_kfree_skb_any(rbi->skb); 598 rq->stats.rx_buf_alloc_failure++; 599 break; 600 } 601 } else { 602 /* rx buffer skipped by the device */ 603 } 604 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT; 605 } else { 606 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE || 607 rbi->len != PAGE_SIZE); 608 609 if (rbi->page == NULL) { 610 rbi->page = alloc_page(GFP_ATOMIC); 611 if (unlikely(rbi->page == NULL)) { 612 rq->stats.rx_buf_alloc_failure++; 613 break; 614 } 615 rbi->dma_addr = dma_map_page( 616 &adapter->pdev->dev, 617 rbi->page, 0, PAGE_SIZE, 618 PCI_DMA_FROMDEVICE); 619 if (dma_mapping_error(&adapter->pdev->dev, 620 rbi->dma_addr)) { 621 put_page(rbi->page); 622 rq->stats.rx_buf_alloc_failure++; 623 break; 624 } 625 } else { 626 /* rx buffers skipped by the device */ 627 } 628 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT; 629 } 630 631 gd->rxd.addr = cpu_to_le64(rbi->dma_addr); 632 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT) 633 | val | rbi->len); 634 635 /* Fill the last buffer but dont mark it ready, or else the 636 * device will think that the queue is full */ 637 if (num_allocated == num_to_alloc) 638 break; 639 640 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT); 641 num_allocated++; 642 vmxnet3_cmd_ring_adv_next2fill(ring); 643 } 644 645 netdev_dbg(adapter->netdev, 646 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n", 647 num_allocated, ring->next2fill, ring->next2comp); 648 649 /* so that the device can distinguish a full ring and an empty ring */ 650 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp); 651 652 return num_allocated; 653 } 654 655 656 static void 657 vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd, 658 struct vmxnet3_rx_buf_info *rbi) 659 { 660 skb_frag_t *frag = skb_shinfo(skb)->frags + skb_shinfo(skb)->nr_frags; 661 662 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS); 663 664 __skb_frag_set_page(frag, rbi->page); 665 skb_frag_off_set(frag, 0); 666 skb_frag_size_set(frag, rcd->len); 667 skb->data_len += rcd->len; 668 skb->truesize += PAGE_SIZE; 669 skb_shinfo(skb)->nr_frags++; 670 } 671 672 673 static int 674 vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx, 675 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev, 676 struct vmxnet3_adapter *adapter) 677 { 678 u32 dw2, len; 679 unsigned long buf_offset; 680 int i; 681 union Vmxnet3_GenericDesc *gdesc; 682 struct vmxnet3_tx_buf_info *tbi = NULL; 683 684 BUG_ON(ctx->copy_size > skb_headlen(skb)); 685 686 /* use the previous gen bit for the SOP desc */ 687 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT; 688 689 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill; 690 gdesc = ctx->sop_txd; /* both loops below can be skipped */ 691 692 /* no need to map the buffer if headers are copied */ 693 if (ctx->copy_size) { 694 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA + 695 tq->tx_ring.next2fill * 696 tq->txdata_desc_size); 697 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size); 698 ctx->sop_txd->dword[3] = 0; 699 700 tbi = tq->buf_info + tq->tx_ring.next2fill; 701 tbi->map_type = VMXNET3_MAP_NONE; 702 703 netdev_dbg(adapter->netdev, 704 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 705 tq->tx_ring.next2fill, 706 le64_to_cpu(ctx->sop_txd->txd.addr), 707 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]); 708 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 709 710 /* use the right gen for non-SOP desc */ 711 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 712 } 713 714 /* linear part can use multiple tx desc if it's big */ 715 len = skb_headlen(skb) - ctx->copy_size; 716 buf_offset = ctx->copy_size; 717 while (len) { 718 u32 buf_size; 719 720 if (len < VMXNET3_MAX_TX_BUF_SIZE) { 721 buf_size = len; 722 dw2 |= len; 723 } else { 724 buf_size = VMXNET3_MAX_TX_BUF_SIZE; 725 /* spec says that for TxDesc.len, 0 == 2^14 */ 726 } 727 728 tbi = tq->buf_info + tq->tx_ring.next2fill; 729 tbi->map_type = VMXNET3_MAP_SINGLE; 730 tbi->dma_addr = dma_map_single(&adapter->pdev->dev, 731 skb->data + buf_offset, buf_size, 732 PCI_DMA_TODEVICE); 733 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr)) 734 return -EFAULT; 735 736 tbi->len = buf_size; 737 738 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 739 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 740 741 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 742 gdesc->dword[2] = cpu_to_le32(dw2); 743 gdesc->dword[3] = 0; 744 745 netdev_dbg(adapter->netdev, 746 "txd[%u]: 0x%Lx 0x%x 0x%x\n", 747 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 748 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 749 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 750 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 751 752 len -= buf_size; 753 buf_offset += buf_size; 754 } 755 756 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 757 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 758 u32 buf_size; 759 760 buf_offset = 0; 761 len = skb_frag_size(frag); 762 while (len) { 763 tbi = tq->buf_info + tq->tx_ring.next2fill; 764 if (len < VMXNET3_MAX_TX_BUF_SIZE) { 765 buf_size = len; 766 dw2 |= len; 767 } else { 768 buf_size = VMXNET3_MAX_TX_BUF_SIZE; 769 /* spec says that for TxDesc.len, 0 == 2^14 */ 770 } 771 tbi->map_type = VMXNET3_MAP_PAGE; 772 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag, 773 buf_offset, buf_size, 774 DMA_TO_DEVICE); 775 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr)) 776 return -EFAULT; 777 778 tbi->len = buf_size; 779 780 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill; 781 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen); 782 783 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr); 784 gdesc->dword[2] = cpu_to_le32(dw2); 785 gdesc->dword[3] = 0; 786 787 netdev_dbg(adapter->netdev, 788 "txd[%u]: 0x%llx %u %u\n", 789 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr), 790 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]); 791 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring); 792 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT; 793 794 len -= buf_size; 795 buf_offset += buf_size; 796 } 797 } 798 799 ctx->eop_txd = gdesc; 800 801 /* set the last buf_info for the pkt */ 802 tbi->skb = skb; 803 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base; 804 805 return 0; 806 } 807 808 809 /* Init all tx queues */ 810 static void 811 vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter) 812 { 813 int i; 814 815 for (i = 0; i < adapter->num_tx_queues; i++) 816 vmxnet3_tq_init(&adapter->tx_queue[i], adapter); 817 } 818 819 820 /* 821 * parse relevant protocol headers: 822 * For a tso pkt, relevant headers are L2/3/4 including options 823 * For a pkt requesting csum offloading, they are L2/3 and may include L4 824 * if it's a TCP/UDP pkt 825 * 826 * Returns: 827 * -1: error happens during parsing 828 * 0: protocol headers parsed, but too big to be copied 829 * 1: protocol headers parsed and copied 830 * 831 * Other effects: 832 * 1. related *ctx fields are updated. 833 * 2. ctx->copy_size is # of bytes copied 834 * 3. the portion to be copied is guaranteed to be in the linear part 835 * 836 */ 837 static int 838 vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 839 struct vmxnet3_tx_ctx *ctx, 840 struct vmxnet3_adapter *adapter) 841 { 842 u8 protocol = 0; 843 844 if (ctx->mss) { /* TSO */ 845 ctx->eth_ip_hdr_size = skb_transport_offset(skb); 846 ctx->l4_hdr_size = tcp_hdrlen(skb); 847 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size; 848 } else { 849 if (skb->ip_summed == CHECKSUM_PARTIAL) { 850 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb); 851 852 if (ctx->ipv4) { 853 const struct iphdr *iph = ip_hdr(skb); 854 855 protocol = iph->protocol; 856 } else if (ctx->ipv6) { 857 const struct ipv6hdr *ipv6h = ipv6_hdr(skb); 858 859 protocol = ipv6h->nexthdr; 860 } 861 862 switch (protocol) { 863 case IPPROTO_TCP: 864 ctx->l4_hdr_size = tcp_hdrlen(skb); 865 break; 866 case IPPROTO_UDP: 867 ctx->l4_hdr_size = sizeof(struct udphdr); 868 break; 869 default: 870 ctx->l4_hdr_size = 0; 871 break; 872 } 873 874 ctx->copy_size = min(ctx->eth_ip_hdr_size + 875 ctx->l4_hdr_size, skb->len); 876 } else { 877 ctx->eth_ip_hdr_size = 0; 878 ctx->l4_hdr_size = 0; 879 /* copy as much as allowed */ 880 ctx->copy_size = min_t(unsigned int, 881 tq->txdata_desc_size, 882 skb_headlen(skb)); 883 } 884 885 if (skb->len <= VMXNET3_HDR_COPY_SIZE) 886 ctx->copy_size = skb->len; 887 888 /* make sure headers are accessible directly */ 889 if (unlikely(!pskb_may_pull(skb, ctx->copy_size))) 890 goto err; 891 } 892 893 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) { 894 tq->stats.oversized_hdr++; 895 ctx->copy_size = 0; 896 return 0; 897 } 898 899 return 1; 900 err: 901 return -1; 902 } 903 904 /* 905 * copy relevant protocol headers to the transmit ring: 906 * For a tso pkt, relevant headers are L2/3/4 including options 907 * For a pkt requesting csum offloading, they are L2/3 and may include L4 908 * if it's a TCP/UDP pkt 909 * 910 * 911 * Note that this requires that vmxnet3_parse_hdr be called first to set the 912 * appropriate bits in ctx first 913 */ 914 static void 915 vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 916 struct vmxnet3_tx_ctx *ctx, 917 struct vmxnet3_adapter *adapter) 918 { 919 struct Vmxnet3_TxDataDesc *tdd; 920 921 tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base + 922 tq->tx_ring.next2fill * 923 tq->txdata_desc_size); 924 925 memcpy(tdd->data, skb->data, ctx->copy_size); 926 netdev_dbg(adapter->netdev, 927 "copy %u bytes to dataRing[%u]\n", 928 ctx->copy_size, tq->tx_ring.next2fill); 929 } 930 931 932 static void 933 vmxnet3_prepare_tso(struct sk_buff *skb, 934 struct vmxnet3_tx_ctx *ctx) 935 { 936 struct tcphdr *tcph = tcp_hdr(skb); 937 938 if (ctx->ipv4) { 939 struct iphdr *iph = ip_hdr(skb); 940 941 iph->check = 0; 942 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0, 943 IPPROTO_TCP, 0); 944 } else if (ctx->ipv6) { 945 tcp_v6_gso_csum_prep(skb); 946 } 947 } 948 949 static int txd_estimate(const struct sk_buff *skb) 950 { 951 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 952 int i; 953 954 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 955 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 956 957 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag)); 958 } 959 return count; 960 } 961 962 /* 963 * Transmits a pkt thru a given tq 964 * Returns: 965 * NETDEV_TX_OK: descriptors are setup successfully 966 * NETDEV_TX_OK: error occurred, the pkt is dropped 967 * NETDEV_TX_BUSY: tx ring is full, queue is stopped 968 * 969 * Side-effects: 970 * 1. tx ring may be changed 971 * 2. tq stats may be updated accordingly 972 * 3. shared->txNumDeferred may be updated 973 */ 974 975 static int 976 vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq, 977 struct vmxnet3_adapter *adapter, struct net_device *netdev) 978 { 979 int ret; 980 u32 count; 981 int num_pkts; 982 int tx_num_deferred; 983 unsigned long flags; 984 struct vmxnet3_tx_ctx ctx; 985 union Vmxnet3_GenericDesc *gdesc; 986 #ifdef __BIG_ENDIAN_BITFIELD 987 /* Use temporary descriptor to avoid touching bits multiple times */ 988 union Vmxnet3_GenericDesc tempTxDesc; 989 #endif 990 991 count = txd_estimate(skb); 992 993 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP)); 994 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6)); 995 996 ctx.mss = skb_shinfo(skb)->gso_size; 997 if (ctx.mss) { 998 if (skb_header_cloned(skb)) { 999 if (unlikely(pskb_expand_head(skb, 0, 0, 1000 GFP_ATOMIC) != 0)) { 1001 tq->stats.drop_tso++; 1002 goto drop_pkt; 1003 } 1004 tq->stats.copy_skb_header++; 1005 } 1006 vmxnet3_prepare_tso(skb, &ctx); 1007 } else { 1008 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) { 1009 1010 /* non-tso pkts must not use more than 1011 * VMXNET3_MAX_TXD_PER_PKT entries 1012 */ 1013 if (skb_linearize(skb) != 0) { 1014 tq->stats.drop_too_many_frags++; 1015 goto drop_pkt; 1016 } 1017 tq->stats.linearized++; 1018 1019 /* recalculate the # of descriptors to use */ 1020 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1; 1021 } 1022 } 1023 1024 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter); 1025 if (ret >= 0) { 1026 BUG_ON(ret <= 0 && ctx.copy_size != 0); 1027 /* hdrs parsed, check against other limits */ 1028 if (ctx.mss) { 1029 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size > 1030 VMXNET3_MAX_TX_BUF_SIZE)) { 1031 tq->stats.drop_oversized_hdr++; 1032 goto drop_pkt; 1033 } 1034 } else { 1035 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1036 if (unlikely(ctx.eth_ip_hdr_size + 1037 skb->csum_offset > 1038 VMXNET3_MAX_CSUM_OFFSET)) { 1039 tq->stats.drop_oversized_hdr++; 1040 goto drop_pkt; 1041 } 1042 } 1043 } 1044 } else { 1045 tq->stats.drop_hdr_inspect_err++; 1046 goto drop_pkt; 1047 } 1048 1049 spin_lock_irqsave(&tq->tx_lock, flags); 1050 1051 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) { 1052 tq->stats.tx_ring_full++; 1053 netdev_dbg(adapter->netdev, 1054 "tx queue stopped on %s, next2comp %u" 1055 " next2fill %u\n", adapter->netdev->name, 1056 tq->tx_ring.next2comp, tq->tx_ring.next2fill); 1057 1058 vmxnet3_tq_stop(tq, adapter); 1059 spin_unlock_irqrestore(&tq->tx_lock, flags); 1060 return NETDEV_TX_BUSY; 1061 } 1062 1063 1064 vmxnet3_copy_hdr(skb, tq, &ctx, adapter); 1065 1066 /* fill tx descs related to addr & len */ 1067 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter)) 1068 goto unlock_drop_pkt; 1069 1070 /* setup the EOP desc */ 1071 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP); 1072 1073 /* setup the SOP desc */ 1074 #ifdef __BIG_ENDIAN_BITFIELD 1075 gdesc = &tempTxDesc; 1076 gdesc->dword[2] = ctx.sop_txd->dword[2]; 1077 gdesc->dword[3] = ctx.sop_txd->dword[3]; 1078 #else 1079 gdesc = ctx.sop_txd; 1080 #endif 1081 tx_num_deferred = le32_to_cpu(tq->shared->txNumDeferred); 1082 if (ctx.mss) { 1083 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size; 1084 gdesc->txd.om = VMXNET3_OM_TSO; 1085 gdesc->txd.msscof = ctx.mss; 1086 num_pkts = (skb->len - gdesc->txd.hlen + ctx.mss - 1) / ctx.mss; 1087 } else { 1088 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1089 gdesc->txd.hlen = ctx.eth_ip_hdr_size; 1090 gdesc->txd.om = VMXNET3_OM_CSUM; 1091 gdesc->txd.msscof = ctx.eth_ip_hdr_size + 1092 skb->csum_offset; 1093 } else { 1094 gdesc->txd.om = 0; 1095 gdesc->txd.msscof = 0; 1096 } 1097 num_pkts = 1; 1098 } 1099 le32_add_cpu(&tq->shared->txNumDeferred, num_pkts); 1100 tx_num_deferred += num_pkts; 1101 1102 if (skb_vlan_tag_present(skb)) { 1103 gdesc->txd.ti = 1; 1104 gdesc->txd.tci = skb_vlan_tag_get(skb); 1105 } 1106 1107 /* Ensure that the write to (&gdesc->txd)->gen will be observed after 1108 * all other writes to &gdesc->txd. 1109 */ 1110 dma_wmb(); 1111 1112 /* finally flips the GEN bit of the SOP desc. */ 1113 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^ 1114 VMXNET3_TXD_GEN); 1115 #ifdef __BIG_ENDIAN_BITFIELD 1116 /* Finished updating in bitfields of Tx Desc, so write them in original 1117 * place. 1118 */ 1119 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc, 1120 (struct Vmxnet3_TxDesc *)ctx.sop_txd); 1121 gdesc = ctx.sop_txd; 1122 #endif 1123 netdev_dbg(adapter->netdev, 1124 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n", 1125 (u32)(ctx.sop_txd - 1126 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr), 1127 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3])); 1128 1129 spin_unlock_irqrestore(&tq->tx_lock, flags); 1130 1131 if (tx_num_deferred >= le32_to_cpu(tq->shared->txThreshold)) { 1132 tq->shared->txNumDeferred = 0; 1133 VMXNET3_WRITE_BAR0_REG(adapter, 1134 VMXNET3_REG_TXPROD + tq->qid * 8, 1135 tq->tx_ring.next2fill); 1136 } 1137 1138 return NETDEV_TX_OK; 1139 1140 unlock_drop_pkt: 1141 spin_unlock_irqrestore(&tq->tx_lock, flags); 1142 drop_pkt: 1143 tq->stats.drop_total++; 1144 dev_kfree_skb_any(skb); 1145 return NETDEV_TX_OK; 1146 } 1147 1148 1149 static netdev_tx_t 1150 vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 1151 { 1152 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 1153 1154 BUG_ON(skb->queue_mapping > adapter->num_tx_queues); 1155 return vmxnet3_tq_xmit(skb, 1156 &adapter->tx_queue[skb->queue_mapping], 1157 adapter, netdev); 1158 } 1159 1160 1161 static void 1162 vmxnet3_rx_csum(struct vmxnet3_adapter *adapter, 1163 struct sk_buff *skb, 1164 union Vmxnet3_GenericDesc *gdesc) 1165 { 1166 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) { 1167 if (gdesc->rcd.v4 && 1168 (le32_to_cpu(gdesc->dword[3]) & 1169 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) { 1170 skb->ip_summed = CHECKSUM_UNNECESSARY; 1171 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp)); 1172 BUG_ON(gdesc->rcd.frg); 1173 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) & 1174 (1 << VMXNET3_RCD_TUC_SHIFT))) { 1175 skb->ip_summed = CHECKSUM_UNNECESSARY; 1176 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp)); 1177 BUG_ON(gdesc->rcd.frg); 1178 } else { 1179 if (gdesc->rcd.csum) { 1180 skb->csum = htons(gdesc->rcd.csum); 1181 skb->ip_summed = CHECKSUM_PARTIAL; 1182 } else { 1183 skb_checksum_none_assert(skb); 1184 } 1185 } 1186 } else { 1187 skb_checksum_none_assert(skb); 1188 } 1189 } 1190 1191 1192 static void 1193 vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd, 1194 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter) 1195 { 1196 rq->stats.drop_err++; 1197 if (!rcd->fcs) 1198 rq->stats.drop_fcs++; 1199 1200 rq->stats.drop_total++; 1201 1202 /* 1203 * We do not unmap and chain the rx buffer to the skb. 1204 * We basically pretend this buffer is not used and will be recycled 1205 * by vmxnet3_rq_alloc_rx_buf() 1206 */ 1207 1208 /* 1209 * ctx->skb may be NULL if this is the first and the only one 1210 * desc for the pkt 1211 */ 1212 if (ctx->skb) 1213 dev_kfree_skb_irq(ctx->skb); 1214 1215 ctx->skb = NULL; 1216 } 1217 1218 1219 static u32 1220 vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb, 1221 union Vmxnet3_GenericDesc *gdesc) 1222 { 1223 u32 hlen, maplen; 1224 union { 1225 void *ptr; 1226 struct ethhdr *eth; 1227 struct vlan_ethhdr *veth; 1228 struct iphdr *ipv4; 1229 struct ipv6hdr *ipv6; 1230 struct tcphdr *tcp; 1231 } hdr; 1232 BUG_ON(gdesc->rcd.tcp == 0); 1233 1234 maplen = skb_headlen(skb); 1235 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen)) 1236 return 0; 1237 1238 if (skb->protocol == cpu_to_be16(ETH_P_8021Q) || 1239 skb->protocol == cpu_to_be16(ETH_P_8021AD)) 1240 hlen = sizeof(struct vlan_ethhdr); 1241 else 1242 hlen = sizeof(struct ethhdr); 1243 1244 hdr.eth = eth_hdr(skb); 1245 if (gdesc->rcd.v4) { 1246 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP) && 1247 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IP)); 1248 hdr.ptr += hlen; 1249 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP); 1250 hlen = hdr.ipv4->ihl << 2; 1251 hdr.ptr += hdr.ipv4->ihl << 2; 1252 } else if (gdesc->rcd.v6) { 1253 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6) && 1254 hdr.veth->h_vlan_encapsulated_proto != htons(ETH_P_IPV6)); 1255 hdr.ptr += hlen; 1256 /* Use an estimated value, since we also need to handle 1257 * TSO case. 1258 */ 1259 if (hdr.ipv6->nexthdr != IPPROTO_TCP) 1260 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr); 1261 hlen = sizeof(struct ipv6hdr); 1262 hdr.ptr += sizeof(struct ipv6hdr); 1263 } else { 1264 /* Non-IP pkt, dont estimate header length */ 1265 return 0; 1266 } 1267 1268 if (hlen + sizeof(struct tcphdr) > maplen) 1269 return 0; 1270 1271 return (hlen + (hdr.tcp->doff << 2)); 1272 } 1273 1274 static int 1275 vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq, 1276 struct vmxnet3_adapter *adapter, int quota) 1277 { 1278 static const u32 rxprod_reg[2] = { 1279 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2 1280 }; 1281 u32 num_pkts = 0; 1282 bool skip_page_frags = false; 1283 struct Vmxnet3_RxCompDesc *rcd; 1284 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx; 1285 u16 segCnt = 0, mss = 0; 1286 #ifdef __BIG_ENDIAN_BITFIELD 1287 struct Vmxnet3_RxDesc rxCmdDesc; 1288 struct Vmxnet3_RxCompDesc rxComp; 1289 #endif 1290 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, 1291 &rxComp); 1292 while (rcd->gen == rq->comp_ring.gen) { 1293 struct vmxnet3_rx_buf_info *rbi; 1294 struct sk_buff *skb, *new_skb = NULL; 1295 struct page *new_page = NULL; 1296 dma_addr_t new_dma_addr; 1297 int num_to_alloc; 1298 struct Vmxnet3_RxDesc *rxd; 1299 u32 idx, ring_idx; 1300 struct vmxnet3_cmd_ring *ring = NULL; 1301 if (num_pkts >= quota) { 1302 /* we may stop even before we see the EOP desc of 1303 * the current pkt 1304 */ 1305 break; 1306 } 1307 1308 /* Prevent any rcd field from being (speculatively) read before 1309 * rcd->gen is read. 1310 */ 1311 dma_rmb(); 1312 1313 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 && 1314 rcd->rqID != rq->dataRingQid); 1315 idx = rcd->rxdIdx; 1316 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID); 1317 ring = rq->rx_ring + ring_idx; 1318 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd, 1319 &rxCmdDesc); 1320 rbi = rq->buf_info[ring_idx] + idx; 1321 1322 BUG_ON(rxd->addr != rbi->dma_addr || 1323 rxd->len != rbi->len); 1324 1325 if (unlikely(rcd->eop && rcd->err)) { 1326 vmxnet3_rx_error(rq, rcd, ctx, adapter); 1327 goto rcd_done; 1328 } 1329 1330 if (rcd->sop) { /* first buf of the pkt */ 1331 bool rxDataRingUsed; 1332 u16 len; 1333 1334 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD || 1335 (rcd->rqID != rq->qid && 1336 rcd->rqID != rq->dataRingQid)); 1337 1338 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB); 1339 BUG_ON(ctx->skb != NULL || rbi->skb == NULL); 1340 1341 if (unlikely(rcd->len == 0)) { 1342 /* Pretend the rx buffer is skipped. */ 1343 BUG_ON(!(rcd->sop && rcd->eop)); 1344 netdev_dbg(adapter->netdev, 1345 "rxRing[%u][%u] 0 length\n", 1346 ring_idx, idx); 1347 goto rcd_done; 1348 } 1349 1350 skip_page_frags = false; 1351 ctx->skb = rbi->skb; 1352 1353 rxDataRingUsed = 1354 VMXNET3_RX_DATA_RING(adapter, rcd->rqID); 1355 len = rxDataRingUsed ? rcd->len : rbi->len; 1356 new_skb = netdev_alloc_skb_ip_align(adapter->netdev, 1357 len); 1358 if (new_skb == NULL) { 1359 /* Skb allocation failed, do not handover this 1360 * skb to stack. Reuse it. Drop the existing pkt 1361 */ 1362 rq->stats.rx_buf_alloc_failure++; 1363 ctx->skb = NULL; 1364 rq->stats.drop_total++; 1365 skip_page_frags = true; 1366 goto rcd_done; 1367 } 1368 1369 if (rxDataRingUsed) { 1370 size_t sz; 1371 1372 BUG_ON(rcd->len > rq->data_ring.desc_size); 1373 1374 ctx->skb = new_skb; 1375 sz = rcd->rxdIdx * rq->data_ring.desc_size; 1376 memcpy(new_skb->data, 1377 &rq->data_ring.base[sz], rcd->len); 1378 } else { 1379 ctx->skb = rbi->skb; 1380 1381 new_dma_addr = 1382 dma_map_single(&adapter->pdev->dev, 1383 new_skb->data, rbi->len, 1384 PCI_DMA_FROMDEVICE); 1385 if (dma_mapping_error(&adapter->pdev->dev, 1386 new_dma_addr)) { 1387 dev_kfree_skb(new_skb); 1388 /* Skb allocation failed, do not 1389 * handover this skb to stack. Reuse 1390 * it. Drop the existing pkt. 1391 */ 1392 rq->stats.rx_buf_alloc_failure++; 1393 ctx->skb = NULL; 1394 rq->stats.drop_total++; 1395 skip_page_frags = true; 1396 goto rcd_done; 1397 } 1398 1399 dma_unmap_single(&adapter->pdev->dev, 1400 rbi->dma_addr, 1401 rbi->len, 1402 PCI_DMA_FROMDEVICE); 1403 1404 /* Immediate refill */ 1405 rbi->skb = new_skb; 1406 rbi->dma_addr = new_dma_addr; 1407 rxd->addr = cpu_to_le64(rbi->dma_addr); 1408 rxd->len = rbi->len; 1409 } 1410 1411 #ifdef VMXNET3_RSS 1412 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE && 1413 (adapter->netdev->features & NETIF_F_RXHASH)) 1414 skb_set_hash(ctx->skb, 1415 le32_to_cpu(rcd->rssHash), 1416 PKT_HASH_TYPE_L3); 1417 #endif 1418 skb_put(ctx->skb, rcd->len); 1419 1420 if (VMXNET3_VERSION_GE_2(adapter) && 1421 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) { 1422 struct Vmxnet3_RxCompDescExt *rcdlro; 1423 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd; 1424 1425 segCnt = rcdlro->segCnt; 1426 WARN_ON_ONCE(segCnt == 0); 1427 mss = rcdlro->mss; 1428 if (unlikely(segCnt <= 1)) 1429 segCnt = 0; 1430 } else { 1431 segCnt = 0; 1432 } 1433 } else { 1434 BUG_ON(ctx->skb == NULL && !skip_page_frags); 1435 1436 /* non SOP buffer must be type 1 in most cases */ 1437 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE); 1438 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY); 1439 1440 /* If an sop buffer was dropped, skip all 1441 * following non-sop fragments. They will be reused. 1442 */ 1443 if (skip_page_frags) 1444 goto rcd_done; 1445 1446 if (rcd->len) { 1447 new_page = alloc_page(GFP_ATOMIC); 1448 /* Replacement page frag could not be allocated. 1449 * Reuse this page. Drop the pkt and free the 1450 * skb which contained this page as a frag. Skip 1451 * processing all the following non-sop frags. 1452 */ 1453 if (unlikely(!new_page)) { 1454 rq->stats.rx_buf_alloc_failure++; 1455 dev_kfree_skb(ctx->skb); 1456 ctx->skb = NULL; 1457 skip_page_frags = true; 1458 goto rcd_done; 1459 } 1460 new_dma_addr = dma_map_page(&adapter->pdev->dev, 1461 new_page, 1462 0, PAGE_SIZE, 1463 PCI_DMA_FROMDEVICE); 1464 if (dma_mapping_error(&adapter->pdev->dev, 1465 new_dma_addr)) { 1466 put_page(new_page); 1467 rq->stats.rx_buf_alloc_failure++; 1468 dev_kfree_skb(ctx->skb); 1469 ctx->skb = NULL; 1470 skip_page_frags = true; 1471 goto rcd_done; 1472 } 1473 1474 dma_unmap_page(&adapter->pdev->dev, 1475 rbi->dma_addr, rbi->len, 1476 PCI_DMA_FROMDEVICE); 1477 1478 vmxnet3_append_frag(ctx->skb, rcd, rbi); 1479 1480 /* Immediate refill */ 1481 rbi->page = new_page; 1482 rbi->dma_addr = new_dma_addr; 1483 rxd->addr = cpu_to_le64(rbi->dma_addr); 1484 rxd->len = rbi->len; 1485 } 1486 } 1487 1488 1489 skb = ctx->skb; 1490 if (rcd->eop) { 1491 u32 mtu = adapter->netdev->mtu; 1492 skb->len += skb->data_len; 1493 1494 vmxnet3_rx_csum(adapter, skb, 1495 (union Vmxnet3_GenericDesc *)rcd); 1496 skb->protocol = eth_type_trans(skb, adapter->netdev); 1497 if (!rcd->tcp || 1498 !(adapter->netdev->features & NETIF_F_LRO)) 1499 goto not_lro; 1500 1501 if (segCnt != 0 && mss != 0) { 1502 skb_shinfo(skb)->gso_type = rcd->v4 ? 1503 SKB_GSO_TCPV4 : SKB_GSO_TCPV6; 1504 skb_shinfo(skb)->gso_size = mss; 1505 skb_shinfo(skb)->gso_segs = segCnt; 1506 } else if (segCnt != 0 || skb->len > mtu) { 1507 u32 hlen; 1508 1509 hlen = vmxnet3_get_hdr_len(adapter, skb, 1510 (union Vmxnet3_GenericDesc *)rcd); 1511 if (hlen == 0) 1512 goto not_lro; 1513 1514 skb_shinfo(skb)->gso_type = 1515 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6; 1516 if (segCnt != 0) { 1517 skb_shinfo(skb)->gso_segs = segCnt; 1518 skb_shinfo(skb)->gso_size = 1519 DIV_ROUND_UP(skb->len - 1520 hlen, segCnt); 1521 } else { 1522 skb_shinfo(skb)->gso_size = mtu - hlen; 1523 } 1524 } 1525 not_lro: 1526 if (unlikely(rcd->ts)) 1527 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci); 1528 1529 if (adapter->netdev->features & NETIF_F_LRO) 1530 netif_receive_skb(skb); 1531 else 1532 napi_gro_receive(&rq->napi, skb); 1533 1534 ctx->skb = NULL; 1535 num_pkts++; 1536 } 1537 1538 rcd_done: 1539 /* device may have skipped some rx descs */ 1540 ring->next2comp = idx; 1541 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring); 1542 ring = rq->rx_ring + ring_idx; 1543 1544 /* Ensure that the writes to rxd->gen bits will be observed 1545 * after all other writes to rxd objects. 1546 */ 1547 dma_wmb(); 1548 1549 while (num_to_alloc) { 1550 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd, 1551 &rxCmdDesc); 1552 BUG_ON(!rxd->addr); 1553 1554 /* Recv desc is ready to be used by the device */ 1555 rxd->gen = ring->gen; 1556 vmxnet3_cmd_ring_adv_next2fill(ring); 1557 num_to_alloc--; 1558 } 1559 1560 /* if needed, update the register */ 1561 if (unlikely(rq->shared->updateRxProd)) { 1562 VMXNET3_WRITE_BAR0_REG(adapter, 1563 rxprod_reg[ring_idx] + rq->qid * 8, 1564 ring->next2fill); 1565 } 1566 1567 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring); 1568 vmxnet3_getRxComp(rcd, 1569 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp); 1570 } 1571 1572 return num_pkts; 1573 } 1574 1575 1576 static void 1577 vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq, 1578 struct vmxnet3_adapter *adapter) 1579 { 1580 u32 i, ring_idx; 1581 struct Vmxnet3_RxDesc *rxd; 1582 1583 for (ring_idx = 0; ring_idx < 2; ring_idx++) { 1584 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) { 1585 #ifdef __BIG_ENDIAN_BITFIELD 1586 struct Vmxnet3_RxDesc rxDesc; 1587 #endif 1588 vmxnet3_getRxDesc(rxd, 1589 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc); 1590 1591 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD && 1592 rq->buf_info[ring_idx][i].skb) { 1593 dma_unmap_single(&adapter->pdev->dev, rxd->addr, 1594 rxd->len, PCI_DMA_FROMDEVICE); 1595 dev_kfree_skb(rq->buf_info[ring_idx][i].skb); 1596 rq->buf_info[ring_idx][i].skb = NULL; 1597 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY && 1598 rq->buf_info[ring_idx][i].page) { 1599 dma_unmap_page(&adapter->pdev->dev, rxd->addr, 1600 rxd->len, PCI_DMA_FROMDEVICE); 1601 put_page(rq->buf_info[ring_idx][i].page); 1602 rq->buf_info[ring_idx][i].page = NULL; 1603 } 1604 } 1605 1606 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN; 1607 rq->rx_ring[ring_idx].next2fill = 1608 rq->rx_ring[ring_idx].next2comp = 0; 1609 } 1610 1611 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1612 rq->comp_ring.next2proc = 0; 1613 } 1614 1615 1616 static void 1617 vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter) 1618 { 1619 int i; 1620 1621 for (i = 0; i < adapter->num_rx_queues; i++) 1622 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter); 1623 } 1624 1625 1626 static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq, 1627 struct vmxnet3_adapter *adapter) 1628 { 1629 int i; 1630 int j; 1631 1632 /* all rx buffers must have already been freed */ 1633 for (i = 0; i < 2; i++) { 1634 if (rq->buf_info[i]) { 1635 for (j = 0; j < rq->rx_ring[i].size; j++) 1636 BUG_ON(rq->buf_info[i][j].page != NULL); 1637 } 1638 } 1639 1640 1641 for (i = 0; i < 2; i++) { 1642 if (rq->rx_ring[i].base) { 1643 dma_free_coherent(&adapter->pdev->dev, 1644 rq->rx_ring[i].size 1645 * sizeof(struct Vmxnet3_RxDesc), 1646 rq->rx_ring[i].base, 1647 rq->rx_ring[i].basePA); 1648 rq->rx_ring[i].base = NULL; 1649 } 1650 } 1651 1652 if (rq->data_ring.base) { 1653 dma_free_coherent(&adapter->pdev->dev, 1654 rq->rx_ring[0].size * rq->data_ring.desc_size, 1655 rq->data_ring.base, rq->data_ring.basePA); 1656 rq->data_ring.base = NULL; 1657 } 1658 1659 if (rq->comp_ring.base) { 1660 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size 1661 * sizeof(struct Vmxnet3_RxCompDesc), 1662 rq->comp_ring.base, rq->comp_ring.basePA); 1663 rq->comp_ring.base = NULL; 1664 } 1665 1666 if (rq->buf_info[0]) { 1667 size_t sz = sizeof(struct vmxnet3_rx_buf_info) * 1668 (rq->rx_ring[0].size + rq->rx_ring[1].size); 1669 dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0], 1670 rq->buf_info_pa); 1671 rq->buf_info[0] = rq->buf_info[1] = NULL; 1672 } 1673 } 1674 1675 static void 1676 vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter) 1677 { 1678 int i; 1679 1680 for (i = 0; i < adapter->num_rx_queues; i++) { 1681 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 1682 1683 if (rq->data_ring.base) { 1684 dma_free_coherent(&adapter->pdev->dev, 1685 (rq->rx_ring[0].size * 1686 rq->data_ring.desc_size), 1687 rq->data_ring.base, 1688 rq->data_ring.basePA); 1689 rq->data_ring.base = NULL; 1690 rq->data_ring.desc_size = 0; 1691 } 1692 } 1693 } 1694 1695 static int 1696 vmxnet3_rq_init(struct vmxnet3_rx_queue *rq, 1697 struct vmxnet3_adapter *adapter) 1698 { 1699 int i; 1700 1701 /* initialize buf_info */ 1702 for (i = 0; i < rq->rx_ring[0].size; i++) { 1703 1704 /* 1st buf for a pkt is skbuff */ 1705 if (i % adapter->rx_buf_per_pkt == 0) { 1706 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB; 1707 rq->buf_info[0][i].len = adapter->skb_buf_size; 1708 } else { /* subsequent bufs for a pkt is frag */ 1709 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE; 1710 rq->buf_info[0][i].len = PAGE_SIZE; 1711 } 1712 } 1713 for (i = 0; i < rq->rx_ring[1].size; i++) { 1714 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE; 1715 rq->buf_info[1][i].len = PAGE_SIZE; 1716 } 1717 1718 /* reset internal state and allocate buffers for both rings */ 1719 for (i = 0; i < 2; i++) { 1720 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0; 1721 1722 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size * 1723 sizeof(struct Vmxnet3_RxDesc)); 1724 rq->rx_ring[i].gen = VMXNET3_INIT_GEN; 1725 } 1726 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1, 1727 adapter) == 0) { 1728 /* at least has 1 rx buffer for the 1st ring */ 1729 return -ENOMEM; 1730 } 1731 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter); 1732 1733 /* reset the comp ring */ 1734 rq->comp_ring.next2proc = 0; 1735 memset(rq->comp_ring.base, 0, rq->comp_ring.size * 1736 sizeof(struct Vmxnet3_RxCompDesc)); 1737 rq->comp_ring.gen = VMXNET3_INIT_GEN; 1738 1739 /* reset rxctx */ 1740 rq->rx_ctx.skb = NULL; 1741 1742 /* stats are not reset */ 1743 return 0; 1744 } 1745 1746 1747 static int 1748 vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter) 1749 { 1750 int i, err = 0; 1751 1752 for (i = 0; i < adapter->num_rx_queues; i++) { 1753 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter); 1754 if (unlikely(err)) { 1755 dev_err(&adapter->netdev->dev, "%s: failed to " 1756 "initialize rx queue%i\n", 1757 adapter->netdev->name, i); 1758 break; 1759 } 1760 } 1761 return err; 1762 1763 } 1764 1765 1766 static int 1767 vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter) 1768 { 1769 int i; 1770 size_t sz; 1771 struct vmxnet3_rx_buf_info *bi; 1772 1773 for (i = 0; i < 2; i++) { 1774 1775 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc); 1776 rq->rx_ring[i].base = dma_alloc_coherent( 1777 &adapter->pdev->dev, sz, 1778 &rq->rx_ring[i].basePA, 1779 GFP_KERNEL); 1780 if (!rq->rx_ring[i].base) { 1781 netdev_err(adapter->netdev, 1782 "failed to allocate rx ring %d\n", i); 1783 goto err; 1784 } 1785 } 1786 1787 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) { 1788 sz = rq->rx_ring[0].size * rq->data_ring.desc_size; 1789 rq->data_ring.base = 1790 dma_alloc_coherent(&adapter->pdev->dev, sz, 1791 &rq->data_ring.basePA, 1792 GFP_KERNEL); 1793 if (!rq->data_ring.base) { 1794 netdev_err(adapter->netdev, 1795 "rx data ring will be disabled\n"); 1796 adapter->rxdataring_enabled = false; 1797 } 1798 } else { 1799 rq->data_ring.base = NULL; 1800 rq->data_ring.desc_size = 0; 1801 } 1802 1803 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc); 1804 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz, 1805 &rq->comp_ring.basePA, 1806 GFP_KERNEL); 1807 if (!rq->comp_ring.base) { 1808 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n"); 1809 goto err; 1810 } 1811 1812 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size + 1813 rq->rx_ring[1].size); 1814 bi = dma_alloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa, 1815 GFP_KERNEL); 1816 if (!bi) 1817 goto err; 1818 1819 rq->buf_info[0] = bi; 1820 rq->buf_info[1] = bi + rq->rx_ring[0].size; 1821 1822 return 0; 1823 1824 err: 1825 vmxnet3_rq_destroy(rq, adapter); 1826 return -ENOMEM; 1827 } 1828 1829 1830 static int 1831 vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter) 1832 { 1833 int i, err = 0; 1834 1835 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter); 1836 1837 for (i = 0; i < adapter->num_rx_queues; i++) { 1838 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter); 1839 if (unlikely(err)) { 1840 dev_err(&adapter->netdev->dev, 1841 "%s: failed to create rx queue%i\n", 1842 adapter->netdev->name, i); 1843 goto err_out; 1844 } 1845 } 1846 1847 if (!adapter->rxdataring_enabled) 1848 vmxnet3_rq_destroy_all_rxdataring(adapter); 1849 1850 return err; 1851 err_out: 1852 vmxnet3_rq_destroy_all(adapter); 1853 return err; 1854 1855 } 1856 1857 /* Multiple queue aware polling function for tx and rx */ 1858 1859 static int 1860 vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget) 1861 { 1862 int rcd_done = 0, i; 1863 if (unlikely(adapter->shared->ecr)) 1864 vmxnet3_process_events(adapter); 1865 for (i = 0; i < adapter->num_tx_queues; i++) 1866 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter); 1867 1868 for (i = 0; i < adapter->num_rx_queues; i++) 1869 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i], 1870 adapter, budget); 1871 return rcd_done; 1872 } 1873 1874 1875 static int 1876 vmxnet3_poll(struct napi_struct *napi, int budget) 1877 { 1878 struct vmxnet3_rx_queue *rx_queue = container_of(napi, 1879 struct vmxnet3_rx_queue, napi); 1880 int rxd_done; 1881 1882 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget); 1883 1884 if (rxd_done < budget) { 1885 napi_complete_done(napi, rxd_done); 1886 vmxnet3_enable_all_intrs(rx_queue->adapter); 1887 } 1888 return rxd_done; 1889 } 1890 1891 /* 1892 * NAPI polling function for MSI-X mode with multiple Rx queues 1893 * Returns the # of the NAPI credit consumed (# of rx descriptors processed) 1894 */ 1895 1896 static int 1897 vmxnet3_poll_rx_only(struct napi_struct *napi, int budget) 1898 { 1899 struct vmxnet3_rx_queue *rq = container_of(napi, 1900 struct vmxnet3_rx_queue, napi); 1901 struct vmxnet3_adapter *adapter = rq->adapter; 1902 int rxd_done; 1903 1904 /* When sharing interrupt with corresponding tx queue, process 1905 * tx completions in that queue as well 1906 */ 1907 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) { 1908 struct vmxnet3_tx_queue *tq = 1909 &adapter->tx_queue[rq - adapter->rx_queue]; 1910 vmxnet3_tq_tx_complete(tq, adapter); 1911 } 1912 1913 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget); 1914 1915 if (rxd_done < budget) { 1916 napi_complete_done(napi, rxd_done); 1917 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx); 1918 } 1919 return rxd_done; 1920 } 1921 1922 1923 #ifdef CONFIG_PCI_MSI 1924 1925 /* 1926 * Handle completion interrupts on tx queues 1927 * Returns whether or not the intr is handled 1928 */ 1929 1930 static irqreturn_t 1931 vmxnet3_msix_tx(int irq, void *data) 1932 { 1933 struct vmxnet3_tx_queue *tq = data; 1934 struct vmxnet3_adapter *adapter = tq->adapter; 1935 1936 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1937 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx); 1938 1939 /* Handle the case where only one irq is allocate for all tx queues */ 1940 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 1941 int i; 1942 for (i = 0; i < adapter->num_tx_queues; i++) { 1943 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i]; 1944 vmxnet3_tq_tx_complete(txq, adapter); 1945 } 1946 } else { 1947 vmxnet3_tq_tx_complete(tq, adapter); 1948 } 1949 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx); 1950 1951 return IRQ_HANDLED; 1952 } 1953 1954 1955 /* 1956 * Handle completion interrupts on rx queues. Returns whether or not the 1957 * intr is handled 1958 */ 1959 1960 static irqreturn_t 1961 vmxnet3_msix_rx(int irq, void *data) 1962 { 1963 struct vmxnet3_rx_queue *rq = data; 1964 struct vmxnet3_adapter *adapter = rq->adapter; 1965 1966 /* disable intr if needed */ 1967 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1968 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx); 1969 napi_schedule(&rq->napi); 1970 1971 return IRQ_HANDLED; 1972 } 1973 1974 /* 1975 *---------------------------------------------------------------------------- 1976 * 1977 * vmxnet3_msix_event -- 1978 * 1979 * vmxnet3 msix event intr handler 1980 * 1981 * Result: 1982 * whether or not the intr is handled 1983 * 1984 *---------------------------------------------------------------------------- 1985 */ 1986 1987 static irqreturn_t 1988 vmxnet3_msix_event(int irq, void *data) 1989 { 1990 struct net_device *dev = data; 1991 struct vmxnet3_adapter *adapter = netdev_priv(dev); 1992 1993 /* disable intr if needed */ 1994 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 1995 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx); 1996 1997 if (adapter->shared->ecr) 1998 vmxnet3_process_events(adapter); 1999 2000 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx); 2001 2002 return IRQ_HANDLED; 2003 } 2004 2005 #endif /* CONFIG_PCI_MSI */ 2006 2007 2008 /* Interrupt handler for vmxnet3 */ 2009 static irqreturn_t 2010 vmxnet3_intr(int irq, void *dev_id) 2011 { 2012 struct net_device *dev = dev_id; 2013 struct vmxnet3_adapter *adapter = netdev_priv(dev); 2014 2015 if (adapter->intr.type == VMXNET3_IT_INTX) { 2016 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR); 2017 if (unlikely(icr == 0)) 2018 /* not ours */ 2019 return IRQ_NONE; 2020 } 2021 2022 2023 /* disable intr if needed */ 2024 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE) 2025 vmxnet3_disable_all_intrs(adapter); 2026 2027 napi_schedule(&adapter->rx_queue[0].napi); 2028 2029 return IRQ_HANDLED; 2030 } 2031 2032 #ifdef CONFIG_NET_POLL_CONTROLLER 2033 2034 /* netpoll callback. */ 2035 static void 2036 vmxnet3_netpoll(struct net_device *netdev) 2037 { 2038 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2039 2040 switch (adapter->intr.type) { 2041 #ifdef CONFIG_PCI_MSI 2042 case VMXNET3_IT_MSIX: { 2043 int i; 2044 for (i = 0; i < adapter->num_rx_queues; i++) 2045 vmxnet3_msix_rx(0, &adapter->rx_queue[i]); 2046 break; 2047 } 2048 #endif 2049 case VMXNET3_IT_MSI: 2050 default: 2051 vmxnet3_intr(0, adapter->netdev); 2052 break; 2053 } 2054 2055 } 2056 #endif /* CONFIG_NET_POLL_CONTROLLER */ 2057 2058 static int 2059 vmxnet3_request_irqs(struct vmxnet3_adapter *adapter) 2060 { 2061 struct vmxnet3_intr *intr = &adapter->intr; 2062 int err = 0, i; 2063 int vector = 0; 2064 2065 #ifdef CONFIG_PCI_MSI 2066 if (adapter->intr.type == VMXNET3_IT_MSIX) { 2067 for (i = 0; i < adapter->num_tx_queues; i++) { 2068 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 2069 sprintf(adapter->tx_queue[i].name, "%s-tx-%d", 2070 adapter->netdev->name, vector); 2071 err = request_irq( 2072 intr->msix_entries[vector].vector, 2073 vmxnet3_msix_tx, 0, 2074 adapter->tx_queue[i].name, 2075 &adapter->tx_queue[i]); 2076 } else { 2077 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d", 2078 adapter->netdev->name, vector); 2079 } 2080 if (err) { 2081 dev_err(&adapter->netdev->dev, 2082 "Failed to request irq for MSIX, %s, " 2083 "error %d\n", 2084 adapter->tx_queue[i].name, err); 2085 return err; 2086 } 2087 2088 /* Handle the case where only 1 MSIx was allocated for 2089 * all tx queues */ 2090 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) { 2091 for (; i < adapter->num_tx_queues; i++) 2092 adapter->tx_queue[i].comp_ring.intr_idx 2093 = vector; 2094 vector++; 2095 break; 2096 } else { 2097 adapter->tx_queue[i].comp_ring.intr_idx 2098 = vector++; 2099 } 2100 } 2101 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) 2102 vector = 0; 2103 2104 for (i = 0; i < adapter->num_rx_queues; i++) { 2105 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) 2106 sprintf(adapter->rx_queue[i].name, "%s-rx-%d", 2107 adapter->netdev->name, vector); 2108 else 2109 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d", 2110 adapter->netdev->name, vector); 2111 err = request_irq(intr->msix_entries[vector].vector, 2112 vmxnet3_msix_rx, 0, 2113 adapter->rx_queue[i].name, 2114 &(adapter->rx_queue[i])); 2115 if (err) { 2116 netdev_err(adapter->netdev, 2117 "Failed to request irq for MSIX, " 2118 "%s, error %d\n", 2119 adapter->rx_queue[i].name, err); 2120 return err; 2121 } 2122 2123 adapter->rx_queue[i].comp_ring.intr_idx = vector++; 2124 } 2125 2126 sprintf(intr->event_msi_vector_name, "%s-event-%d", 2127 adapter->netdev->name, vector); 2128 err = request_irq(intr->msix_entries[vector].vector, 2129 vmxnet3_msix_event, 0, 2130 intr->event_msi_vector_name, adapter->netdev); 2131 intr->event_intr_idx = vector; 2132 2133 } else if (intr->type == VMXNET3_IT_MSI) { 2134 adapter->num_rx_queues = 1; 2135 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0, 2136 adapter->netdev->name, adapter->netdev); 2137 } else { 2138 #endif 2139 adapter->num_rx_queues = 1; 2140 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 2141 IRQF_SHARED, adapter->netdev->name, 2142 adapter->netdev); 2143 #ifdef CONFIG_PCI_MSI 2144 } 2145 #endif 2146 intr->num_intrs = vector + 1; 2147 if (err) { 2148 netdev_err(adapter->netdev, 2149 "Failed to request irq (intr type:%d), error %d\n", 2150 intr->type, err); 2151 } else { 2152 /* Number of rx queues will not change after this */ 2153 for (i = 0; i < adapter->num_rx_queues; i++) { 2154 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2155 rq->qid = i; 2156 rq->qid2 = i + adapter->num_rx_queues; 2157 rq->dataRingQid = i + 2 * adapter->num_rx_queues; 2158 } 2159 2160 /* init our intr settings */ 2161 for (i = 0; i < intr->num_intrs; i++) 2162 intr->mod_levels[i] = UPT1_IML_ADAPTIVE; 2163 if (adapter->intr.type != VMXNET3_IT_MSIX) { 2164 adapter->intr.event_intr_idx = 0; 2165 for (i = 0; i < adapter->num_tx_queues; i++) 2166 adapter->tx_queue[i].comp_ring.intr_idx = 0; 2167 adapter->rx_queue[0].comp_ring.intr_idx = 0; 2168 } 2169 2170 netdev_info(adapter->netdev, 2171 "intr type %u, mode %u, %u vectors allocated\n", 2172 intr->type, intr->mask_mode, intr->num_intrs); 2173 } 2174 2175 return err; 2176 } 2177 2178 2179 static void 2180 vmxnet3_free_irqs(struct vmxnet3_adapter *adapter) 2181 { 2182 struct vmxnet3_intr *intr = &adapter->intr; 2183 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0); 2184 2185 switch (intr->type) { 2186 #ifdef CONFIG_PCI_MSI 2187 case VMXNET3_IT_MSIX: 2188 { 2189 int i, vector = 0; 2190 2191 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) { 2192 for (i = 0; i < adapter->num_tx_queues; i++) { 2193 free_irq(intr->msix_entries[vector++].vector, 2194 &(adapter->tx_queue[i])); 2195 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) 2196 break; 2197 } 2198 } 2199 2200 for (i = 0; i < adapter->num_rx_queues; i++) { 2201 free_irq(intr->msix_entries[vector++].vector, 2202 &(adapter->rx_queue[i])); 2203 } 2204 2205 free_irq(intr->msix_entries[vector].vector, 2206 adapter->netdev); 2207 BUG_ON(vector >= intr->num_intrs); 2208 break; 2209 } 2210 #endif 2211 case VMXNET3_IT_MSI: 2212 free_irq(adapter->pdev->irq, adapter->netdev); 2213 break; 2214 case VMXNET3_IT_INTX: 2215 free_irq(adapter->pdev->irq, adapter->netdev); 2216 break; 2217 default: 2218 BUG(); 2219 } 2220 } 2221 2222 2223 static void 2224 vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter) 2225 { 2226 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2227 u16 vid; 2228 2229 /* allow untagged pkts */ 2230 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0); 2231 2232 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 2233 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 2234 } 2235 2236 2237 static int 2238 vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid) 2239 { 2240 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2241 2242 if (!(netdev->flags & IFF_PROMISC)) { 2243 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2244 unsigned long flags; 2245 2246 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid); 2247 spin_lock_irqsave(&adapter->cmd_lock, flags); 2248 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2249 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2250 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2251 } 2252 2253 set_bit(vid, adapter->active_vlans); 2254 2255 return 0; 2256 } 2257 2258 2259 static int 2260 vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) 2261 { 2262 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2263 2264 if (!(netdev->flags & IFF_PROMISC)) { 2265 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2266 unsigned long flags; 2267 2268 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid); 2269 spin_lock_irqsave(&adapter->cmd_lock, flags); 2270 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2271 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2272 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2273 } 2274 2275 clear_bit(vid, adapter->active_vlans); 2276 2277 return 0; 2278 } 2279 2280 2281 static u8 * 2282 vmxnet3_copy_mc(struct net_device *netdev) 2283 { 2284 u8 *buf = NULL; 2285 u32 sz = netdev_mc_count(netdev) * ETH_ALEN; 2286 2287 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */ 2288 if (sz <= 0xffff) { 2289 /* We may be called with BH disabled */ 2290 buf = kmalloc(sz, GFP_ATOMIC); 2291 if (buf) { 2292 struct netdev_hw_addr *ha; 2293 int i = 0; 2294 2295 netdev_for_each_mc_addr(ha, netdev) 2296 memcpy(buf + i++ * ETH_ALEN, ha->addr, 2297 ETH_ALEN); 2298 } 2299 } 2300 return buf; 2301 } 2302 2303 2304 static void 2305 vmxnet3_set_mc(struct net_device *netdev) 2306 { 2307 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2308 unsigned long flags; 2309 struct Vmxnet3_RxFilterConf *rxConf = 2310 &adapter->shared->devRead.rxFilterConf; 2311 u8 *new_table = NULL; 2312 dma_addr_t new_table_pa = 0; 2313 bool new_table_pa_valid = false; 2314 u32 new_mode = VMXNET3_RXM_UCAST; 2315 2316 if (netdev->flags & IFF_PROMISC) { 2317 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable; 2318 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable)); 2319 2320 new_mode |= VMXNET3_RXM_PROMISC; 2321 } else { 2322 vmxnet3_restore_vlan(adapter); 2323 } 2324 2325 if (netdev->flags & IFF_BROADCAST) 2326 new_mode |= VMXNET3_RXM_BCAST; 2327 2328 if (netdev->flags & IFF_ALLMULTI) 2329 new_mode |= VMXNET3_RXM_ALL_MULTI; 2330 else 2331 if (!netdev_mc_empty(netdev)) { 2332 new_table = vmxnet3_copy_mc(netdev); 2333 if (new_table) { 2334 size_t sz = netdev_mc_count(netdev) * ETH_ALEN; 2335 2336 rxConf->mfTableLen = cpu_to_le16(sz); 2337 new_table_pa = dma_map_single( 2338 &adapter->pdev->dev, 2339 new_table, 2340 sz, 2341 PCI_DMA_TODEVICE); 2342 if (!dma_mapping_error(&adapter->pdev->dev, 2343 new_table_pa)) { 2344 new_mode |= VMXNET3_RXM_MCAST; 2345 new_table_pa_valid = true; 2346 rxConf->mfTablePA = cpu_to_le64( 2347 new_table_pa); 2348 } 2349 } 2350 if (!new_table_pa_valid) { 2351 netdev_info(netdev, 2352 "failed to copy mcast list, setting ALL_MULTI\n"); 2353 new_mode |= VMXNET3_RXM_ALL_MULTI; 2354 } 2355 } 2356 2357 if (!(new_mode & VMXNET3_RXM_MCAST)) { 2358 rxConf->mfTableLen = 0; 2359 rxConf->mfTablePA = 0; 2360 } 2361 2362 spin_lock_irqsave(&adapter->cmd_lock, flags); 2363 if (new_mode != rxConf->rxMode) { 2364 rxConf->rxMode = cpu_to_le32(new_mode); 2365 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2366 VMXNET3_CMD_UPDATE_RX_MODE); 2367 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2368 VMXNET3_CMD_UPDATE_VLAN_FILTERS); 2369 } 2370 2371 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2372 VMXNET3_CMD_UPDATE_MAC_FILTERS); 2373 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2374 2375 if (new_table_pa_valid) 2376 dma_unmap_single(&adapter->pdev->dev, new_table_pa, 2377 rxConf->mfTableLen, PCI_DMA_TODEVICE); 2378 kfree(new_table); 2379 } 2380 2381 void 2382 vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter) 2383 { 2384 int i; 2385 2386 for (i = 0; i < adapter->num_rx_queues; i++) 2387 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter); 2388 } 2389 2390 2391 /* 2392 * Set up driver_shared based on settings in adapter. 2393 */ 2394 2395 static void 2396 vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter) 2397 { 2398 struct Vmxnet3_DriverShared *shared = adapter->shared; 2399 struct Vmxnet3_DSDevRead *devRead = &shared->devRead; 2400 struct Vmxnet3_TxQueueConf *tqc; 2401 struct Vmxnet3_RxQueueConf *rqc; 2402 int i; 2403 2404 memset(shared, 0, sizeof(*shared)); 2405 2406 /* driver settings */ 2407 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC); 2408 devRead->misc.driverInfo.version = cpu_to_le32( 2409 VMXNET3_DRIVER_VERSION_NUM); 2410 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ? 2411 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64); 2412 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX; 2413 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32( 2414 *((u32 *)&devRead->misc.driverInfo.gos)); 2415 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1); 2416 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1); 2417 2418 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa); 2419 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter)); 2420 2421 /* set up feature flags */ 2422 if (adapter->netdev->features & NETIF_F_RXCSUM) 2423 devRead->misc.uptFeatures |= UPT1_F_RXCSUM; 2424 2425 if (adapter->netdev->features & NETIF_F_LRO) { 2426 devRead->misc.uptFeatures |= UPT1_F_LRO; 2427 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS); 2428 } 2429 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) 2430 devRead->misc.uptFeatures |= UPT1_F_RXVLAN; 2431 2432 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu); 2433 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa); 2434 devRead->misc.queueDescLen = cpu_to_le32( 2435 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) + 2436 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc)); 2437 2438 /* tx queue settings */ 2439 devRead->misc.numTxQueues = adapter->num_tx_queues; 2440 for (i = 0; i < adapter->num_tx_queues; i++) { 2441 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2442 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL); 2443 tqc = &adapter->tqd_start[i].conf; 2444 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA); 2445 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA); 2446 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA); 2447 tqc->ddPA = cpu_to_le64(tq->buf_info_pa); 2448 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size); 2449 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size); 2450 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size); 2451 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size); 2452 tqc->ddLen = cpu_to_le32( 2453 sizeof(struct vmxnet3_tx_buf_info) * 2454 tqc->txRingSize); 2455 tqc->intrIdx = tq->comp_ring.intr_idx; 2456 } 2457 2458 /* rx queue settings */ 2459 devRead->misc.numRxQueues = adapter->num_rx_queues; 2460 for (i = 0; i < adapter->num_rx_queues; i++) { 2461 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2462 rqc = &adapter->rqd_start[i].conf; 2463 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA); 2464 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA); 2465 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA); 2466 rqc->ddPA = cpu_to_le64(rq->buf_info_pa); 2467 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size); 2468 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size); 2469 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size); 2470 rqc->ddLen = cpu_to_le32( 2471 sizeof(struct vmxnet3_rx_buf_info) * 2472 (rqc->rxRingSize[0] + 2473 rqc->rxRingSize[1])); 2474 rqc->intrIdx = rq->comp_ring.intr_idx; 2475 if (VMXNET3_VERSION_GE_3(adapter)) { 2476 rqc->rxDataRingBasePA = 2477 cpu_to_le64(rq->data_ring.basePA); 2478 rqc->rxDataRingDescSize = 2479 cpu_to_le16(rq->data_ring.desc_size); 2480 } 2481 } 2482 2483 #ifdef VMXNET3_RSS 2484 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf)); 2485 2486 if (adapter->rss) { 2487 struct UPT1_RSSConf *rssConf = adapter->rss_conf; 2488 2489 devRead->misc.uptFeatures |= UPT1_F_RSS; 2490 devRead->misc.numRxQueues = adapter->num_rx_queues; 2491 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 | 2492 UPT1_RSS_HASH_TYPE_IPV4 | 2493 UPT1_RSS_HASH_TYPE_TCP_IPV6 | 2494 UPT1_RSS_HASH_TYPE_IPV6; 2495 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ; 2496 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE; 2497 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE; 2498 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey)); 2499 2500 for (i = 0; i < rssConf->indTableSize; i++) 2501 rssConf->indTable[i] = ethtool_rxfh_indir_default( 2502 i, adapter->num_rx_queues); 2503 2504 devRead->rssConfDesc.confVer = 1; 2505 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf)); 2506 devRead->rssConfDesc.confPA = 2507 cpu_to_le64(adapter->rss_conf_pa); 2508 } 2509 2510 #endif /* VMXNET3_RSS */ 2511 2512 /* intr settings */ 2513 devRead->intrConf.autoMask = adapter->intr.mask_mode == 2514 VMXNET3_IMM_AUTO; 2515 devRead->intrConf.numIntrs = adapter->intr.num_intrs; 2516 for (i = 0; i < adapter->intr.num_intrs; i++) 2517 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i]; 2518 2519 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx; 2520 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL); 2521 2522 /* rx filter settings */ 2523 devRead->rxFilterConf.rxMode = 0; 2524 vmxnet3_restore_vlan(adapter); 2525 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr); 2526 2527 /* the rest are already zeroed */ 2528 } 2529 2530 static void 2531 vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter) 2532 { 2533 struct Vmxnet3_DriverShared *shared = adapter->shared; 2534 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo; 2535 unsigned long flags; 2536 2537 if (!VMXNET3_VERSION_GE_3(adapter)) 2538 return; 2539 2540 spin_lock_irqsave(&adapter->cmd_lock, flags); 2541 cmdInfo->varConf.confVer = 1; 2542 cmdInfo->varConf.confLen = 2543 cpu_to_le32(sizeof(*adapter->coal_conf)); 2544 cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa); 2545 2546 if (adapter->default_coal_mode) { 2547 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2548 VMXNET3_CMD_GET_COALESCE); 2549 } else { 2550 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2551 VMXNET3_CMD_SET_COALESCE); 2552 } 2553 2554 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2555 } 2556 2557 int 2558 vmxnet3_activate_dev(struct vmxnet3_adapter *adapter) 2559 { 2560 int err, i; 2561 u32 ret; 2562 unsigned long flags; 2563 2564 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d," 2565 " ring sizes %u %u %u\n", adapter->netdev->name, 2566 adapter->skb_buf_size, adapter->rx_buf_per_pkt, 2567 adapter->tx_queue[0].tx_ring.size, 2568 adapter->rx_queue[0].rx_ring[0].size, 2569 adapter->rx_queue[0].rx_ring[1].size); 2570 2571 vmxnet3_tq_init_all(adapter); 2572 err = vmxnet3_rq_init_all(adapter); 2573 if (err) { 2574 netdev_err(adapter->netdev, 2575 "Failed to init rx queue error %d\n", err); 2576 goto rq_err; 2577 } 2578 2579 err = vmxnet3_request_irqs(adapter); 2580 if (err) { 2581 netdev_err(adapter->netdev, 2582 "Failed to setup irq for error %d\n", err); 2583 goto irq_err; 2584 } 2585 2586 vmxnet3_setup_driver_shared(adapter); 2587 2588 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO( 2589 adapter->shared_pa)); 2590 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI( 2591 adapter->shared_pa)); 2592 spin_lock_irqsave(&adapter->cmd_lock, flags); 2593 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2594 VMXNET3_CMD_ACTIVATE_DEV); 2595 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 2596 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2597 2598 if (ret != 0) { 2599 netdev_err(adapter->netdev, 2600 "Failed to activate dev: error %u\n", ret); 2601 err = -EINVAL; 2602 goto activate_err; 2603 } 2604 2605 vmxnet3_init_coalesce(adapter); 2606 2607 for (i = 0; i < adapter->num_rx_queues; i++) { 2608 VMXNET3_WRITE_BAR0_REG(adapter, 2609 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN, 2610 adapter->rx_queue[i].rx_ring[0].next2fill); 2611 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 + 2612 (i * VMXNET3_REG_ALIGN)), 2613 adapter->rx_queue[i].rx_ring[1].next2fill); 2614 } 2615 2616 /* Apply the rx filter settins last. */ 2617 vmxnet3_set_mc(adapter->netdev); 2618 2619 /* 2620 * Check link state when first activating device. It will start the 2621 * tx queue if the link is up. 2622 */ 2623 vmxnet3_check_link(adapter, true); 2624 for (i = 0; i < adapter->num_rx_queues; i++) 2625 napi_enable(&adapter->rx_queue[i].napi); 2626 vmxnet3_enable_all_intrs(adapter); 2627 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2628 return 0; 2629 2630 activate_err: 2631 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0); 2632 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0); 2633 vmxnet3_free_irqs(adapter); 2634 irq_err: 2635 rq_err: 2636 /* free up buffers we allocated */ 2637 vmxnet3_rq_cleanup_all(adapter); 2638 return err; 2639 } 2640 2641 2642 void 2643 vmxnet3_reset_dev(struct vmxnet3_adapter *adapter) 2644 { 2645 unsigned long flags; 2646 spin_lock_irqsave(&adapter->cmd_lock, flags); 2647 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV); 2648 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2649 } 2650 2651 2652 int 2653 vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter) 2654 { 2655 int i; 2656 unsigned long flags; 2657 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state)) 2658 return 0; 2659 2660 2661 spin_lock_irqsave(&adapter->cmd_lock, flags); 2662 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2663 VMXNET3_CMD_QUIESCE_DEV); 2664 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2665 vmxnet3_disable_all_intrs(adapter); 2666 2667 for (i = 0; i < adapter->num_rx_queues; i++) 2668 napi_disable(&adapter->rx_queue[i].napi); 2669 netif_tx_disable(adapter->netdev); 2670 adapter->link_speed = 0; 2671 netif_carrier_off(adapter->netdev); 2672 2673 vmxnet3_tq_cleanup_all(adapter); 2674 vmxnet3_rq_cleanup_all(adapter); 2675 vmxnet3_free_irqs(adapter); 2676 return 0; 2677 } 2678 2679 2680 static void 2681 vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 2682 { 2683 u32 tmp; 2684 2685 tmp = *(u32 *)mac; 2686 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp); 2687 2688 tmp = (mac[5] << 8) | mac[4]; 2689 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp); 2690 } 2691 2692 2693 static int 2694 vmxnet3_set_mac_addr(struct net_device *netdev, void *p) 2695 { 2696 struct sockaddr *addr = p; 2697 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2698 2699 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 2700 vmxnet3_write_mac_addr(adapter, addr->sa_data); 2701 2702 return 0; 2703 } 2704 2705 2706 /* ==================== initialization and cleanup routines ============ */ 2707 2708 static int 2709 vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter) 2710 { 2711 int err; 2712 unsigned long mmio_start, mmio_len; 2713 struct pci_dev *pdev = adapter->pdev; 2714 2715 err = pci_enable_device(pdev); 2716 if (err) { 2717 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err); 2718 return err; 2719 } 2720 2721 err = pci_request_selected_regions(pdev, (1 << 2) - 1, 2722 vmxnet3_driver_name); 2723 if (err) { 2724 dev_err(&pdev->dev, 2725 "Failed to request region for adapter: error %d\n", err); 2726 goto err_enable_device; 2727 } 2728 2729 pci_set_master(pdev); 2730 2731 mmio_start = pci_resource_start(pdev, 0); 2732 mmio_len = pci_resource_len(pdev, 0); 2733 adapter->hw_addr0 = ioremap(mmio_start, mmio_len); 2734 if (!adapter->hw_addr0) { 2735 dev_err(&pdev->dev, "Failed to map bar0\n"); 2736 err = -EIO; 2737 goto err_ioremap; 2738 } 2739 2740 mmio_start = pci_resource_start(pdev, 1); 2741 mmio_len = pci_resource_len(pdev, 1); 2742 adapter->hw_addr1 = ioremap(mmio_start, mmio_len); 2743 if (!adapter->hw_addr1) { 2744 dev_err(&pdev->dev, "Failed to map bar1\n"); 2745 err = -EIO; 2746 goto err_bar1; 2747 } 2748 return 0; 2749 2750 err_bar1: 2751 iounmap(adapter->hw_addr0); 2752 err_ioremap: 2753 pci_release_selected_regions(pdev, (1 << 2) - 1); 2754 err_enable_device: 2755 pci_disable_device(pdev); 2756 return err; 2757 } 2758 2759 2760 static void 2761 vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter) 2762 { 2763 BUG_ON(!adapter->pdev); 2764 2765 iounmap(adapter->hw_addr0); 2766 iounmap(adapter->hw_addr1); 2767 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1); 2768 pci_disable_device(adapter->pdev); 2769 } 2770 2771 2772 static void 2773 vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter) 2774 { 2775 size_t sz, i, ring0_size, ring1_size, comp_size; 2776 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE - 2777 VMXNET3_MAX_ETH_HDR_SIZE) { 2778 adapter->skb_buf_size = adapter->netdev->mtu + 2779 VMXNET3_MAX_ETH_HDR_SIZE; 2780 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE) 2781 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE; 2782 2783 adapter->rx_buf_per_pkt = 1; 2784 } else { 2785 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE; 2786 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE + 2787 VMXNET3_MAX_ETH_HDR_SIZE; 2788 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE; 2789 } 2790 2791 /* 2792 * for simplicity, force the ring0 size to be a multiple of 2793 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN 2794 */ 2795 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN; 2796 ring0_size = adapter->rx_queue[0].rx_ring[0].size; 2797 ring0_size = (ring0_size + sz - 1) / sz * sz; 2798 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE / 2799 sz * sz); 2800 ring1_size = adapter->rx_queue[0].rx_ring[1].size; 2801 ring1_size = (ring1_size + sz - 1) / sz * sz; 2802 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE / 2803 sz * sz); 2804 comp_size = ring0_size + ring1_size; 2805 2806 for (i = 0; i < adapter->num_rx_queues; i++) { 2807 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2808 2809 rq->rx_ring[0].size = ring0_size; 2810 rq->rx_ring[1].size = ring1_size; 2811 rq->comp_ring.size = comp_size; 2812 } 2813 } 2814 2815 2816 int 2817 vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size, 2818 u32 rx_ring_size, u32 rx_ring2_size, 2819 u16 txdata_desc_size, u16 rxdata_desc_size) 2820 { 2821 int err = 0, i; 2822 2823 for (i = 0; i < adapter->num_tx_queues; i++) { 2824 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i]; 2825 tq->tx_ring.size = tx_ring_size; 2826 tq->data_ring.size = tx_ring_size; 2827 tq->comp_ring.size = tx_ring_size; 2828 tq->txdata_desc_size = txdata_desc_size; 2829 tq->shared = &adapter->tqd_start[i].ctrl; 2830 tq->stopped = true; 2831 tq->adapter = adapter; 2832 tq->qid = i; 2833 err = vmxnet3_tq_create(tq, adapter); 2834 /* 2835 * Too late to change num_tx_queues. We cannot do away with 2836 * lesser number of queues than what we asked for 2837 */ 2838 if (err) 2839 goto queue_err; 2840 } 2841 2842 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size; 2843 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size; 2844 vmxnet3_adjust_rx_ring_size(adapter); 2845 2846 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter); 2847 for (i = 0; i < adapter->num_rx_queues; i++) { 2848 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i]; 2849 /* qid and qid2 for rx queues will be assigned later when num 2850 * of rx queues is finalized after allocating intrs */ 2851 rq->shared = &adapter->rqd_start[i].ctrl; 2852 rq->adapter = adapter; 2853 rq->data_ring.desc_size = rxdata_desc_size; 2854 err = vmxnet3_rq_create(rq, adapter); 2855 if (err) { 2856 if (i == 0) { 2857 netdev_err(adapter->netdev, 2858 "Could not allocate any rx queues. " 2859 "Aborting.\n"); 2860 goto queue_err; 2861 } else { 2862 netdev_info(adapter->netdev, 2863 "Number of rx queues changed " 2864 "to : %d.\n", i); 2865 adapter->num_rx_queues = i; 2866 err = 0; 2867 break; 2868 } 2869 } 2870 } 2871 2872 if (!adapter->rxdataring_enabled) 2873 vmxnet3_rq_destroy_all_rxdataring(adapter); 2874 2875 return err; 2876 queue_err: 2877 vmxnet3_tq_destroy_all(adapter); 2878 return err; 2879 } 2880 2881 static int 2882 vmxnet3_open(struct net_device *netdev) 2883 { 2884 struct vmxnet3_adapter *adapter; 2885 int err, i; 2886 2887 adapter = netdev_priv(netdev); 2888 2889 for (i = 0; i < adapter->num_tx_queues; i++) 2890 spin_lock_init(&adapter->tx_queue[i].tx_lock); 2891 2892 if (VMXNET3_VERSION_GE_3(adapter)) { 2893 unsigned long flags; 2894 u16 txdata_desc_size; 2895 2896 spin_lock_irqsave(&adapter->cmd_lock, flags); 2897 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 2898 VMXNET3_CMD_GET_TXDATA_DESC_SIZE); 2899 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter, 2900 VMXNET3_REG_CMD); 2901 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 2902 2903 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) || 2904 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) || 2905 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) { 2906 adapter->txdata_desc_size = 2907 sizeof(struct Vmxnet3_TxDataDesc); 2908 } else { 2909 adapter->txdata_desc_size = txdata_desc_size; 2910 } 2911 } else { 2912 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc); 2913 } 2914 2915 err = vmxnet3_create_queues(adapter, 2916 adapter->tx_ring_size, 2917 adapter->rx_ring_size, 2918 adapter->rx_ring2_size, 2919 adapter->txdata_desc_size, 2920 adapter->rxdata_desc_size); 2921 if (err) 2922 goto queue_err; 2923 2924 err = vmxnet3_activate_dev(adapter); 2925 if (err) 2926 goto activate_err; 2927 2928 return 0; 2929 2930 activate_err: 2931 vmxnet3_rq_destroy_all(adapter); 2932 vmxnet3_tq_destroy_all(adapter); 2933 queue_err: 2934 return err; 2935 } 2936 2937 2938 static int 2939 vmxnet3_close(struct net_device *netdev) 2940 { 2941 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2942 2943 /* 2944 * Reset_work may be in the middle of resetting the device, wait for its 2945 * completion. 2946 */ 2947 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2948 usleep_range(1000, 2000); 2949 2950 vmxnet3_quiesce_dev(adapter); 2951 2952 vmxnet3_rq_destroy_all(adapter); 2953 vmxnet3_tq_destroy_all(adapter); 2954 2955 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 2956 2957 2958 return 0; 2959 } 2960 2961 2962 void 2963 vmxnet3_force_close(struct vmxnet3_adapter *adapter) 2964 { 2965 int i; 2966 2967 /* 2968 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise 2969 * vmxnet3_close() will deadlock. 2970 */ 2971 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)); 2972 2973 /* we need to enable NAPI, otherwise dev_close will deadlock */ 2974 for (i = 0; i < adapter->num_rx_queues; i++) 2975 napi_enable(&adapter->rx_queue[i].napi); 2976 /* 2977 * Need to clear the quiesce bit to ensure that vmxnet3_close 2978 * can quiesce the device properly 2979 */ 2980 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 2981 dev_close(adapter->netdev); 2982 } 2983 2984 2985 static int 2986 vmxnet3_change_mtu(struct net_device *netdev, int new_mtu) 2987 { 2988 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 2989 int err = 0; 2990 2991 netdev->mtu = new_mtu; 2992 2993 /* 2994 * Reset_work may be in the middle of resetting the device, wait for its 2995 * completion. 2996 */ 2997 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 2998 usleep_range(1000, 2000); 2999 3000 if (netif_running(netdev)) { 3001 vmxnet3_quiesce_dev(adapter); 3002 vmxnet3_reset_dev(adapter); 3003 3004 /* we need to re-create the rx queue based on the new mtu */ 3005 vmxnet3_rq_destroy_all(adapter); 3006 vmxnet3_adjust_rx_ring_size(adapter); 3007 err = vmxnet3_rq_create_all(adapter); 3008 if (err) { 3009 netdev_err(netdev, 3010 "failed to re-create rx queues, " 3011 " error %d. Closing it.\n", err); 3012 goto out; 3013 } 3014 3015 err = vmxnet3_activate_dev(adapter); 3016 if (err) { 3017 netdev_err(netdev, 3018 "failed to re-activate, error %d. " 3019 "Closing it\n", err); 3020 goto out; 3021 } 3022 } 3023 3024 out: 3025 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3026 if (err) 3027 vmxnet3_force_close(adapter); 3028 3029 return err; 3030 } 3031 3032 3033 static void 3034 vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64) 3035 { 3036 struct net_device *netdev = adapter->netdev; 3037 3038 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM | 3039 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX | 3040 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 | 3041 NETIF_F_LRO; 3042 if (dma64) 3043 netdev->hw_features |= NETIF_F_HIGHDMA; 3044 netdev->vlan_features = netdev->hw_features & 3045 ~(NETIF_F_HW_VLAN_CTAG_TX | 3046 NETIF_F_HW_VLAN_CTAG_RX); 3047 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; 3048 } 3049 3050 3051 static void 3052 vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac) 3053 { 3054 u32 tmp; 3055 3056 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL); 3057 *(u32 *)mac = tmp; 3058 3059 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH); 3060 mac[4] = tmp & 0xff; 3061 mac[5] = (tmp >> 8) & 0xff; 3062 } 3063 3064 #ifdef CONFIG_PCI_MSI 3065 3066 /* 3067 * Enable MSIx vectors. 3068 * Returns : 3069 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required 3070 * were enabled. 3071 * number of vectors which were enabled otherwise (this number is greater 3072 * than VMXNET3_LINUX_MIN_MSIX_VECT) 3073 */ 3074 3075 static int 3076 vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec) 3077 { 3078 int ret = pci_enable_msix_range(adapter->pdev, 3079 adapter->intr.msix_entries, nvec, nvec); 3080 3081 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) { 3082 dev_err(&adapter->netdev->dev, 3083 "Failed to enable %d MSI-X, trying %d\n", 3084 nvec, VMXNET3_LINUX_MIN_MSIX_VECT); 3085 3086 ret = pci_enable_msix_range(adapter->pdev, 3087 adapter->intr.msix_entries, 3088 VMXNET3_LINUX_MIN_MSIX_VECT, 3089 VMXNET3_LINUX_MIN_MSIX_VECT); 3090 } 3091 3092 if (ret < 0) { 3093 dev_err(&adapter->netdev->dev, 3094 "Failed to enable MSI-X, error: %d\n", ret); 3095 } 3096 3097 return ret; 3098 } 3099 3100 3101 #endif /* CONFIG_PCI_MSI */ 3102 3103 static void 3104 vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter) 3105 { 3106 u32 cfg; 3107 unsigned long flags; 3108 3109 /* intr settings */ 3110 spin_lock_irqsave(&adapter->cmd_lock, flags); 3111 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3112 VMXNET3_CMD_GET_CONF_INTR); 3113 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD); 3114 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3115 adapter->intr.type = cfg & 0x3; 3116 adapter->intr.mask_mode = (cfg >> 2) & 0x3; 3117 3118 if (adapter->intr.type == VMXNET3_IT_AUTO) { 3119 adapter->intr.type = VMXNET3_IT_MSIX; 3120 } 3121 3122 #ifdef CONFIG_PCI_MSI 3123 if (adapter->intr.type == VMXNET3_IT_MSIX) { 3124 int i, nvec; 3125 3126 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ? 3127 1 : adapter->num_tx_queues; 3128 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ? 3129 0 : adapter->num_rx_queues; 3130 nvec += 1; /* for link event */ 3131 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ? 3132 nvec : VMXNET3_LINUX_MIN_MSIX_VECT; 3133 3134 for (i = 0; i < nvec; i++) 3135 adapter->intr.msix_entries[i].entry = i; 3136 3137 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec); 3138 if (nvec < 0) 3139 goto msix_err; 3140 3141 /* If we cannot allocate one MSIx vector per queue 3142 * then limit the number of rx queues to 1 3143 */ 3144 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) { 3145 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE 3146 || adapter->num_rx_queues != 1) { 3147 adapter->share_intr = VMXNET3_INTR_TXSHARE; 3148 netdev_err(adapter->netdev, 3149 "Number of rx queues : 1\n"); 3150 adapter->num_rx_queues = 1; 3151 } 3152 } 3153 3154 adapter->intr.num_intrs = nvec; 3155 return; 3156 3157 msix_err: 3158 /* If we cannot allocate MSIx vectors use only one rx queue */ 3159 dev_info(&adapter->pdev->dev, 3160 "Failed to enable MSI-X, error %d. " 3161 "Limiting #rx queues to 1, try MSI.\n", nvec); 3162 3163 adapter->intr.type = VMXNET3_IT_MSI; 3164 } 3165 3166 if (adapter->intr.type == VMXNET3_IT_MSI) { 3167 if (!pci_enable_msi(adapter->pdev)) { 3168 adapter->num_rx_queues = 1; 3169 adapter->intr.num_intrs = 1; 3170 return; 3171 } 3172 } 3173 #endif /* CONFIG_PCI_MSI */ 3174 3175 adapter->num_rx_queues = 1; 3176 dev_info(&adapter->netdev->dev, 3177 "Using INTx interrupt, #Rx queues: 1.\n"); 3178 adapter->intr.type = VMXNET3_IT_INTX; 3179 3180 /* INT-X related setting */ 3181 adapter->intr.num_intrs = 1; 3182 } 3183 3184 3185 static void 3186 vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter) 3187 { 3188 if (adapter->intr.type == VMXNET3_IT_MSIX) 3189 pci_disable_msix(adapter->pdev); 3190 else if (adapter->intr.type == VMXNET3_IT_MSI) 3191 pci_disable_msi(adapter->pdev); 3192 else 3193 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX); 3194 } 3195 3196 3197 static void 3198 vmxnet3_tx_timeout(struct net_device *netdev, unsigned int txqueue) 3199 { 3200 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3201 adapter->tx_timeout_count++; 3202 3203 netdev_err(adapter->netdev, "tx hang\n"); 3204 schedule_work(&adapter->work); 3205 } 3206 3207 3208 static void 3209 vmxnet3_reset_work(struct work_struct *data) 3210 { 3211 struct vmxnet3_adapter *adapter; 3212 3213 adapter = container_of(data, struct vmxnet3_adapter, work); 3214 3215 /* if another thread is resetting the device, no need to proceed */ 3216 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 3217 return; 3218 3219 /* if the device is closed, we must leave it alone */ 3220 rtnl_lock(); 3221 if (netif_running(adapter->netdev)) { 3222 netdev_notice(adapter->netdev, "resetting\n"); 3223 vmxnet3_quiesce_dev(adapter); 3224 vmxnet3_reset_dev(adapter); 3225 vmxnet3_activate_dev(adapter); 3226 } else { 3227 netdev_info(adapter->netdev, "already closed\n"); 3228 } 3229 rtnl_unlock(); 3230 3231 netif_wake_queue(adapter->netdev); 3232 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3233 } 3234 3235 3236 static int 3237 vmxnet3_probe_device(struct pci_dev *pdev, 3238 const struct pci_device_id *id) 3239 { 3240 static const struct net_device_ops vmxnet3_netdev_ops = { 3241 .ndo_open = vmxnet3_open, 3242 .ndo_stop = vmxnet3_close, 3243 .ndo_start_xmit = vmxnet3_xmit_frame, 3244 .ndo_set_mac_address = vmxnet3_set_mac_addr, 3245 .ndo_change_mtu = vmxnet3_change_mtu, 3246 .ndo_fix_features = vmxnet3_fix_features, 3247 .ndo_set_features = vmxnet3_set_features, 3248 .ndo_get_stats64 = vmxnet3_get_stats64, 3249 .ndo_tx_timeout = vmxnet3_tx_timeout, 3250 .ndo_set_rx_mode = vmxnet3_set_mc, 3251 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid, 3252 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid, 3253 #ifdef CONFIG_NET_POLL_CONTROLLER 3254 .ndo_poll_controller = vmxnet3_netpoll, 3255 #endif 3256 }; 3257 int err; 3258 bool dma64; 3259 u32 ver; 3260 struct net_device *netdev; 3261 struct vmxnet3_adapter *adapter; 3262 u8 mac[ETH_ALEN]; 3263 int size; 3264 int num_tx_queues; 3265 int num_rx_queues; 3266 3267 if (!pci_msi_enabled()) 3268 enable_mq = 0; 3269 3270 #ifdef VMXNET3_RSS 3271 if (enable_mq) 3272 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 3273 (int)num_online_cpus()); 3274 else 3275 #endif 3276 num_rx_queues = 1; 3277 num_rx_queues = rounddown_pow_of_two(num_rx_queues); 3278 3279 if (enable_mq) 3280 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES, 3281 (int)num_online_cpus()); 3282 else 3283 num_tx_queues = 1; 3284 3285 num_tx_queues = rounddown_pow_of_two(num_tx_queues); 3286 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter), 3287 max(num_tx_queues, num_rx_queues)); 3288 dev_info(&pdev->dev, 3289 "# of Tx queues : %d, # of Rx queues : %d\n", 3290 num_tx_queues, num_rx_queues); 3291 3292 if (!netdev) 3293 return -ENOMEM; 3294 3295 pci_set_drvdata(pdev, netdev); 3296 adapter = netdev_priv(netdev); 3297 adapter->netdev = netdev; 3298 adapter->pdev = pdev; 3299 3300 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE; 3301 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE; 3302 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE; 3303 3304 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) { 3305 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) { 3306 dev_err(&pdev->dev, 3307 "pci_set_consistent_dma_mask failed\n"); 3308 err = -EIO; 3309 goto err_set_mask; 3310 } 3311 dma64 = true; 3312 } else { 3313 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) { 3314 dev_err(&pdev->dev, 3315 "pci_set_dma_mask failed\n"); 3316 err = -EIO; 3317 goto err_set_mask; 3318 } 3319 dma64 = false; 3320 } 3321 3322 spin_lock_init(&adapter->cmd_lock); 3323 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter, 3324 sizeof(struct vmxnet3_adapter), 3325 PCI_DMA_TODEVICE); 3326 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) { 3327 dev_err(&pdev->dev, "Failed to map dma\n"); 3328 err = -EFAULT; 3329 goto err_set_mask; 3330 } 3331 adapter->shared = dma_alloc_coherent( 3332 &adapter->pdev->dev, 3333 sizeof(struct Vmxnet3_DriverShared), 3334 &adapter->shared_pa, GFP_KERNEL); 3335 if (!adapter->shared) { 3336 dev_err(&pdev->dev, "Failed to allocate memory\n"); 3337 err = -ENOMEM; 3338 goto err_alloc_shared; 3339 } 3340 3341 adapter->num_rx_queues = num_rx_queues; 3342 adapter->num_tx_queues = num_tx_queues; 3343 adapter->rx_buf_per_pkt = 1; 3344 3345 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 3346 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues; 3347 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size, 3348 &adapter->queue_desc_pa, 3349 GFP_KERNEL); 3350 3351 if (!adapter->tqd_start) { 3352 dev_err(&pdev->dev, "Failed to allocate memory\n"); 3353 err = -ENOMEM; 3354 goto err_alloc_queue_desc; 3355 } 3356 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start + 3357 adapter->num_tx_queues); 3358 3359 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev, 3360 sizeof(struct Vmxnet3_PMConf), 3361 &adapter->pm_conf_pa, 3362 GFP_KERNEL); 3363 if (adapter->pm_conf == NULL) { 3364 err = -ENOMEM; 3365 goto err_alloc_pm; 3366 } 3367 3368 #ifdef VMXNET3_RSS 3369 3370 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev, 3371 sizeof(struct UPT1_RSSConf), 3372 &adapter->rss_conf_pa, 3373 GFP_KERNEL); 3374 if (adapter->rss_conf == NULL) { 3375 err = -ENOMEM; 3376 goto err_alloc_rss; 3377 } 3378 #endif /* VMXNET3_RSS */ 3379 3380 err = vmxnet3_alloc_pci_resources(adapter); 3381 if (err < 0) 3382 goto err_alloc_pci; 3383 3384 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS); 3385 if (ver & (1 << VMXNET3_REV_3)) { 3386 VMXNET3_WRITE_BAR1_REG(adapter, 3387 VMXNET3_REG_VRRS, 3388 1 << VMXNET3_REV_3); 3389 adapter->version = VMXNET3_REV_3 + 1; 3390 } else if (ver & (1 << VMXNET3_REV_2)) { 3391 VMXNET3_WRITE_BAR1_REG(adapter, 3392 VMXNET3_REG_VRRS, 3393 1 << VMXNET3_REV_2); 3394 adapter->version = VMXNET3_REV_2 + 1; 3395 } else if (ver & (1 << VMXNET3_REV_1)) { 3396 VMXNET3_WRITE_BAR1_REG(adapter, 3397 VMXNET3_REG_VRRS, 3398 1 << VMXNET3_REV_1); 3399 adapter->version = VMXNET3_REV_1 + 1; 3400 } else { 3401 dev_err(&pdev->dev, 3402 "Incompatible h/w version (0x%x) for adapter\n", ver); 3403 err = -EBUSY; 3404 goto err_ver; 3405 } 3406 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version); 3407 3408 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS); 3409 if (ver & 1) { 3410 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1); 3411 } else { 3412 dev_err(&pdev->dev, 3413 "Incompatible upt version (0x%x) for adapter\n", ver); 3414 err = -EBUSY; 3415 goto err_ver; 3416 } 3417 3418 if (VMXNET3_VERSION_GE_3(adapter)) { 3419 adapter->coal_conf = 3420 dma_alloc_coherent(&adapter->pdev->dev, 3421 sizeof(struct Vmxnet3_CoalesceScheme) 3422 , 3423 &adapter->coal_conf_pa, 3424 GFP_KERNEL); 3425 if (!adapter->coal_conf) { 3426 err = -ENOMEM; 3427 goto err_ver; 3428 } 3429 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED; 3430 adapter->default_coal_mode = true; 3431 } 3432 3433 SET_NETDEV_DEV(netdev, &pdev->dev); 3434 vmxnet3_declare_features(adapter, dma64); 3435 3436 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ? 3437 VMXNET3_DEF_RXDATA_DESC_SIZE : 0; 3438 3439 if (adapter->num_tx_queues == adapter->num_rx_queues) 3440 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE; 3441 else 3442 adapter->share_intr = VMXNET3_INTR_DONTSHARE; 3443 3444 vmxnet3_alloc_intr_resources(adapter); 3445 3446 #ifdef VMXNET3_RSS 3447 if (adapter->num_rx_queues > 1 && 3448 adapter->intr.type == VMXNET3_IT_MSIX) { 3449 adapter->rss = true; 3450 netdev->hw_features |= NETIF_F_RXHASH; 3451 netdev->features |= NETIF_F_RXHASH; 3452 dev_dbg(&pdev->dev, "RSS is enabled.\n"); 3453 } else { 3454 adapter->rss = false; 3455 } 3456 #endif 3457 3458 vmxnet3_read_mac_addr(adapter, mac); 3459 memcpy(netdev->dev_addr, mac, netdev->addr_len); 3460 3461 netdev->netdev_ops = &vmxnet3_netdev_ops; 3462 vmxnet3_set_ethtool_ops(netdev); 3463 netdev->watchdog_timeo = 5 * HZ; 3464 3465 /* MTU range: 60 - 9000 */ 3466 netdev->min_mtu = VMXNET3_MIN_MTU; 3467 netdev->max_mtu = VMXNET3_MAX_MTU; 3468 3469 INIT_WORK(&adapter->work, vmxnet3_reset_work); 3470 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state); 3471 3472 if (adapter->intr.type == VMXNET3_IT_MSIX) { 3473 int i; 3474 for (i = 0; i < adapter->num_rx_queues; i++) { 3475 netif_napi_add(adapter->netdev, 3476 &adapter->rx_queue[i].napi, 3477 vmxnet3_poll_rx_only, 64); 3478 } 3479 } else { 3480 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi, 3481 vmxnet3_poll, 64); 3482 } 3483 3484 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); 3485 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues); 3486 3487 netif_carrier_off(netdev); 3488 err = register_netdev(netdev); 3489 3490 if (err) { 3491 dev_err(&pdev->dev, "Failed to register adapter\n"); 3492 goto err_register; 3493 } 3494 3495 vmxnet3_check_link(adapter, false); 3496 return 0; 3497 3498 err_register: 3499 if (VMXNET3_VERSION_GE_3(adapter)) { 3500 dma_free_coherent(&adapter->pdev->dev, 3501 sizeof(struct Vmxnet3_CoalesceScheme), 3502 adapter->coal_conf, adapter->coal_conf_pa); 3503 } 3504 vmxnet3_free_intr_resources(adapter); 3505 err_ver: 3506 vmxnet3_free_pci_resources(adapter); 3507 err_alloc_pci: 3508 #ifdef VMXNET3_RSS 3509 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf), 3510 adapter->rss_conf, adapter->rss_conf_pa); 3511 err_alloc_rss: 3512 #endif 3513 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf), 3514 adapter->pm_conf, adapter->pm_conf_pa); 3515 err_alloc_pm: 3516 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start, 3517 adapter->queue_desc_pa); 3518 err_alloc_queue_desc: 3519 dma_free_coherent(&adapter->pdev->dev, 3520 sizeof(struct Vmxnet3_DriverShared), 3521 adapter->shared, adapter->shared_pa); 3522 err_alloc_shared: 3523 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa, 3524 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE); 3525 err_set_mask: 3526 free_netdev(netdev); 3527 return err; 3528 } 3529 3530 3531 static void 3532 vmxnet3_remove_device(struct pci_dev *pdev) 3533 { 3534 struct net_device *netdev = pci_get_drvdata(pdev); 3535 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3536 int size = 0; 3537 int num_rx_queues; 3538 3539 #ifdef VMXNET3_RSS 3540 if (enable_mq) 3541 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES, 3542 (int)num_online_cpus()); 3543 else 3544 #endif 3545 num_rx_queues = 1; 3546 num_rx_queues = rounddown_pow_of_two(num_rx_queues); 3547 3548 cancel_work_sync(&adapter->work); 3549 3550 unregister_netdev(netdev); 3551 3552 vmxnet3_free_intr_resources(adapter); 3553 vmxnet3_free_pci_resources(adapter); 3554 if (VMXNET3_VERSION_GE_3(adapter)) { 3555 dma_free_coherent(&adapter->pdev->dev, 3556 sizeof(struct Vmxnet3_CoalesceScheme), 3557 adapter->coal_conf, adapter->coal_conf_pa); 3558 } 3559 #ifdef VMXNET3_RSS 3560 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf), 3561 adapter->rss_conf, adapter->rss_conf_pa); 3562 #endif 3563 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf), 3564 adapter->pm_conf, adapter->pm_conf_pa); 3565 3566 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues; 3567 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues; 3568 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start, 3569 adapter->queue_desc_pa); 3570 dma_free_coherent(&adapter->pdev->dev, 3571 sizeof(struct Vmxnet3_DriverShared), 3572 adapter->shared, adapter->shared_pa); 3573 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa, 3574 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE); 3575 free_netdev(netdev); 3576 } 3577 3578 static void vmxnet3_shutdown_device(struct pci_dev *pdev) 3579 { 3580 struct net_device *netdev = pci_get_drvdata(pdev); 3581 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3582 unsigned long flags; 3583 3584 /* Reset_work may be in the middle of resetting the device, wait for its 3585 * completion. 3586 */ 3587 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state)) 3588 usleep_range(1000, 2000); 3589 3590 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, 3591 &adapter->state)) { 3592 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3593 return; 3594 } 3595 spin_lock_irqsave(&adapter->cmd_lock, flags); 3596 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3597 VMXNET3_CMD_QUIESCE_DEV); 3598 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3599 vmxnet3_disable_all_intrs(adapter); 3600 3601 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state); 3602 } 3603 3604 3605 #ifdef CONFIG_PM 3606 3607 static int 3608 vmxnet3_suspend(struct device *device) 3609 { 3610 struct pci_dev *pdev = to_pci_dev(device); 3611 struct net_device *netdev = pci_get_drvdata(pdev); 3612 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3613 struct Vmxnet3_PMConf *pmConf; 3614 struct ethhdr *ehdr; 3615 struct arphdr *ahdr; 3616 u8 *arpreq; 3617 struct in_device *in_dev; 3618 struct in_ifaddr *ifa; 3619 unsigned long flags; 3620 int i = 0; 3621 3622 if (!netif_running(netdev)) 3623 return 0; 3624 3625 for (i = 0; i < adapter->num_rx_queues; i++) 3626 napi_disable(&adapter->rx_queue[i].napi); 3627 3628 vmxnet3_disable_all_intrs(adapter); 3629 vmxnet3_free_irqs(adapter); 3630 vmxnet3_free_intr_resources(adapter); 3631 3632 netif_device_detach(netdev); 3633 netif_tx_stop_all_queues(netdev); 3634 3635 /* Create wake-up filters. */ 3636 pmConf = adapter->pm_conf; 3637 memset(pmConf, 0, sizeof(*pmConf)); 3638 3639 if (adapter->wol & WAKE_UCAST) { 3640 pmConf->filters[i].patternSize = ETH_ALEN; 3641 pmConf->filters[i].maskSize = 1; 3642 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN); 3643 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */ 3644 3645 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3646 i++; 3647 } 3648 3649 if (adapter->wol & WAKE_ARP) { 3650 rcu_read_lock(); 3651 3652 in_dev = __in_dev_get_rcu(netdev); 3653 if (!in_dev) { 3654 rcu_read_unlock(); 3655 goto skip_arp; 3656 } 3657 3658 ifa = rcu_dereference(in_dev->ifa_list); 3659 if (!ifa) { 3660 rcu_read_unlock(); 3661 goto skip_arp; 3662 } 3663 3664 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/ 3665 sizeof(struct arphdr) + /* ARP header */ 3666 2 * ETH_ALEN + /* 2 Ethernet addresses*/ 3667 2 * sizeof(u32); /*2 IPv4 addresses */ 3668 pmConf->filters[i].maskSize = 3669 (pmConf->filters[i].patternSize - 1) / 8 + 1; 3670 3671 /* ETH_P_ARP in Ethernet header. */ 3672 ehdr = (struct ethhdr *)pmConf->filters[i].pattern; 3673 ehdr->h_proto = htons(ETH_P_ARP); 3674 3675 /* ARPOP_REQUEST in ARP header. */ 3676 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN]; 3677 ahdr->ar_op = htons(ARPOP_REQUEST); 3678 arpreq = (u8 *)(ahdr + 1); 3679 3680 /* The Unicast IPv4 address in 'tip' field. */ 3681 arpreq += 2 * ETH_ALEN + sizeof(u32); 3682 *(__be32 *)arpreq = ifa->ifa_address; 3683 3684 rcu_read_unlock(); 3685 3686 /* The mask for the relevant bits. */ 3687 pmConf->filters[i].mask[0] = 0x00; 3688 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */ 3689 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */ 3690 pmConf->filters[i].mask[3] = 0x00; 3691 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */ 3692 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */ 3693 3694 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER; 3695 i++; 3696 } 3697 3698 skip_arp: 3699 if (adapter->wol & WAKE_MAGIC) 3700 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC; 3701 3702 pmConf->numFilters = i; 3703 3704 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1); 3705 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof( 3706 *pmConf)); 3707 adapter->shared->devRead.pmConfDesc.confPA = 3708 cpu_to_le64(adapter->pm_conf_pa); 3709 3710 spin_lock_irqsave(&adapter->cmd_lock, flags); 3711 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3712 VMXNET3_CMD_UPDATE_PMCFG); 3713 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3714 3715 pci_save_state(pdev); 3716 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND), 3717 adapter->wol); 3718 pci_disable_device(pdev); 3719 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND)); 3720 3721 return 0; 3722 } 3723 3724 3725 static int 3726 vmxnet3_resume(struct device *device) 3727 { 3728 int err; 3729 unsigned long flags; 3730 struct pci_dev *pdev = to_pci_dev(device); 3731 struct net_device *netdev = pci_get_drvdata(pdev); 3732 struct vmxnet3_adapter *adapter = netdev_priv(netdev); 3733 3734 if (!netif_running(netdev)) 3735 return 0; 3736 3737 pci_set_power_state(pdev, PCI_D0); 3738 pci_restore_state(pdev); 3739 err = pci_enable_device_mem(pdev); 3740 if (err != 0) 3741 return err; 3742 3743 pci_enable_wake(pdev, PCI_D0, 0); 3744 3745 vmxnet3_alloc_intr_resources(adapter); 3746 3747 /* During hibernate and suspend, device has to be reinitialized as the 3748 * device state need not be preserved. 3749 */ 3750 3751 /* Need not check adapter state as other reset tasks cannot run during 3752 * device resume. 3753 */ 3754 spin_lock_irqsave(&adapter->cmd_lock, flags); 3755 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, 3756 VMXNET3_CMD_QUIESCE_DEV); 3757 spin_unlock_irqrestore(&adapter->cmd_lock, flags); 3758 vmxnet3_tq_cleanup_all(adapter); 3759 vmxnet3_rq_cleanup_all(adapter); 3760 3761 vmxnet3_reset_dev(adapter); 3762 err = vmxnet3_activate_dev(adapter); 3763 if (err != 0) { 3764 netdev_err(netdev, 3765 "failed to re-activate on resume, error: %d", err); 3766 vmxnet3_force_close(adapter); 3767 return err; 3768 } 3769 netif_device_attach(netdev); 3770 3771 return 0; 3772 } 3773 3774 static const struct dev_pm_ops vmxnet3_pm_ops = { 3775 .suspend = vmxnet3_suspend, 3776 .resume = vmxnet3_resume, 3777 .freeze = vmxnet3_suspend, 3778 .restore = vmxnet3_resume, 3779 }; 3780 #endif 3781 3782 static struct pci_driver vmxnet3_driver = { 3783 .name = vmxnet3_driver_name, 3784 .id_table = vmxnet3_pciid_table, 3785 .probe = vmxnet3_probe_device, 3786 .remove = vmxnet3_remove_device, 3787 .shutdown = vmxnet3_shutdown_device, 3788 #ifdef CONFIG_PM 3789 .driver.pm = &vmxnet3_pm_ops, 3790 #endif 3791 }; 3792 3793 3794 static int __init 3795 vmxnet3_init_module(void) 3796 { 3797 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC, 3798 VMXNET3_DRIVER_VERSION_REPORT); 3799 return pci_register_driver(&vmxnet3_driver); 3800 } 3801 3802 module_init(vmxnet3_init_module); 3803 3804 3805 static void 3806 vmxnet3_exit_module(void) 3807 { 3808 pci_unregister_driver(&vmxnet3_driver); 3809 } 3810 3811 module_exit(vmxnet3_exit_module); 3812 3813 MODULE_AUTHOR("VMware, Inc."); 3814 MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC); 3815 MODULE_LICENSE("GPL v2"); 3816 MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING); 3817