1 /* 2 * DM81xx hwmod data. 3 * 4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/ 5 * Copyright (C) 2013 SKTB SKiT, http://www.skitlab.ru/ 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation version 2. 10 * 11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 12 * kind, whether express or implied; without even the implied warranty 13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 */ 17 18 #include <linux/types.h> 19 20 #include <linux/platform_data/hsmmc-omap.h> 21 22 #include "omap_hwmod_common_data.h" 23 #include "cm81xx.h" 24 #include "ti81xx.h" 25 #include "wd_timer.h" 26 27 /* 28 * DM816X hardware modules integration data 29 * 30 * Note: This is incomplete and at present, not generated from h/w database. 31 */ 32 33 /* 34 * Common alwon .clkctrl_offs from dm814x TRM "Table 2-278. CM_ALWON REGISTERS" 35 * also dm816x TRM 18.7.17 CM_ALWON device register values minus 0x1400. 36 */ 37 #define DM81XX_CM_ALWON_MCASP0_CLKCTRL 0x140 38 #define DM81XX_CM_ALWON_MCASP1_CLKCTRL 0x144 39 #define DM81XX_CM_ALWON_MCASP2_CLKCTRL 0x148 40 #define DM81XX_CM_ALWON_MCBSP_CLKCTRL 0x14c 41 #define DM81XX_CM_ALWON_UART_0_CLKCTRL 0x150 42 #define DM81XX_CM_ALWON_UART_1_CLKCTRL 0x154 43 #define DM81XX_CM_ALWON_UART_2_CLKCTRL 0x158 44 #define DM81XX_CM_ALWON_GPIO_0_CLKCTRL 0x15c 45 #define DM81XX_CM_ALWON_GPIO_1_CLKCTRL 0x160 46 #define DM81XX_CM_ALWON_I2C_0_CLKCTRL 0x164 47 #define DM81XX_CM_ALWON_I2C_1_CLKCTRL 0x168 48 #define DM81XX_CM_ALWON_WDTIMER_CLKCTRL 0x18c 49 #define DM81XX_CM_ALWON_SPI_CLKCTRL 0x190 50 #define DM81XX_CM_ALWON_MAILBOX_CLKCTRL 0x194 51 #define DM81XX_CM_ALWON_SPINBOX_CLKCTRL 0x198 52 #define DM81XX_CM_ALWON_MMUDATA_CLKCTRL 0x19c 53 #define DM81XX_CM_ALWON_MMUCFG_CLKCTRL 0x1a8 54 #define DM81XX_CM_ALWON_CONTROL_CLKCTRL 0x1c4 55 #define DM81XX_CM_ALWON_GPMC_CLKCTRL 0x1d0 56 #define DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL 0x1d4 57 #define DM81XX_CM_ALWON_L3_CLKCTRL 0x1e4 58 #define DM81XX_CM_ALWON_L4HS_CLKCTRL 0x1e8 59 #define DM81XX_CM_ALWON_L4LS_CLKCTRL 0x1ec 60 #define DM81XX_CM_ALWON_RTC_CLKCTRL 0x1f0 61 #define DM81XX_CM_ALWON_TPCC_CLKCTRL 0x1f4 62 #define DM81XX_CM_ALWON_TPTC0_CLKCTRL 0x1f8 63 #define DM81XX_CM_ALWON_TPTC1_CLKCTRL 0x1fc 64 #define DM81XX_CM_ALWON_TPTC2_CLKCTRL 0x200 65 #define DM81XX_CM_ALWON_TPTC3_CLKCTRL 0x204 66 67 /* Registers specific to dm814x */ 68 #define DM814X_CM_ALWON_MCASP_3_4_5_CLKCTRL 0x16c 69 #define DM814X_CM_ALWON_ATL_CLKCTRL 0x170 70 #define DM814X_CM_ALWON_MLB_CLKCTRL 0x174 71 #define DM814X_CM_ALWON_PATA_CLKCTRL 0x178 72 #define DM814X_CM_ALWON_UART_3_CLKCTRL 0x180 73 #define DM814X_CM_ALWON_UART_4_CLKCTRL 0x184 74 #define DM814X_CM_ALWON_UART_5_CLKCTRL 0x188 75 #define DM814X_CM_ALWON_OCM_0_CLKCTRL 0x1b4 76 #define DM814X_CM_ALWON_VCP_CLKCTRL 0x1b8 77 #define DM814X_CM_ALWON_MPU_CLKCTRL 0x1dc 78 #define DM814X_CM_ALWON_DEBUGSS_CLKCTRL 0x1e0 79 #define DM814X_CM_ALWON_DCAN_0_1_CLKCTRL 0x218 80 #define DM814X_CM_ALWON_MMCHS_0_CLKCTRL 0x21c 81 #define DM814X_CM_ALWON_MMCHS_1_CLKCTRL 0x220 82 #define DM814X_CM_ALWON_MMCHS_2_CLKCTRL 0x224 83 #define DM814X_CM_ALWON_CUST_EFUSE_CLKCTRL 0x228 84 85 /* Registers specific to dm816x */ 86 #define DM816X_DM_ALWON_BASE 0x1400 87 #define DM816X_CM_ALWON_TIMER_1_CLKCTRL (0x1570 - DM816X_DM_ALWON_BASE) 88 #define DM816X_CM_ALWON_TIMER_2_CLKCTRL (0x1574 - DM816X_DM_ALWON_BASE) 89 #define DM816X_CM_ALWON_TIMER_3_CLKCTRL (0x1578 - DM816X_DM_ALWON_BASE) 90 #define DM816X_CM_ALWON_TIMER_4_CLKCTRL (0x157c - DM816X_DM_ALWON_BASE) 91 #define DM816X_CM_ALWON_TIMER_5_CLKCTRL (0x1580 - DM816X_DM_ALWON_BASE) 92 #define DM816X_CM_ALWON_TIMER_6_CLKCTRL (0x1584 - DM816X_DM_ALWON_BASE) 93 #define DM816X_CM_ALWON_TIMER_7_CLKCTRL (0x1588 - DM816X_DM_ALWON_BASE) 94 #define DM816X_CM_ALWON_SDIO_CLKCTRL (0x15b0 - DM816X_DM_ALWON_BASE) 95 #define DM816X_CM_ALWON_OCMC_0_CLKCTRL (0x15b4 - DM816X_DM_ALWON_BASE) 96 #define DM816X_CM_ALWON_OCMC_1_CLKCTRL (0x15b8 - DM816X_DM_ALWON_BASE) 97 #define DM816X_CM_ALWON_ETHERNET_1_CLKCTRL (0x15d8 - DM816X_DM_ALWON_BASE) 98 #define DM816X_CM_ALWON_MPU_CLKCTRL (0x15dc - DM816X_DM_ALWON_BASE) 99 #define DM816X_CM_ALWON_SR_0_CLKCTRL (0x1608 - DM816X_DM_ALWON_BASE) 100 #define DM816X_CM_ALWON_SR_1_CLKCTRL (0x160c - DM816X_DM_ALWON_BASE) 101 102 /* 103 * The default .clkctrl_offs field is offset from CM_DEFAULT, that's 104 * TRM 18.7.6 CM_DEFAULT device register values minus 0x500 105 */ 106 #define DM81XX_CM_DEFAULT_OFFSET 0x500 107 #define DM81XX_CM_DEFAULT_USB_CLKCTRL (0x558 - DM81XX_CM_DEFAULT_OFFSET) 108 #define DM81XX_CM_DEFAULT_SATA_CLKCTRL (0x560 - DM81XX_CM_DEFAULT_OFFSET) 109 110 /* L3 Interconnect entries clocked at 125, 250 and 500MHz */ 111 static struct omap_hwmod dm81xx_alwon_l3_slow_hwmod = { 112 .name = "alwon_l3_slow", 113 .clkdm_name = "alwon_l3s_clkdm", 114 .class = &l3_hwmod_class, 115 .flags = HWMOD_NO_IDLEST, 116 }; 117 118 static struct omap_hwmod dm81xx_default_l3_slow_hwmod = { 119 .name = "default_l3_slow", 120 .clkdm_name = "default_l3_slow_clkdm", 121 .class = &l3_hwmod_class, 122 .flags = HWMOD_NO_IDLEST, 123 }; 124 125 static struct omap_hwmod dm81xx_alwon_l3_med_hwmod = { 126 .name = "l3_med", 127 .clkdm_name = "alwon_l3_med_clkdm", 128 .class = &l3_hwmod_class, 129 .flags = HWMOD_NO_IDLEST, 130 }; 131 132 /* 133 * L4 standard peripherals, see TRM table 1-12 for devices using this. 134 * See TRM table 1-73 for devices using the 125MHz SYSCLK6 clock. 135 */ 136 static struct omap_hwmod dm81xx_l4_ls_hwmod = { 137 .name = "l4_ls", 138 .clkdm_name = "alwon_l3s_clkdm", 139 .class = &l4_hwmod_class, 140 .flags = HWMOD_NO_IDLEST, 141 }; 142 143 /* 144 * L4 high-speed peripherals. For devices using this, please see the TRM 145 * table 1-13. On dm816x, only EMAC, MDIO and SATA use this. See also TRM 146 * table 1-73 for devices using 250MHz SYSCLK5 clock. 147 */ 148 static struct omap_hwmod dm81xx_l4_hs_hwmod = { 149 .name = "l4_hs", 150 .clkdm_name = "alwon_l3_med_clkdm", 151 .class = &l4_hwmod_class, 152 .flags = HWMOD_NO_IDLEST, 153 }; 154 155 /* L3 slow -> L4 ls peripheral interface running at 125MHz */ 156 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_ls = { 157 .master = &dm81xx_alwon_l3_slow_hwmod, 158 .slave = &dm81xx_l4_ls_hwmod, 159 .user = OCP_USER_MPU, 160 }; 161 162 /* L3 med -> L4 fast peripheral interface running at 250MHz */ 163 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__l4_hs = { 164 .master = &dm81xx_alwon_l3_med_hwmod, 165 .slave = &dm81xx_l4_hs_hwmod, 166 .user = OCP_USER_MPU, 167 }; 168 169 /* MPU */ 170 static struct omap_hwmod dm814x_mpu_hwmod = { 171 .name = "mpu", 172 .clkdm_name = "alwon_l3s_clkdm", 173 .class = &mpu_hwmod_class, 174 .flags = HWMOD_INIT_NO_IDLE, 175 .main_clk = "mpu_ck", 176 .prcm = { 177 .omap4 = { 178 .clkctrl_offs = DM814X_CM_ALWON_MPU_CLKCTRL, 179 .modulemode = MODULEMODE_SWCTRL, 180 }, 181 }, 182 }; 183 184 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_slow = { 185 .master = &dm814x_mpu_hwmod, 186 .slave = &dm81xx_alwon_l3_slow_hwmod, 187 .user = OCP_USER_MPU, 188 }; 189 190 /* L3 med peripheral interface running at 200MHz */ 191 static struct omap_hwmod_ocp_if dm814x_mpu__alwon_l3_med = { 192 .master = &dm814x_mpu_hwmod, 193 .slave = &dm81xx_alwon_l3_med_hwmod, 194 .user = OCP_USER_MPU, 195 }; 196 197 static struct omap_hwmod dm816x_mpu_hwmod = { 198 .name = "mpu", 199 .clkdm_name = "alwon_mpu_clkdm", 200 .class = &mpu_hwmod_class, 201 .flags = HWMOD_INIT_NO_IDLE, 202 .main_clk = "mpu_ck", 203 .prcm = { 204 .omap4 = { 205 .clkctrl_offs = DM816X_CM_ALWON_MPU_CLKCTRL, 206 .modulemode = MODULEMODE_SWCTRL, 207 }, 208 }, 209 }; 210 211 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_slow = { 212 .master = &dm816x_mpu_hwmod, 213 .slave = &dm81xx_alwon_l3_slow_hwmod, 214 .user = OCP_USER_MPU, 215 }; 216 217 /* L3 med peripheral interface running at 250MHz */ 218 static struct omap_hwmod_ocp_if dm816x_mpu__alwon_l3_med = { 219 .master = &dm816x_mpu_hwmod, 220 .slave = &dm81xx_alwon_l3_med_hwmod, 221 .user = OCP_USER_MPU, 222 }; 223 224 /* RTC */ 225 static struct omap_hwmod_class_sysconfig ti81xx_rtc_sysc = { 226 .rev_offs = 0x74, 227 .sysc_offs = 0x78, 228 .sysc_flags = SYSC_HAS_SIDLEMODE, 229 .idlemodes = SIDLE_FORCE | SIDLE_NO | 230 SIDLE_SMART | SIDLE_SMART_WKUP, 231 .sysc_fields = &omap_hwmod_sysc_type3, 232 }; 233 234 static struct omap_hwmod_class ti81xx_rtc_hwmod_class = { 235 .name = "rtc", 236 .sysc = &ti81xx_rtc_sysc, 237 }; 238 239 static struct omap_hwmod ti81xx_rtc_hwmod = { 240 .name = "rtc", 241 .class = &ti81xx_rtc_hwmod_class, 242 .clkdm_name = "alwon_l3s_clkdm", 243 .flags = HWMOD_NO_IDLEST, 244 .main_clk = "sysclk18_ck", 245 .prcm = { 246 .omap4 = { 247 .clkctrl_offs = DM81XX_CM_ALWON_RTC_CLKCTRL, 248 .modulemode = MODULEMODE_SWCTRL, 249 }, 250 }, 251 }; 252 253 static struct omap_hwmod_ocp_if ti81xx_l4_ls__rtc = { 254 .master = &dm81xx_l4_ls_hwmod, 255 .slave = &ti81xx_rtc_hwmod, 256 .clk = "sysclk6_ck", 257 .user = OCP_USER_MPU, 258 }; 259 260 /* UART common */ 261 static struct omap_hwmod_class_sysconfig uart_sysc = { 262 .rev_offs = 0x50, 263 .sysc_offs = 0x54, 264 .syss_offs = 0x58, 265 .sysc_flags = SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | 266 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | 267 SYSS_HAS_RESET_STATUS, 268 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 269 MSTANDBY_SMART_WKUP, 270 .sysc_fields = &omap_hwmod_sysc_type1, 271 }; 272 273 static struct omap_hwmod_class uart_class = { 274 .name = "uart", 275 .sysc = &uart_sysc, 276 }; 277 278 static struct omap_hwmod dm81xx_uart1_hwmod = { 279 .name = "uart1", 280 .clkdm_name = "alwon_l3s_clkdm", 281 .main_clk = "sysclk10_ck", 282 .prcm = { 283 .omap4 = { 284 .clkctrl_offs = DM81XX_CM_ALWON_UART_0_CLKCTRL, 285 .modulemode = MODULEMODE_SWCTRL, 286 }, 287 }, 288 .class = &uart_class, 289 .flags = DEBUG_TI81XXUART1_FLAGS, 290 }; 291 292 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart1 = { 293 .master = &dm81xx_l4_ls_hwmod, 294 .slave = &dm81xx_uart1_hwmod, 295 .clk = "sysclk6_ck", 296 .user = OCP_USER_MPU, 297 }; 298 299 static struct omap_hwmod dm81xx_uart2_hwmod = { 300 .name = "uart2", 301 .clkdm_name = "alwon_l3s_clkdm", 302 .main_clk = "sysclk10_ck", 303 .prcm = { 304 .omap4 = { 305 .clkctrl_offs = DM81XX_CM_ALWON_UART_1_CLKCTRL, 306 .modulemode = MODULEMODE_SWCTRL, 307 }, 308 }, 309 .class = &uart_class, 310 .flags = DEBUG_TI81XXUART2_FLAGS, 311 }; 312 313 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart2 = { 314 .master = &dm81xx_l4_ls_hwmod, 315 .slave = &dm81xx_uart2_hwmod, 316 .clk = "sysclk6_ck", 317 .user = OCP_USER_MPU, 318 }; 319 320 static struct omap_hwmod dm81xx_uart3_hwmod = { 321 .name = "uart3", 322 .clkdm_name = "alwon_l3s_clkdm", 323 .main_clk = "sysclk10_ck", 324 .prcm = { 325 .omap4 = { 326 .clkctrl_offs = DM81XX_CM_ALWON_UART_2_CLKCTRL, 327 .modulemode = MODULEMODE_SWCTRL, 328 }, 329 }, 330 .class = &uart_class, 331 .flags = DEBUG_TI81XXUART3_FLAGS, 332 }; 333 334 static struct omap_hwmod_ocp_if dm81xx_l4_ls__uart3 = { 335 .master = &dm81xx_l4_ls_hwmod, 336 .slave = &dm81xx_uart3_hwmod, 337 .clk = "sysclk6_ck", 338 .user = OCP_USER_MPU, 339 }; 340 341 static struct omap_hwmod_class_sysconfig wd_timer_sysc = { 342 .rev_offs = 0x0, 343 .sysc_offs = 0x10, 344 .syss_offs = 0x14, 345 .sysc_flags = SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | 346 SYSS_HAS_RESET_STATUS, 347 .sysc_fields = &omap_hwmod_sysc_type1, 348 }; 349 350 static struct omap_hwmod_class wd_timer_class = { 351 .name = "wd_timer", 352 .sysc = &wd_timer_sysc, 353 .pre_shutdown = &omap2_wd_timer_disable, 354 .reset = &omap2_wd_timer_reset, 355 }; 356 357 static struct omap_hwmod dm81xx_wd_timer_hwmod = { 358 .name = "wd_timer", 359 .clkdm_name = "alwon_l3s_clkdm", 360 .main_clk = "sysclk18_ck", 361 .flags = HWMOD_NO_IDLEST, 362 .prcm = { 363 .omap4 = { 364 .clkctrl_offs = DM81XX_CM_ALWON_WDTIMER_CLKCTRL, 365 .modulemode = MODULEMODE_SWCTRL, 366 }, 367 }, 368 .class = &wd_timer_class, 369 }; 370 371 static struct omap_hwmod_ocp_if dm81xx_l4_ls__wd_timer1 = { 372 .master = &dm81xx_l4_ls_hwmod, 373 .slave = &dm81xx_wd_timer_hwmod, 374 .clk = "sysclk6_ck", 375 .user = OCP_USER_MPU, 376 }; 377 378 /* I2C common */ 379 static struct omap_hwmod_class_sysconfig i2c_sysc = { 380 .rev_offs = 0x0, 381 .sysc_offs = 0x10, 382 .syss_offs = 0x90, 383 .sysc_flags = SYSC_HAS_SIDLEMODE | 384 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 385 SYSC_HAS_AUTOIDLE, 386 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 387 .sysc_fields = &omap_hwmod_sysc_type1, 388 }; 389 390 static struct omap_hwmod_class i2c_class = { 391 .name = "i2c", 392 .sysc = &i2c_sysc, 393 }; 394 395 static struct omap_hwmod dm81xx_i2c1_hwmod = { 396 .name = "i2c1", 397 .clkdm_name = "alwon_l3s_clkdm", 398 .main_clk = "sysclk10_ck", 399 .prcm = { 400 .omap4 = { 401 .clkctrl_offs = DM81XX_CM_ALWON_I2C_0_CLKCTRL, 402 .modulemode = MODULEMODE_SWCTRL, 403 }, 404 }, 405 .class = &i2c_class, 406 }; 407 408 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c1 = { 409 .master = &dm81xx_l4_ls_hwmod, 410 .slave = &dm81xx_i2c1_hwmod, 411 .clk = "sysclk6_ck", 412 .user = OCP_USER_MPU, 413 }; 414 415 static struct omap_hwmod dm81xx_i2c2_hwmod = { 416 .name = "i2c2", 417 .clkdm_name = "alwon_l3s_clkdm", 418 .main_clk = "sysclk10_ck", 419 .prcm = { 420 .omap4 = { 421 .clkctrl_offs = DM81XX_CM_ALWON_I2C_1_CLKCTRL, 422 .modulemode = MODULEMODE_SWCTRL, 423 }, 424 }, 425 .class = &i2c_class, 426 }; 427 428 static struct omap_hwmod_ocp_if dm81xx_l4_ls__i2c2 = { 429 .master = &dm81xx_l4_ls_hwmod, 430 .slave = &dm81xx_i2c2_hwmod, 431 .clk = "sysclk6_ck", 432 .user = OCP_USER_MPU, 433 }; 434 435 static struct omap_hwmod_class_sysconfig dm81xx_elm_sysc = { 436 .rev_offs = 0x0000, 437 .sysc_offs = 0x0010, 438 .syss_offs = 0x0014, 439 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 440 SYSC_HAS_SOFTRESET | 441 SYSS_HAS_RESET_STATUS, 442 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 443 .sysc_fields = &omap_hwmod_sysc_type1, 444 }; 445 446 static struct omap_hwmod_class dm81xx_elm_hwmod_class = { 447 .name = "elm", 448 .sysc = &dm81xx_elm_sysc, 449 }; 450 451 static struct omap_hwmod dm81xx_elm_hwmod = { 452 .name = "elm", 453 .clkdm_name = "alwon_l3s_clkdm", 454 .class = &dm81xx_elm_hwmod_class, 455 .main_clk = "sysclk6_ck", 456 }; 457 458 static struct omap_hwmod_ocp_if dm81xx_l4_ls__elm = { 459 .master = &dm81xx_l4_ls_hwmod, 460 .slave = &dm81xx_elm_hwmod, 461 .clk = "sysclk6_ck", 462 .user = OCP_USER_MPU, 463 }; 464 465 static struct omap_hwmod_class_sysconfig dm81xx_gpio_sysc = { 466 .rev_offs = 0x0000, 467 .sysc_offs = 0x0010, 468 .syss_offs = 0x0114, 469 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | 470 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 471 SYSS_HAS_RESET_STATUS, 472 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 473 SIDLE_SMART_WKUP, 474 .sysc_fields = &omap_hwmod_sysc_type1, 475 }; 476 477 static struct omap_hwmod_class dm81xx_gpio_hwmod_class = { 478 .name = "gpio", 479 .sysc = &dm81xx_gpio_sysc, 480 }; 481 482 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { 483 { .role = "dbclk", .clk = "sysclk18_ck" }, 484 }; 485 486 static struct omap_hwmod dm81xx_gpio1_hwmod = { 487 .name = "gpio1", 488 .clkdm_name = "alwon_l3s_clkdm", 489 .class = &dm81xx_gpio_hwmod_class, 490 .main_clk = "sysclk6_ck", 491 .prcm = { 492 .omap4 = { 493 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_0_CLKCTRL, 494 .modulemode = MODULEMODE_SWCTRL, 495 }, 496 }, 497 .opt_clks = gpio1_opt_clks, 498 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), 499 }; 500 501 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio1 = { 502 .master = &dm81xx_l4_ls_hwmod, 503 .slave = &dm81xx_gpio1_hwmod, 504 .clk = "sysclk6_ck", 505 .user = OCP_USER_MPU, 506 }; 507 508 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { 509 { .role = "dbclk", .clk = "sysclk18_ck" }, 510 }; 511 512 static struct omap_hwmod dm81xx_gpio2_hwmod = { 513 .name = "gpio2", 514 .clkdm_name = "alwon_l3s_clkdm", 515 .class = &dm81xx_gpio_hwmod_class, 516 .main_clk = "sysclk6_ck", 517 .prcm = { 518 .omap4 = { 519 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, 520 .modulemode = MODULEMODE_SWCTRL, 521 }, 522 }, 523 .opt_clks = gpio2_opt_clks, 524 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), 525 }; 526 527 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio2 = { 528 .master = &dm81xx_l4_ls_hwmod, 529 .slave = &dm81xx_gpio2_hwmod, 530 .clk = "sysclk6_ck", 531 .user = OCP_USER_MPU, 532 }; 533 534 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { 535 { .role = "dbclk", .clk = "sysclk18_ck" }, 536 }; 537 538 static struct omap_hwmod dm81xx_gpio3_hwmod = { 539 .name = "gpio3", 540 .clkdm_name = "alwon_l3s_clkdm", 541 .class = &dm81xx_gpio_hwmod_class, 542 .main_clk = "sysclk6_ck", 543 .prcm = { 544 .omap4 = { 545 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, 546 .modulemode = MODULEMODE_SWCTRL, 547 }, 548 }, 549 .opt_clks = gpio3_opt_clks, 550 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), 551 }; 552 553 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio3 = { 554 .master = &dm81xx_l4_ls_hwmod, 555 .slave = &dm81xx_gpio3_hwmod, 556 .clk = "sysclk6_ck", 557 .user = OCP_USER_MPU, 558 }; 559 560 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { 561 { .role = "dbclk", .clk = "sysclk18_ck" }, 562 }; 563 564 static struct omap_hwmod dm81xx_gpio4_hwmod = { 565 .name = "gpio4", 566 .clkdm_name = "alwon_l3s_clkdm", 567 .class = &dm81xx_gpio_hwmod_class, 568 .main_clk = "sysclk6_ck", 569 .prcm = { 570 .omap4 = { 571 .clkctrl_offs = DM81XX_CM_ALWON_GPIO_1_CLKCTRL, 572 .modulemode = MODULEMODE_SWCTRL, 573 }, 574 }, 575 .opt_clks = gpio4_opt_clks, 576 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), 577 }; 578 579 static struct omap_hwmod_ocp_if dm81xx_l4_ls__gpio4 = { 580 .master = &dm81xx_l4_ls_hwmod, 581 .slave = &dm81xx_gpio4_hwmod, 582 .clk = "sysclk6_ck", 583 .user = OCP_USER_MPU, 584 }; 585 586 static struct omap_hwmod_class_sysconfig dm81xx_gpmc_sysc = { 587 .rev_offs = 0x0, 588 .sysc_offs = 0x10, 589 .syss_offs = 0x14, 590 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 591 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 592 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 593 .sysc_fields = &omap_hwmod_sysc_type1, 594 }; 595 596 static struct omap_hwmod_class dm81xx_gpmc_hwmod_class = { 597 .name = "gpmc", 598 .sysc = &dm81xx_gpmc_sysc, 599 }; 600 601 static struct omap_hwmod dm81xx_gpmc_hwmod = { 602 .name = "gpmc", 603 .clkdm_name = "alwon_l3s_clkdm", 604 .class = &dm81xx_gpmc_hwmod_class, 605 .main_clk = "sysclk6_ck", 606 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ 607 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS, 608 .prcm = { 609 .omap4 = { 610 .clkctrl_offs = DM81XX_CM_ALWON_GPMC_CLKCTRL, 611 .modulemode = MODULEMODE_SWCTRL, 612 }, 613 }, 614 }; 615 616 static struct omap_hwmod_ocp_if dm81xx_alwon_l3_slow__gpmc = { 617 .master = &dm81xx_alwon_l3_slow_hwmod, 618 .slave = &dm81xx_gpmc_hwmod, 619 .user = OCP_USER_MPU, 620 }; 621 622 /* USB needs udelay 1 after reset at least on hp t410, use 2 for margin */ 623 static struct omap_hwmod_class_sysconfig dm81xx_usbhsotg_sysc = { 624 .rev_offs = 0x0, 625 .sysc_offs = 0x10, 626 .srst_udelay = 2, 627 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | 628 SYSC_HAS_SOFTRESET, 629 .idlemodes = SIDLE_SMART | MSTANDBY_FORCE | MSTANDBY_SMART, 630 .sysc_fields = &omap_hwmod_sysc_type2, 631 }; 632 633 static struct omap_hwmod_class dm81xx_usbotg_class = { 634 .name = "usbotg", 635 .sysc = &dm81xx_usbhsotg_sysc, 636 }; 637 638 static struct omap_hwmod dm814x_usbss_hwmod = { 639 .name = "usb_otg_hs", 640 .clkdm_name = "default_l3_slow_clkdm", 641 .main_clk = "pll260dcoclkldo", /* 481c5260.adpll.dcoclkldo */ 642 .prcm = { 643 .omap4 = { 644 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, 645 .modulemode = MODULEMODE_SWCTRL, 646 }, 647 }, 648 .class = &dm81xx_usbotg_class, 649 }; 650 651 static struct omap_hwmod_ocp_if dm814x_default_l3_slow__usbss = { 652 .master = &dm81xx_default_l3_slow_hwmod, 653 .slave = &dm814x_usbss_hwmod, 654 .clk = "sysclk6_ck", 655 .user = OCP_USER_MPU, 656 }; 657 658 static struct omap_hwmod dm816x_usbss_hwmod = { 659 .name = "usb_otg_hs", 660 .clkdm_name = "default_l3_slow_clkdm", 661 .main_clk = "sysclk6_ck", 662 .prcm = { 663 .omap4 = { 664 .clkctrl_offs = DM81XX_CM_DEFAULT_USB_CLKCTRL, 665 .modulemode = MODULEMODE_SWCTRL, 666 }, 667 }, 668 .class = &dm81xx_usbotg_class, 669 }; 670 671 static struct omap_hwmod_ocp_if dm816x_default_l3_slow__usbss = { 672 .master = &dm81xx_default_l3_slow_hwmod, 673 .slave = &dm816x_usbss_hwmod, 674 .clk = "sysclk6_ck", 675 .user = OCP_USER_MPU, 676 }; 677 678 static struct omap_hwmod_class_sysconfig dm816x_timer_sysc = { 679 .rev_offs = 0x0000, 680 .sysc_offs = 0x0010, 681 .syss_offs = 0x0014, 682 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET, 683 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | 684 SIDLE_SMART_WKUP, 685 .sysc_fields = &omap_hwmod_sysc_type2, 686 }; 687 688 static struct omap_hwmod_class dm816x_timer_hwmod_class = { 689 .name = "timer", 690 .sysc = &dm816x_timer_sysc, 691 }; 692 693 static struct omap_hwmod dm814x_timer1_hwmod = { 694 .name = "timer1", 695 .clkdm_name = "alwon_l3s_clkdm", 696 .main_clk = "timer1_fck", 697 .class = &dm816x_timer_hwmod_class, 698 .flags = HWMOD_NO_IDLEST, 699 }; 700 701 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer1 = { 702 .master = &dm81xx_l4_ls_hwmod, 703 .slave = &dm814x_timer1_hwmod, 704 .clk = "sysclk6_ck", 705 .user = OCP_USER_MPU, 706 }; 707 708 static struct omap_hwmod dm816x_timer1_hwmod = { 709 .name = "timer1", 710 .clkdm_name = "alwon_l3s_clkdm", 711 .main_clk = "timer1_fck", 712 .prcm = { 713 .omap4 = { 714 .clkctrl_offs = DM816X_CM_ALWON_TIMER_1_CLKCTRL, 715 .modulemode = MODULEMODE_SWCTRL, 716 }, 717 }, 718 .class = &dm816x_timer_hwmod_class, 719 }; 720 721 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer1 = { 722 .master = &dm81xx_l4_ls_hwmod, 723 .slave = &dm816x_timer1_hwmod, 724 .clk = "sysclk6_ck", 725 .user = OCP_USER_MPU, 726 }; 727 728 static struct omap_hwmod dm814x_timer2_hwmod = { 729 .name = "timer2", 730 .clkdm_name = "alwon_l3s_clkdm", 731 .main_clk = "timer2_fck", 732 .class = &dm816x_timer_hwmod_class, 733 .flags = HWMOD_NO_IDLEST, 734 }; 735 736 static struct omap_hwmod_ocp_if dm814x_l4_ls__timer2 = { 737 .master = &dm81xx_l4_ls_hwmod, 738 .slave = &dm814x_timer2_hwmod, 739 .clk = "sysclk6_ck", 740 .user = OCP_USER_MPU, 741 }; 742 743 static struct omap_hwmod dm816x_timer2_hwmod = { 744 .name = "timer2", 745 .clkdm_name = "alwon_l3s_clkdm", 746 .main_clk = "timer2_fck", 747 .prcm = { 748 .omap4 = { 749 .clkctrl_offs = DM816X_CM_ALWON_TIMER_2_CLKCTRL, 750 .modulemode = MODULEMODE_SWCTRL, 751 }, 752 }, 753 .class = &dm816x_timer_hwmod_class, 754 }; 755 756 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer2 = { 757 .master = &dm81xx_l4_ls_hwmod, 758 .slave = &dm816x_timer2_hwmod, 759 .clk = "sysclk6_ck", 760 .user = OCP_USER_MPU, 761 }; 762 763 static struct omap_hwmod dm816x_timer3_hwmod = { 764 .name = "timer3", 765 .clkdm_name = "alwon_l3s_clkdm", 766 .main_clk = "timer3_fck", 767 .prcm = { 768 .omap4 = { 769 .clkctrl_offs = DM816X_CM_ALWON_TIMER_3_CLKCTRL, 770 .modulemode = MODULEMODE_SWCTRL, 771 }, 772 }, 773 .class = &dm816x_timer_hwmod_class, 774 }; 775 776 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer3 = { 777 .master = &dm81xx_l4_ls_hwmod, 778 .slave = &dm816x_timer3_hwmod, 779 .clk = "sysclk6_ck", 780 .user = OCP_USER_MPU, 781 }; 782 783 static struct omap_hwmod dm816x_timer4_hwmod = { 784 .name = "timer4", 785 .clkdm_name = "alwon_l3s_clkdm", 786 .main_clk = "timer4_fck", 787 .prcm = { 788 .omap4 = { 789 .clkctrl_offs = DM816X_CM_ALWON_TIMER_4_CLKCTRL, 790 .modulemode = MODULEMODE_SWCTRL, 791 }, 792 }, 793 .class = &dm816x_timer_hwmod_class, 794 }; 795 796 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer4 = { 797 .master = &dm81xx_l4_ls_hwmod, 798 .slave = &dm816x_timer4_hwmod, 799 .clk = "sysclk6_ck", 800 .user = OCP_USER_MPU, 801 }; 802 803 static struct omap_hwmod dm816x_timer5_hwmod = { 804 .name = "timer5", 805 .clkdm_name = "alwon_l3s_clkdm", 806 .main_clk = "timer5_fck", 807 .prcm = { 808 .omap4 = { 809 .clkctrl_offs = DM816X_CM_ALWON_TIMER_5_CLKCTRL, 810 .modulemode = MODULEMODE_SWCTRL, 811 }, 812 }, 813 .class = &dm816x_timer_hwmod_class, 814 }; 815 816 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer5 = { 817 .master = &dm81xx_l4_ls_hwmod, 818 .slave = &dm816x_timer5_hwmod, 819 .clk = "sysclk6_ck", 820 .user = OCP_USER_MPU, 821 }; 822 823 static struct omap_hwmod dm816x_timer6_hwmod = { 824 .name = "timer6", 825 .clkdm_name = "alwon_l3s_clkdm", 826 .main_clk = "timer6_fck", 827 .prcm = { 828 .omap4 = { 829 .clkctrl_offs = DM816X_CM_ALWON_TIMER_6_CLKCTRL, 830 .modulemode = MODULEMODE_SWCTRL, 831 }, 832 }, 833 .class = &dm816x_timer_hwmod_class, 834 }; 835 836 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer6 = { 837 .master = &dm81xx_l4_ls_hwmod, 838 .slave = &dm816x_timer6_hwmod, 839 .clk = "sysclk6_ck", 840 .user = OCP_USER_MPU, 841 }; 842 843 static struct omap_hwmod dm816x_timer7_hwmod = { 844 .name = "timer7", 845 .clkdm_name = "alwon_l3s_clkdm", 846 .main_clk = "timer7_fck", 847 .prcm = { 848 .omap4 = { 849 .clkctrl_offs = DM816X_CM_ALWON_TIMER_7_CLKCTRL, 850 .modulemode = MODULEMODE_SWCTRL, 851 }, 852 }, 853 .class = &dm816x_timer_hwmod_class, 854 }; 855 856 static struct omap_hwmod_ocp_if dm816x_l4_ls__timer7 = { 857 .master = &dm81xx_l4_ls_hwmod, 858 .slave = &dm816x_timer7_hwmod, 859 .clk = "sysclk6_ck", 860 .user = OCP_USER_MPU, 861 }; 862 863 /* EMAC Ethernet */ 864 static struct omap_hwmod_class_sysconfig dm816x_emac_sysc = { 865 .rev_offs = 0x0, 866 .sysc_offs = 0x4, 867 .sysc_flags = SYSC_HAS_SOFTRESET, 868 .sysc_fields = &omap_hwmod_sysc_type2, 869 }; 870 871 static struct omap_hwmod_class dm816x_emac_hwmod_class = { 872 .name = "emac", 873 .sysc = &dm816x_emac_sysc, 874 }; 875 876 /* 877 * On dm816x the MDIO is within EMAC0. As the MDIO driver is a separate 878 * driver probed before EMAC0, we let MDIO do the clock idling. 879 */ 880 static struct omap_hwmod dm816x_emac0_hwmod = { 881 .name = "emac0", 882 .clkdm_name = "alwon_ethernet_clkdm", 883 .class = &dm816x_emac_hwmod_class, 884 .flags = HWMOD_NO_IDLEST, 885 }; 886 887 static struct omap_hwmod_ocp_if dm81xx_l4_hs__emac0 = { 888 .master = &dm81xx_l4_hs_hwmod, 889 .slave = &dm816x_emac0_hwmod, 890 .clk = "sysclk5_ck", 891 .user = OCP_USER_MPU, 892 }; 893 894 static struct omap_hwmod_class dm81xx_mdio_hwmod_class = { 895 .name = "davinci_mdio", 896 .sysc = &dm816x_emac_sysc, 897 }; 898 899 static struct omap_hwmod dm81xx_emac0_mdio_hwmod = { 900 .name = "davinci_mdio", 901 .class = &dm81xx_mdio_hwmod_class, 902 .clkdm_name = "alwon_ethernet_clkdm", 903 .main_clk = "sysclk24_ck", 904 .flags = HWMOD_NO_IDLEST, 905 /* 906 * REVISIT: This should be moved to the emac0_hwmod 907 * once we have a better way to handle device slaves. 908 */ 909 .prcm = { 910 .omap4 = { 911 .clkctrl_offs = DM81XX_CM_ALWON_ETHERNET_0_CLKCTRL, 912 .modulemode = MODULEMODE_SWCTRL, 913 }, 914 }, 915 }; 916 917 static struct omap_hwmod_ocp_if dm81xx_emac0__mdio = { 918 .master = &dm81xx_l4_hs_hwmod, 919 .slave = &dm81xx_emac0_mdio_hwmod, 920 .user = OCP_USER_MPU, 921 }; 922 923 static struct omap_hwmod dm816x_emac1_hwmod = { 924 .name = "emac1", 925 .clkdm_name = "alwon_ethernet_clkdm", 926 .main_clk = "sysclk24_ck", 927 .flags = HWMOD_NO_IDLEST, 928 .prcm = { 929 .omap4 = { 930 .clkctrl_offs = DM816X_CM_ALWON_ETHERNET_1_CLKCTRL, 931 .modulemode = MODULEMODE_SWCTRL, 932 }, 933 }, 934 .class = &dm816x_emac_hwmod_class, 935 }; 936 937 static struct omap_hwmod_ocp_if dm816x_l4_hs__emac1 = { 938 .master = &dm81xx_l4_hs_hwmod, 939 .slave = &dm816x_emac1_hwmod, 940 .clk = "sysclk5_ck", 941 .user = OCP_USER_MPU, 942 }; 943 944 static struct omap_hwmod_class_sysconfig dm81xx_sata_sysc = { 945 .rev_offs = 0x00fc, 946 .sysc_offs = 0x1100, 947 .sysc_flags = SYSC_HAS_SIDLEMODE, 948 .idlemodes = SIDLE_FORCE, 949 .sysc_fields = &omap_hwmod_sysc_type3, 950 }; 951 952 static struct omap_hwmod_class dm81xx_sata_hwmod_class = { 953 .name = "sata", 954 .sysc = &dm81xx_sata_sysc, 955 }; 956 957 static struct omap_hwmod dm81xx_sata_hwmod = { 958 .name = "sata", 959 .clkdm_name = "default_clkdm", 960 .flags = HWMOD_NO_IDLEST, 961 .prcm = { 962 .omap4 = { 963 .clkctrl_offs = DM81XX_CM_DEFAULT_SATA_CLKCTRL, 964 .modulemode = MODULEMODE_SWCTRL, 965 }, 966 }, 967 .class = &dm81xx_sata_hwmod_class, 968 }; 969 970 static struct omap_hwmod_ocp_if dm81xx_l4_hs__sata = { 971 .master = &dm81xx_l4_hs_hwmod, 972 .slave = &dm81xx_sata_hwmod, 973 .clk = "sysclk5_ck", 974 .user = OCP_USER_MPU, 975 }; 976 977 static struct omap_hwmod_class_sysconfig dm81xx_mmc_sysc = { 978 .rev_offs = 0x0, 979 .sysc_offs = 0x110, 980 .syss_offs = 0x114, 981 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 982 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 983 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 984 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 985 .sysc_fields = &omap_hwmod_sysc_type1, 986 }; 987 988 static struct omap_hwmod_class dm81xx_mmc_class = { 989 .name = "mmc", 990 .sysc = &dm81xx_mmc_sysc, 991 }; 992 993 static struct omap_hwmod_opt_clk dm81xx_mmc_opt_clks[] = { 994 { .role = "dbck", .clk = "sysclk18_ck", }, 995 }; 996 997 static struct omap_hsmmc_dev_attr mmc_dev_attr = { 998 }; 999 1000 static struct omap_hwmod dm814x_mmc1_hwmod = { 1001 .name = "mmc1", 1002 .clkdm_name = "alwon_l3s_clkdm", 1003 .opt_clks = dm81xx_mmc_opt_clks, 1004 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1005 .main_clk = "sysclk8_ck", 1006 .prcm = { 1007 .omap4 = { 1008 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_0_CLKCTRL, 1009 .modulemode = MODULEMODE_SWCTRL, 1010 }, 1011 }, 1012 .dev_attr = &mmc_dev_attr, 1013 .class = &dm81xx_mmc_class, 1014 }; 1015 1016 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc1 = { 1017 .master = &dm81xx_l4_ls_hwmod, 1018 .slave = &dm814x_mmc1_hwmod, 1019 .clk = "sysclk6_ck", 1020 .user = OCP_USER_MPU, 1021 .flags = OMAP_FIREWALL_L4 1022 }; 1023 1024 static struct omap_hwmod dm814x_mmc2_hwmod = { 1025 .name = "mmc2", 1026 .clkdm_name = "alwon_l3s_clkdm", 1027 .opt_clks = dm81xx_mmc_opt_clks, 1028 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1029 .main_clk = "sysclk8_ck", 1030 .prcm = { 1031 .omap4 = { 1032 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_1_CLKCTRL, 1033 .modulemode = MODULEMODE_SWCTRL, 1034 }, 1035 }, 1036 .dev_attr = &mmc_dev_attr, 1037 .class = &dm81xx_mmc_class, 1038 }; 1039 1040 static struct omap_hwmod_ocp_if dm814x_l4_ls__mmc2 = { 1041 .master = &dm81xx_l4_ls_hwmod, 1042 .slave = &dm814x_mmc2_hwmod, 1043 .clk = "sysclk6_ck", 1044 .user = OCP_USER_MPU, 1045 .flags = OMAP_FIREWALL_L4 1046 }; 1047 1048 static struct omap_hwmod dm814x_mmc3_hwmod = { 1049 .name = "mmc3", 1050 .clkdm_name = "alwon_l3_med_clkdm", 1051 .opt_clks = dm81xx_mmc_opt_clks, 1052 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1053 .main_clk = "sysclk8_ck", 1054 .prcm = { 1055 .omap4 = { 1056 .clkctrl_offs = DM814X_CM_ALWON_MMCHS_2_CLKCTRL, 1057 .modulemode = MODULEMODE_SWCTRL, 1058 }, 1059 }, 1060 .dev_attr = &mmc_dev_attr, 1061 .class = &dm81xx_mmc_class, 1062 }; 1063 1064 static struct omap_hwmod_ocp_if dm814x_alwon_l3_med__mmc3 = { 1065 .master = &dm81xx_alwon_l3_med_hwmod, 1066 .slave = &dm814x_mmc3_hwmod, 1067 .clk = "sysclk4_ck", 1068 .user = OCP_USER_MPU, 1069 }; 1070 1071 static struct omap_hwmod dm816x_mmc1_hwmod = { 1072 .name = "mmc1", 1073 .clkdm_name = "alwon_l3s_clkdm", 1074 .opt_clks = dm81xx_mmc_opt_clks, 1075 .opt_clks_cnt = ARRAY_SIZE(dm81xx_mmc_opt_clks), 1076 .main_clk = "sysclk10_ck", 1077 .prcm = { 1078 .omap4 = { 1079 .clkctrl_offs = DM816X_CM_ALWON_SDIO_CLKCTRL, 1080 .modulemode = MODULEMODE_SWCTRL, 1081 }, 1082 }, 1083 .dev_attr = &mmc_dev_attr, 1084 .class = &dm81xx_mmc_class, 1085 }; 1086 1087 static struct omap_hwmod_ocp_if dm816x_l4_ls__mmc1 = { 1088 .master = &dm81xx_l4_ls_hwmod, 1089 .slave = &dm816x_mmc1_hwmod, 1090 .clk = "sysclk6_ck", 1091 .user = OCP_USER_MPU, 1092 .flags = OMAP_FIREWALL_L4 1093 }; 1094 1095 static struct omap_hwmod_class_sysconfig dm816x_mcspi_sysc = { 1096 .rev_offs = 0x0, 1097 .sysc_offs = 0x110, 1098 .syss_offs = 0x114, 1099 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1100 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 1101 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS, 1102 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1103 .sysc_fields = &omap_hwmod_sysc_type1, 1104 }; 1105 1106 static struct omap_hwmod_class dm816x_mcspi_class = { 1107 .name = "mcspi", 1108 .sysc = &dm816x_mcspi_sysc, 1109 }; 1110 1111 static struct omap_hwmod dm81xx_mcspi1_hwmod = { 1112 .name = "mcspi1", 1113 .clkdm_name = "alwon_l3s_clkdm", 1114 .main_clk = "sysclk10_ck", 1115 .prcm = { 1116 .omap4 = { 1117 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 1118 .modulemode = MODULEMODE_SWCTRL, 1119 }, 1120 }, 1121 .class = &dm816x_mcspi_class, 1122 }; 1123 1124 static struct omap_hwmod dm81xx_mcspi2_hwmod = { 1125 .name = "mcspi2", 1126 .clkdm_name = "alwon_l3s_clkdm", 1127 .main_clk = "sysclk10_ck", 1128 .prcm = { 1129 .omap4 = { 1130 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 1131 .modulemode = MODULEMODE_SWCTRL, 1132 }, 1133 }, 1134 .class = &dm816x_mcspi_class, 1135 }; 1136 1137 static struct omap_hwmod dm81xx_mcspi3_hwmod = { 1138 .name = "mcspi3", 1139 .clkdm_name = "alwon_l3s_clkdm", 1140 .main_clk = "sysclk10_ck", 1141 .prcm = { 1142 .omap4 = { 1143 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 1144 .modulemode = MODULEMODE_SWCTRL, 1145 }, 1146 }, 1147 .class = &dm816x_mcspi_class, 1148 }; 1149 1150 static struct omap_hwmod dm81xx_mcspi4_hwmod = { 1151 .name = "mcspi4", 1152 .clkdm_name = "alwon_l3s_clkdm", 1153 .main_clk = "sysclk10_ck", 1154 .prcm = { 1155 .omap4 = { 1156 .clkctrl_offs = DM81XX_CM_ALWON_SPI_CLKCTRL, 1157 .modulemode = MODULEMODE_SWCTRL, 1158 }, 1159 }, 1160 .class = &dm816x_mcspi_class, 1161 }; 1162 1163 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi1 = { 1164 .master = &dm81xx_l4_ls_hwmod, 1165 .slave = &dm81xx_mcspi1_hwmod, 1166 .clk = "sysclk6_ck", 1167 .user = OCP_USER_MPU, 1168 }; 1169 1170 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi2 = { 1171 .master = &dm81xx_l4_ls_hwmod, 1172 .slave = &dm81xx_mcspi2_hwmod, 1173 .clk = "sysclk6_ck", 1174 .user = OCP_USER_MPU, 1175 }; 1176 1177 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi3 = { 1178 .master = &dm81xx_l4_ls_hwmod, 1179 .slave = &dm81xx_mcspi3_hwmod, 1180 .clk = "sysclk6_ck", 1181 .user = OCP_USER_MPU, 1182 }; 1183 1184 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mcspi4 = { 1185 .master = &dm81xx_l4_ls_hwmod, 1186 .slave = &dm81xx_mcspi4_hwmod, 1187 .clk = "sysclk6_ck", 1188 .user = OCP_USER_MPU, 1189 }; 1190 1191 static struct omap_hwmod_class_sysconfig dm81xx_mailbox_sysc = { 1192 .rev_offs = 0x000, 1193 .sysc_offs = 0x010, 1194 .syss_offs = 0x014, 1195 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1196 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, 1197 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1198 .sysc_fields = &omap_hwmod_sysc_type1, 1199 }; 1200 1201 static struct omap_hwmod_class dm81xx_mailbox_hwmod_class = { 1202 .name = "mailbox", 1203 .sysc = &dm81xx_mailbox_sysc, 1204 }; 1205 1206 static struct omap_hwmod dm81xx_mailbox_hwmod = { 1207 .name = "mailbox", 1208 .clkdm_name = "alwon_l3s_clkdm", 1209 .class = &dm81xx_mailbox_hwmod_class, 1210 .main_clk = "sysclk6_ck", 1211 .prcm = { 1212 .omap4 = { 1213 .clkctrl_offs = DM81XX_CM_ALWON_MAILBOX_CLKCTRL, 1214 .modulemode = MODULEMODE_SWCTRL, 1215 }, 1216 }, 1217 }; 1218 1219 static struct omap_hwmod_ocp_if dm81xx_l4_ls__mailbox = { 1220 .master = &dm81xx_l4_ls_hwmod, 1221 .slave = &dm81xx_mailbox_hwmod, 1222 .clk = "sysclk6_ck", 1223 .user = OCP_USER_MPU, 1224 }; 1225 1226 static struct omap_hwmod_class_sysconfig dm81xx_spinbox_sysc = { 1227 .rev_offs = 0x000, 1228 .sysc_offs = 0x010, 1229 .syss_offs = 0x014, 1230 .sysc_flags = SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | 1231 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE, 1232 .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART, 1233 .sysc_fields = &omap_hwmod_sysc_type1, 1234 }; 1235 1236 static struct omap_hwmod_class dm81xx_spinbox_hwmod_class = { 1237 .name = "spinbox", 1238 .sysc = &dm81xx_spinbox_sysc, 1239 }; 1240 1241 static struct omap_hwmod dm81xx_spinbox_hwmod = { 1242 .name = "spinbox", 1243 .clkdm_name = "alwon_l3s_clkdm", 1244 .class = &dm81xx_spinbox_hwmod_class, 1245 .main_clk = "sysclk6_ck", 1246 .prcm = { 1247 .omap4 = { 1248 .clkctrl_offs = DM81XX_CM_ALWON_SPINBOX_CLKCTRL, 1249 .modulemode = MODULEMODE_SWCTRL, 1250 }, 1251 }, 1252 }; 1253 1254 static struct omap_hwmod_ocp_if dm81xx_l4_ls__spinbox = { 1255 .master = &dm81xx_l4_ls_hwmod, 1256 .slave = &dm81xx_spinbox_hwmod, 1257 .clk = "sysclk6_ck", 1258 .user = OCP_USER_MPU, 1259 }; 1260 1261 /* 1262 * REVISIT: Test and enable the following once clocks work: 1263 * dm81xx_l4_ls__mailbox 1264 * 1265 * Also note that some devices share a single clkctrl_offs.. 1266 * For example, i2c1 and 3 share one, and i2c2 and 4 share one. 1267 */ 1268 static struct omap_hwmod_ocp_if *dm814x_hwmod_ocp_ifs[] __initdata = { 1269 &dm814x_mpu__alwon_l3_slow, 1270 &dm814x_mpu__alwon_l3_med, 1271 &dm81xx_alwon_l3_slow__l4_ls, 1272 &dm81xx_alwon_l3_slow__l4_hs, 1273 &dm81xx_l4_ls__uart1, 1274 &dm81xx_l4_ls__uart2, 1275 &dm81xx_l4_ls__uart3, 1276 &dm81xx_l4_ls__wd_timer1, 1277 &dm81xx_l4_ls__i2c1, 1278 &dm81xx_l4_ls__i2c2, 1279 &dm81xx_l4_ls__gpio1, 1280 &dm81xx_l4_ls__gpio2, 1281 &dm81xx_l4_ls__gpio3, 1282 &dm81xx_l4_ls__gpio4, 1283 &dm81xx_l4_ls__elm, 1284 &dm81xx_l4_ls__mcspi1, 1285 &dm81xx_l4_ls__mcspi2, 1286 &dm81xx_l4_ls__mcspi3, 1287 &dm81xx_l4_ls__mcspi4, 1288 &dm814x_l4_ls__mmc1, 1289 &dm814x_l4_ls__mmc2, 1290 &ti81xx_l4_ls__rtc, 1291 &dm814x_l4_ls__timer1, 1292 &dm814x_l4_ls__timer2, 1293 &dm81xx_alwon_l3_slow__gpmc, 1294 &dm814x_default_l3_slow__usbss, 1295 &dm814x_alwon_l3_med__mmc3, 1296 NULL, 1297 }; 1298 1299 int __init dm814x_hwmod_init(void) 1300 { 1301 omap_hwmod_init(); 1302 return omap_hwmod_register_links(dm814x_hwmod_ocp_ifs); 1303 } 1304 1305 static struct omap_hwmod_ocp_if *dm816x_hwmod_ocp_ifs[] __initdata = { 1306 &dm816x_mpu__alwon_l3_slow, 1307 &dm816x_mpu__alwon_l3_med, 1308 &dm81xx_alwon_l3_slow__l4_ls, 1309 &dm81xx_alwon_l3_slow__l4_hs, 1310 &dm81xx_l4_ls__uart1, 1311 &dm81xx_l4_ls__uart2, 1312 &dm81xx_l4_ls__uart3, 1313 &dm81xx_l4_ls__wd_timer1, 1314 &dm81xx_l4_ls__i2c1, 1315 &dm81xx_l4_ls__i2c2, 1316 &dm81xx_l4_ls__gpio1, 1317 &dm81xx_l4_ls__gpio2, 1318 &dm81xx_l4_ls__elm, 1319 &ti81xx_l4_ls__rtc, 1320 &dm816x_l4_ls__mmc1, 1321 &dm816x_l4_ls__timer1, 1322 &dm816x_l4_ls__timer2, 1323 &dm816x_l4_ls__timer3, 1324 &dm816x_l4_ls__timer4, 1325 &dm816x_l4_ls__timer5, 1326 &dm816x_l4_ls__timer6, 1327 &dm816x_l4_ls__timer7, 1328 &dm81xx_l4_ls__mcspi1, 1329 &dm81xx_l4_ls__mailbox, 1330 &dm81xx_l4_ls__spinbox, 1331 &dm81xx_l4_hs__emac0, 1332 &dm81xx_emac0__mdio, 1333 &dm816x_l4_hs__emac1, 1334 &dm81xx_l4_hs__sata, 1335 &dm81xx_alwon_l3_slow__gpmc, 1336 &dm816x_default_l3_slow__usbss, 1337 NULL, 1338 }; 1339 1340 int __init dm816x_hwmod_init(void) 1341 { 1342 omap_hwmod_init(); 1343 return omap_hwmod_register_links(dm816x_hwmod_ocp_ifs); 1344 } 1345