1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 #ifndef ATH11K_HAL_DESC_H 6 #define ATH11K_HAL_DESC_H 7 8 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0) 9 10 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0) 11 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8) 12 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11) 13 14 struct ath11k_buffer_addr { 15 u32 info0; 16 u32 info1; 17 } __packed; 18 19 /* ath11k_buffer_addr 20 * 21 * info0 22 * Address (lower 32 bits) of the msdu buffer or msdu extension 23 * descriptor or Link descriptor 24 * 25 * addr 26 * Address (upper 8 bits) of the msdu buffer or msdu extension 27 * descriptor or Link descriptor 28 * 29 * return_buffer_manager (RBM) 30 * Consumer: WBM 31 * Producer: SW/FW 32 * Indicates to which buffer manager the buffer or MSDU_EXTENSION 33 * descriptor or link descriptor that is being pointed to shall be 34 * returned after the frame has been processed. It is used by WBM 35 * for routing purposes. 36 * 37 * Values are defined in enum %HAL_RX_BUF_RBM_ 38 * 39 * sw_buffer_cookie 40 * Cookie field exclusively used by SW. HW ignores the contents, 41 * accept that it passes the programmed value on to other 42 * descriptors together with the physical address. 43 * 44 * Field can be used by SW to for example associate the buffers 45 * physical address with the virtual address. 46 */ 47 48 enum hal_tlv_tag { 49 HAL_MACTX_CBF_START = 0 /* 0x0 */, 50 HAL_PHYRX_DATA = 1 /* 0x1 */, 51 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */, 52 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */, 53 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */, 54 HAL_MACTX_DATA_RESP = 5 /* 0x5 */, 55 HAL_MACTX_CBF_DATA = 6 /* 0x6 */, 56 HAL_MACTX_CBF_DONE = 7 /* 0x7 */, 57 HAL_MACRX_CBF_READ_REQUEST = 8 /* 0x8 */, 58 HAL_MACRX_CBF_DATA_REQUEST = 9 /* 0x9 */, 59 HAL_MACRX_EXPECT_NDP_RECEPTION = 10 /* 0xa */, 60 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 11 /* 0xb */, 61 HAL_MACRX_NDP_TIMEOUT = 12 /* 0xc */, 62 HAL_MACRX_ABORT_ACK = 13 /* 0xd */, 63 HAL_MACRX_REQ_IMPLICIT_FB = 14 /* 0xe */, 64 HAL_MACRX_CHAIN_MASK = 15 /* 0xf */, 65 HAL_MACRX_NAP_USER = 16 /* 0x10 */, 66 HAL_MACRX_ABORT_REQUEST = 17 /* 0x11 */, 67 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 18 /* 0x12 */, 68 HAL_PHYTX_ABORT_ACK = 19 /* 0x13 */, 69 HAL_PHYTX_ABORT_REQUEST = 20 /* 0x14 */, 70 HAL_PHYTX_PKT_END = 21 /* 0x15 */, 71 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 22 /* 0x16 */, 72 HAL_PHYTX_REQUEST_CTRL_INFO = 23 /* 0x17 */, 73 HAL_PHYTX_DATA_REQUEST = 24 /* 0x18 */, 74 HAL_PHYTX_BF_CV_LOADING_DONE = 25 /* 0x19 */, 75 HAL_PHYTX_NAP_ACK = 26 /* 0x1a */, 76 HAL_PHYTX_NAP_DONE = 27 /* 0x1b */, 77 HAL_PHYTX_OFF_ACK = 28 /* 0x1c */, 78 HAL_PHYTX_ON_ACK = 29 /* 0x1d */, 79 HAL_PHYTX_SYNTH_OFF_ACK = 30 /* 0x1e */, 80 HAL_PHYTX_DEBUG16 = 31 /* 0x1f */, 81 HAL_MACTX_ABORT_REQUEST = 32 /* 0x20 */, 82 HAL_MACTX_ABORT_ACK = 33 /* 0x21 */, 83 HAL_MACTX_PKT_END = 34 /* 0x22 */, 84 HAL_MACTX_PRE_PHY_DESC = 35 /* 0x23 */, 85 HAL_MACTX_BF_PARAMS_COMMON = 36 /* 0x24 */, 86 HAL_MACTX_BF_PARAMS_PER_USER = 37 /* 0x25 */, 87 HAL_MACTX_PREFETCH_CV = 38 /* 0x26 */, 88 HAL_MACTX_USER_DESC_COMMON = 39 /* 0x27 */, 89 HAL_MACTX_USER_DESC_PER_USER = 40 /* 0x28 */, 90 HAL_EXAMPLE_USER_TLV_16 = 41 /* 0x29 */, 91 HAL_EXAMPLE_TLV_16 = 42 /* 0x2a */, 92 HAL_MACTX_PHY_OFF = 43 /* 0x2b */, 93 HAL_MACTX_PHY_ON = 44 /* 0x2c */, 94 HAL_MACTX_SYNTH_OFF = 45 /* 0x2d */, 95 HAL_MACTX_EXPECT_CBF_COMMON = 46 /* 0x2e */, 96 HAL_MACTX_EXPECT_CBF_PER_USER = 47 /* 0x2f */, 97 HAL_MACTX_PHY_DESC = 48 /* 0x30 */, 98 HAL_MACTX_L_SIG_A = 49 /* 0x31 */, 99 HAL_MACTX_L_SIG_B = 50 /* 0x32 */, 100 HAL_MACTX_HT_SIG = 51 /* 0x33 */, 101 HAL_MACTX_VHT_SIG_A = 52 /* 0x34 */, 102 HAL_MACTX_VHT_SIG_B_SU20 = 53 /* 0x35 */, 103 HAL_MACTX_VHT_SIG_B_SU40 = 54 /* 0x36 */, 104 HAL_MACTX_VHT_SIG_B_SU80 = 55 /* 0x37 */, 105 HAL_MACTX_VHT_SIG_B_SU160 = 56 /* 0x38 */, 106 HAL_MACTX_VHT_SIG_B_MU20 = 57 /* 0x39 */, 107 HAL_MACTX_VHT_SIG_B_MU40 = 58 /* 0x3a */, 108 HAL_MACTX_VHT_SIG_B_MU80 = 59 /* 0x3b */, 109 HAL_MACTX_VHT_SIG_B_MU160 = 60 /* 0x3c */, 110 HAL_MACTX_SERVICE = 61 /* 0x3d */, 111 HAL_MACTX_HE_SIG_A_SU = 62 /* 0x3e */, 112 HAL_MACTX_HE_SIG_A_MU_DL = 63 /* 0x3f */, 113 HAL_MACTX_HE_SIG_A_MU_UL = 64 /* 0x40 */, 114 HAL_MACTX_HE_SIG_B1_MU = 65 /* 0x41 */, 115 HAL_MACTX_HE_SIG_B2_MU = 66 /* 0x42 */, 116 HAL_MACTX_HE_SIG_B2_OFDMA = 67 /* 0x43 */, 117 HAL_MACTX_DELETE_CV = 68 /* 0x44 */, 118 HAL_MACTX_MU_UPLINK_COMMON = 69 /* 0x45 */, 119 HAL_MACTX_MU_UPLINK_USER_SETUP = 70 /* 0x46 */, 120 HAL_MACTX_OTHER_TRANSMIT_INFO = 71 /* 0x47 */, 121 HAL_MACTX_PHY_NAP = 72 /* 0x48 */, 122 HAL_MACTX_DEBUG = 73 /* 0x49 */, 123 HAL_PHYRX_ABORT_ACK = 74 /* 0x4a */, 124 HAL_PHYRX_GENERATED_CBF_DETAILS = 75 /* 0x4b */, 125 HAL_PHYRX_RSSI_LEGACY = 76 /* 0x4c */, 126 HAL_PHYRX_RSSI_HT = 77 /* 0x4d */, 127 HAL_PHYRX_USER_INFO = 78 /* 0x4e */, 128 HAL_PHYRX_PKT_END = 79 /* 0x4f */, 129 HAL_PHYRX_DEBUG = 80 /* 0x50 */, 130 HAL_PHYRX_CBF_TRANSFER_DONE = 81 /* 0x51 */, 131 HAL_PHYRX_CBF_TRANSFER_ABORT = 82 /* 0x52 */, 132 HAL_PHYRX_L_SIG_A = 83 /* 0x53 */, 133 HAL_PHYRX_L_SIG_B = 84 /* 0x54 */, 134 HAL_PHYRX_HT_SIG = 85 /* 0x55 */, 135 HAL_PHYRX_VHT_SIG_A = 86 /* 0x56 */, 136 HAL_PHYRX_VHT_SIG_B_SU20 = 87 /* 0x57 */, 137 HAL_PHYRX_VHT_SIG_B_SU40 = 88 /* 0x58 */, 138 HAL_PHYRX_VHT_SIG_B_SU80 = 89 /* 0x59 */, 139 HAL_PHYRX_VHT_SIG_B_SU160 = 90 /* 0x5a */, 140 HAL_PHYRX_VHT_SIG_B_MU20 = 91 /* 0x5b */, 141 HAL_PHYRX_VHT_SIG_B_MU40 = 92 /* 0x5c */, 142 HAL_PHYRX_VHT_SIG_B_MU80 = 93 /* 0x5d */, 143 HAL_PHYRX_VHT_SIG_B_MU160 = 94 /* 0x5e */, 144 HAL_PHYRX_HE_SIG_A_SU = 95 /* 0x5f */, 145 HAL_PHYRX_HE_SIG_A_MU_DL = 96 /* 0x60 */, 146 HAL_PHYRX_HE_SIG_A_MU_UL = 97 /* 0x61 */, 147 HAL_PHYRX_HE_SIG_B1_MU = 98 /* 0x62 */, 148 HAL_PHYRX_HE_SIG_B2_MU = 99 /* 0x63 */, 149 HAL_PHYRX_HE_SIG_B2_OFDMA = 100 /* 0x64 */, 150 HAL_PHYRX_OTHER_RECEIVE_INFO = 101 /* 0x65 */, 151 HAL_PHYRX_COMMON_USER_INFO = 102 /* 0x66 */, 152 HAL_PHYRX_DATA_DONE = 103 /* 0x67 */, 153 HAL_RECEIVE_RSSI_INFO = 104 /* 0x68 */, 154 HAL_RECEIVE_USER_INFO = 105 /* 0x69 */, 155 HAL_MIMO_CONTROL_INFO = 106 /* 0x6a */, 156 HAL_RX_LOCATION_INFO = 107 /* 0x6b */, 157 HAL_COEX_TX_REQ = 108 /* 0x6c */, 158 HAL_DUMMY = 109 /* 0x6d */, 159 HAL_RX_TIMING_OFFSET_INFO = 110 /* 0x6e */, 160 HAL_EXAMPLE_TLV_32_NAME = 111 /* 0x6f */, 161 HAL_MPDU_LIMIT = 112 /* 0x70 */, 162 HAL_NA_LENGTH_END = 113 /* 0x71 */, 163 HAL_OLE_BUF_STATUS = 114 /* 0x72 */, 164 HAL_PCU_PPDU_SETUP_DONE = 115 /* 0x73 */, 165 HAL_PCU_PPDU_SETUP_END = 116 /* 0x74 */, 166 HAL_PCU_PPDU_SETUP_INIT = 117 /* 0x75 */, 167 HAL_PCU_PPDU_SETUP_START = 118 /* 0x76 */, 168 HAL_PDG_FES_SETUP = 119 /* 0x77 */, 169 HAL_PDG_RESPONSE = 120 /* 0x78 */, 170 HAL_PDG_TX_REQ = 121 /* 0x79 */, 171 HAL_SCH_WAIT_INSTR = 122 /* 0x7a */, 172 HAL_SCHEDULER_TLV = 123 /* 0x7b */, 173 HAL_TQM_FLOW_EMPTY_STATUS = 124 /* 0x7c */, 174 HAL_TQM_FLOW_NOT_EMPTY_STATUS = 125 /* 0x7d */, 175 HAL_TQM_GEN_MPDU_LENGTH_LIST = 126 /* 0x7e */, 176 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 127 /* 0x7f */, 177 HAL_TQM_GEN_MPDUS = 128 /* 0x80 */, 178 HAL_TQM_GEN_MPDUS_STATUS = 129 /* 0x81 */, 179 HAL_TQM_REMOVE_MPDU = 130 /* 0x82 */, 180 HAL_TQM_REMOVE_MPDU_STATUS = 131 /* 0x83 */, 181 HAL_TQM_REMOVE_MSDU = 132 /* 0x84 */, 182 HAL_TQM_REMOVE_MSDU_STATUS = 133 /* 0x85 */, 183 HAL_TQM_UPDATE_TX_MPDU_COUNT = 134 /* 0x86 */, 184 HAL_TQM_WRITE_CMD = 135 /* 0x87 */, 185 HAL_OFDMA_TRIGGER_DETAILS = 136 /* 0x88 */, 186 HAL_TX_DATA = 137 /* 0x89 */, 187 HAL_TX_FES_SETUP = 138 /* 0x8a */, 188 HAL_RX_PACKET = 139 /* 0x8b */, 189 HAL_EXPECTED_RESPONSE = 140 /* 0x8c */, 190 HAL_TX_MPDU_END = 141 /* 0x8d */, 191 HAL_TX_MPDU_START = 142 /* 0x8e */, 192 HAL_TX_MSDU_END = 143 /* 0x8f */, 193 HAL_TX_MSDU_START = 144 /* 0x90 */, 194 HAL_TX_SW_MODE_SETUP = 145 /* 0x91 */, 195 HAL_TXPCU_BUFFER_STATUS = 146 /* 0x92 */, 196 HAL_TXPCU_USER_BUFFER_STATUS = 147 /* 0x93 */, 197 HAL_DATA_TO_TIME_CONFIG = 148 /* 0x94 */, 198 HAL_EXAMPLE_USER_TLV_32 = 149 /* 0x95 */, 199 HAL_MPDU_INFO = 150 /* 0x96 */, 200 HAL_PDG_USER_SETUP = 151 /* 0x97 */, 201 HAL_TX_11AH_SETUP = 152 /* 0x98 */, 202 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 153 /* 0x99 */, 203 HAL_TX_PEER_ENTRY = 154 /* 0x9a */, 204 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 155 /* 0x9b */, 205 HAL_EXAMPLE_STRUCT_NAME = 156 /* 0x9c */, 206 HAL_PCU_PPDU_SETUP_END_INFO = 157 /* 0x9d */, 207 HAL_PPDU_RATE_SETTING = 158 /* 0x9e */, 208 HAL_PROT_RATE_SETTING = 159 /* 0x9f */, 209 HAL_RX_MPDU_DETAILS = 160 /* 0xa0 */, 210 HAL_EXAMPLE_USER_TLV_42 = 161 /* 0xa1 */, 211 HAL_RX_MSDU_LINK = 162 /* 0xa2 */, 212 HAL_RX_REO_QUEUE = 163 /* 0xa3 */, 213 HAL_ADDR_SEARCH_ENTRY = 164 /* 0xa4 */, 214 HAL_SCHEDULER_CMD = 165 /* 0xa5 */, 215 HAL_TX_FLUSH = 166 /* 0xa6 */, 216 HAL_TQM_ENTRANCE_RING = 167 /* 0xa7 */, 217 HAL_TX_DATA_WORD = 168 /* 0xa8 */, 218 HAL_TX_MPDU_DETAILS = 169 /* 0xa9 */, 219 HAL_TX_MPDU_LINK = 170 /* 0xaa */, 220 HAL_TX_MPDU_LINK_PTR = 171 /* 0xab */, 221 HAL_TX_MPDU_QUEUE_HEAD = 172 /* 0xac */, 222 HAL_TX_MPDU_QUEUE_EXT = 173 /* 0xad */, 223 HAL_TX_MPDU_QUEUE_EXT_PTR = 174 /* 0xae */, 224 HAL_TX_MSDU_DETAILS = 175 /* 0xaf */, 225 HAL_TX_MSDU_EXTENSION = 176 /* 0xb0 */, 226 HAL_TX_MSDU_FLOW = 177 /* 0xb1 */, 227 HAL_TX_MSDU_LINK = 178 /* 0xb2 */, 228 HAL_TX_MSDU_LINK_ENTRY_PTR = 179 /* 0xb3 */, 229 HAL_RESPONSE_RATE_SETTING = 180 /* 0xb4 */, 230 HAL_TXPCU_BUFFER_BASICS = 181 /* 0xb5 */, 231 HAL_UNIFORM_DESCRIPTOR_HEADER = 182 /* 0xb6 */, 232 HAL_UNIFORM_TQM_CMD_HEADER = 183 /* 0xb7 */, 233 HAL_UNIFORM_TQM_STATUS_HEADER = 184 /* 0xb8 */, 234 HAL_USER_RATE_SETTING = 185 /* 0xb9 */, 235 HAL_WBM_BUFFER_RING = 186 /* 0xba */, 236 HAL_WBM_LINK_DESCRIPTOR_RING = 187 /* 0xbb */, 237 HAL_WBM_RELEASE_RING = 188 /* 0xbc */, 238 HAL_TX_FLUSH_REQ = 189 /* 0xbd */, 239 HAL_RX_MSDU_DETAILS = 190 /* 0xbe */, 240 HAL_TQM_WRITE_CMD_STATUS = 191 /* 0xbf */, 241 HAL_TQM_GET_MPDU_QUEUE_STATS = 192 /* 0xc0 */, 242 HAL_TQM_GET_MSDU_FLOW_STATS = 193 /* 0xc1 */, 243 HAL_EXAMPLE_USER_CTLV_32 = 194 /* 0xc2 */, 244 HAL_TX_FES_STATUS_START = 195 /* 0xc3 */, 245 HAL_TX_FES_STATUS_USER_PPDU = 196 /* 0xc4 */, 246 HAL_TX_FES_STATUS_USER_RESPONSE = 197 /* 0xc5 */, 247 HAL_TX_FES_STATUS_END = 198 /* 0xc6 */, 248 HAL_RX_TRIG_INFO = 199 /* 0xc7 */, 249 HAL_RXPCU_TX_SETUP_CLEAR = 200 /* 0xc8 */, 250 HAL_RX_FRAME_BITMAP_REQ = 201 /* 0xc9 */, 251 HAL_RX_FRAME_BITMAP_ACK = 202 /* 0xca */, 252 HAL_COEX_RX_STATUS = 203 /* 0xcb */, 253 HAL_RX_START_PARAM = 204 /* 0xcc */, 254 HAL_RX_PPDU_START = 205 /* 0xcd */, 255 HAL_RX_PPDU_END = 206 /* 0xce */, 256 HAL_RX_MPDU_START = 207 /* 0xcf */, 257 HAL_RX_MPDU_END = 208 /* 0xd0 */, 258 HAL_RX_MSDU_START = 209 /* 0xd1 */, 259 HAL_RX_MSDU_END = 210 /* 0xd2 */, 260 HAL_RX_ATTENTION = 211 /* 0xd3 */, 261 HAL_RECEIVED_RESPONSE_INFO = 212 /* 0xd4 */, 262 HAL_RX_PHY_SLEEP = 213 /* 0xd5 */, 263 HAL_RX_HEADER = 214 /* 0xd6 */, 264 HAL_RX_PEER_ENTRY = 215 /* 0xd7 */, 265 HAL_RX_FLUSH = 216 /* 0xd8 */, 266 HAL_RX_RESPONSE_REQUIRED_INFO = 217 /* 0xd9 */, 267 HAL_RX_FRAMELESS_BAR_DETAILS = 218 /* 0xda */, 268 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 219 /* 0xdb */, 269 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 220 /* 0xdc */, 270 HAL_TX_CBF_INFO = 221 /* 0xdd */, 271 HAL_PCU_PPDU_SETUP_USER = 222 /* 0xde */, 272 HAL_RX_MPDU_PCU_START = 223 /* 0xdf */, 273 HAL_RX_PM_INFO = 224 /* 0xe0 */, 274 HAL_RX_USER_PPDU_END = 225 /* 0xe1 */, 275 HAL_RX_PRE_PPDU_START = 226 /* 0xe2 */, 276 HAL_RX_PREAMBLE = 227 /* 0xe3 */, 277 HAL_TX_FES_SETUP_COMPLETE = 228 /* 0xe4 */, 278 HAL_TX_LAST_MPDU_FETCHED = 229 /* 0xe5 */, 279 HAL_TXDMA_STOP_REQUEST = 230 /* 0xe6 */, 280 HAL_RXPCU_SETUP = 231 /* 0xe7 */, 281 HAL_RXPCU_USER_SETUP = 232 /* 0xe8 */, 282 HAL_TX_FES_STATUS_ACK_OR_BA = 233 /* 0xe9 */, 283 HAL_TQM_ACKED_MPDU = 234 /* 0xea */, 284 HAL_COEX_TX_RESP = 235 /* 0xeb */, 285 HAL_COEX_TX_STATUS = 236 /* 0xec */, 286 HAL_MACTX_COEX_PHY_CTRL = 237 /* 0xed */, 287 HAL_COEX_STATUS_BROADCAST = 238 /* 0xee */, 288 HAL_RESPONSE_START_STATUS = 239 /* 0xef */, 289 HAL_RESPONSE_END_STATUS = 240 /* 0xf0 */, 290 HAL_CRYPTO_STATUS = 241 /* 0xf1 */, 291 HAL_RECEIVED_TRIGGER_INFO = 242 /* 0xf2 */, 292 HAL_REO_ENTRANCE_RING = 243 /* 0xf3 */, 293 HAL_RX_MPDU_LINK = 244 /* 0xf4 */, 294 HAL_COEX_TX_STOP_CTRL = 245 /* 0xf5 */, 295 HAL_RX_PPDU_ACK_REPORT = 246 /* 0xf6 */, 296 HAL_RX_PPDU_NO_ACK_REPORT = 247 /* 0xf7 */, 297 HAL_SCH_COEX_STATUS = 248 /* 0xf8 */, 298 HAL_SCHEDULER_COMMAND_STATUS = 249 /* 0xf9 */, 299 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 250 /* 0xfa */, 300 HAL_TX_FES_STATUS_PROT = 251 /* 0xfb */, 301 HAL_TX_FES_STATUS_START_PPDU = 252 /* 0xfc */, 302 HAL_TX_FES_STATUS_START_PROT = 253 /* 0xfd */, 303 HAL_TXPCU_PHYTX_DEBUG32 = 254 /* 0xfe */, 304 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 255 /* 0xff */, 305 HAL_TX_MPDU_COUNT_TRANSFER_END = 256 /* 0x100 */, 306 HAL_WHO_ANCHOR_OFFSET = 257 /* 0x101 */, 307 HAL_WHO_ANCHOR_VALUE = 258 /* 0x102 */, 308 HAL_WHO_CCE_INFO = 259 /* 0x103 */, 309 HAL_WHO_COMMIT = 260 /* 0x104 */, 310 HAL_WHO_COMMIT_DONE = 261 /* 0x105 */, 311 HAL_WHO_FLUSH = 262 /* 0x106 */, 312 HAL_WHO_L2_LLC = 263 /* 0x107 */, 313 HAL_WHO_L2_PAYLOAD = 264 /* 0x108 */, 314 HAL_WHO_L3_CHECKSUM = 265 /* 0x109 */, 315 HAL_WHO_L3_INFO = 266 /* 0x10a */, 316 HAL_WHO_L4_CHECKSUM = 267 /* 0x10b */, 317 HAL_WHO_L4_INFO = 268 /* 0x10c */, 318 HAL_WHO_MSDU = 269 /* 0x10d */, 319 HAL_WHO_MSDU_MISC = 270 /* 0x10e */, 320 HAL_WHO_PACKET_DATA = 271 /* 0x10f */, 321 HAL_WHO_PACKET_HDR = 272 /* 0x110 */, 322 HAL_WHO_PPDU_END = 273 /* 0x111 */, 323 HAL_WHO_PPDU_START = 274 /* 0x112 */, 324 HAL_WHO_TSO = 275 /* 0x113 */, 325 HAL_WHO_WMAC_HEADER_PV0 = 276 /* 0x114 */, 326 HAL_WHO_WMAC_HEADER_PV1 = 277 /* 0x115 */, 327 HAL_WHO_WMAC_IV = 278 /* 0x116 */, 328 HAL_MPDU_INFO_END = 279 /* 0x117 */, 329 HAL_MPDU_INFO_BITMAP = 280 /* 0x118 */, 330 HAL_TX_QUEUE_EXTENSION = 281 /* 0x119 */, 331 HAL_RX_PEER_ENTRY_DETAILS = 282 /* 0x11a */, 332 HAL_RX_REO_QUEUE_REFERENCE = 283 /* 0x11b */, 333 HAL_RX_REO_QUEUE_EXT = 284 /* 0x11c */, 334 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 285 /* 0x11d */, 335 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 286 /* 0x11e */, 336 HAL_TQM_ACKED_MPDU_STATUS = 287 /* 0x11f */, 337 HAL_TQM_ADD_MSDU_STATUS = 288 /* 0x120 */, 338 HAL_RX_MPDU_LINK_PTR = 289 /* 0x121 */, 339 HAL_REO_DESTINATION_RING = 290 /* 0x122 */, 340 HAL_TQM_LIST_GEN_DONE = 291 /* 0x123 */, 341 HAL_WHO_TERMINATE = 292 /* 0x124 */, 342 HAL_TX_LAST_MPDU_END = 293 /* 0x125 */, 343 HAL_TX_CV_DATA = 294 /* 0x126 */, 344 HAL_TCL_ENTRANCE_FROM_PPE_RING = 295 /* 0x127 */, 345 HAL_PPDU_TX_END = 296 /* 0x128 */, 346 HAL_PROT_TX_END = 297 /* 0x129 */, 347 HAL_PDG_RESPONSE_RATE_SETTING = 298 /* 0x12a */, 348 HAL_MPDU_INFO_GLOBAL_END = 299 /* 0x12b */, 349 HAL_TQM_SCH_INSTR_GLOBAL_END = 300 /* 0x12c */, 350 HAL_RX_PPDU_END_USER_STATS = 301 /* 0x12d */, 351 HAL_RX_PPDU_END_USER_STATS_EXT = 302 /* 0x12e */, 352 HAL_NO_ACK_REPORT = 303 /* 0x12f */, 353 HAL_ACK_REPORT = 304 /* 0x130 */, 354 HAL_UNIFORM_REO_CMD_HEADER = 305 /* 0x131 */, 355 HAL_REO_GET_QUEUE_STATS = 306 /* 0x132 */, 356 HAL_REO_FLUSH_QUEUE = 307 /* 0x133 */, 357 HAL_REO_FLUSH_CACHE = 308 /* 0x134 */, 358 HAL_REO_UNBLOCK_CACHE = 309 /* 0x135 */, 359 HAL_UNIFORM_REO_STATUS_HEADER = 310 /* 0x136 */, 360 HAL_REO_GET_QUEUE_STATS_STATUS = 311 /* 0x137 */, 361 HAL_REO_FLUSH_QUEUE_STATUS = 312 /* 0x138 */, 362 HAL_REO_FLUSH_CACHE_STATUS = 313 /* 0x139 */, 363 HAL_REO_UNBLOCK_CACHE_STATUS = 314 /* 0x13a */, 364 HAL_TQM_FLUSH_CACHE = 315 /* 0x13b */, 365 HAL_TQM_UNBLOCK_CACHE = 316 /* 0x13c */, 366 HAL_TQM_FLUSH_CACHE_STATUS = 317 /* 0x13d */, 367 HAL_TQM_UNBLOCK_CACHE_STATUS = 318 /* 0x13e */, 368 HAL_RX_PPDU_END_STATUS_DONE = 319 /* 0x13f */, 369 HAL_RX_STATUS_BUFFER_DONE = 320 /* 0x140 */, 370 HAL_BUFFER_ADDR_INFO = 321 /* 0x141 */, 371 HAL_RX_MSDU_DESC_INFO = 322 /* 0x142 */, 372 HAL_RX_MPDU_DESC_INFO = 323 /* 0x143 */, 373 HAL_TCL_DATA_CMD = 324 /* 0x144 */, 374 HAL_TCL_GSE_CMD = 325 /* 0x145 */, 375 HAL_TCL_EXIT_BASE = 326 /* 0x146 */, 376 HAL_TCL_COMPACT_EXIT_RING = 327 /* 0x147 */, 377 HAL_TCL_REGULAR_EXIT_RING = 328 /* 0x148 */, 378 HAL_TCL_EXTENDED_EXIT_RING = 329 /* 0x149 */, 379 HAL_UPLINK_COMMON_INFO = 330 /* 0x14a */, 380 HAL_UPLINK_USER_SETUP_INFO = 331 /* 0x14b */, 381 HAL_TX_DATA_SYNC = 332 /* 0x14c */, 382 HAL_PHYRX_CBF_READ_REQUEST_ACK = 333 /* 0x14d */, 383 HAL_TCL_STATUS_RING = 334 /* 0x14e */, 384 HAL_TQM_GET_MPDU_HEAD_INFO = 335 /* 0x14f */, 385 HAL_TQM_SYNC_CMD = 336 /* 0x150 */, 386 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 337 /* 0x151 */, 387 HAL_TQM_SYNC_CMD_STATUS = 338 /* 0x152 */, 388 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 339 /* 0x153 */, 389 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 340 /* 0x154 */, 390 HAL_REO_FLUSH_TIMEOUT_LIST = 341 /* 0x155 */, 391 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 342 /* 0x156 */, 392 HAL_REO_TO_PPE_RING = 343 /* 0x157 */, 393 HAL_RX_MPDU_INFO = 344 /* 0x158 */, 394 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 345 /* 0x159 */, 395 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 346 /* 0x15a */, 396 HAL_EXAMPLE_USER_TLV_32_NAME = 347 /* 0x15b */, 397 HAL_RX_PPDU_START_USER_INFO = 348 /* 0x15c */, 398 HAL_RX_RXPCU_CLASSIFICATION_OVERVIEW = 349 /* 0x15d */, 399 HAL_RX_RING_MASK = 350 /* 0x15e */, 400 HAL_WHO_CLASSIFY_INFO = 351 /* 0x15f */, 401 HAL_TXPT_CLASSIFY_INFO = 352 /* 0x160 */, 402 HAL_RXPT_CLASSIFY_INFO = 353 /* 0x161 */, 403 HAL_TX_FLOW_SEARCH_ENTRY = 354 /* 0x162 */, 404 HAL_RX_FLOW_SEARCH_ENTRY = 355 /* 0x163 */, 405 HAL_RECEIVED_TRIGGER_INFO_DETAILS = 356 /* 0x164 */, 406 HAL_COEX_MAC_NAP = 357 /* 0x165 */, 407 HAL_MACRX_ABORT_REQUEST_INFO = 358 /* 0x166 */, 408 HAL_MACTX_ABORT_REQUEST_INFO = 359 /* 0x167 */, 409 HAL_PHYRX_ABORT_REQUEST_INFO = 360 /* 0x168 */, 410 HAL_PHYTX_ABORT_REQUEST_INFO = 361 /* 0x169 */, 411 HAL_RXPCU_PPDU_END_INFO = 362 /* 0x16a */, 412 HAL_WHO_MESH_CONTROL = 363 /* 0x16b */, 413 HAL_L_SIG_A_INFO = 364 /* 0x16c */, 414 HAL_L_SIG_B_INFO = 365 /* 0x16d */, 415 HAL_HT_SIG_INFO = 366 /* 0x16e */, 416 HAL_VHT_SIG_A_INFO = 367 /* 0x16f */, 417 HAL_VHT_SIG_B_SU20_INFO = 368 /* 0x170 */, 418 HAL_VHT_SIG_B_SU40_INFO = 369 /* 0x171 */, 419 HAL_VHT_SIG_B_SU80_INFO = 370 /* 0x172 */, 420 HAL_VHT_SIG_B_SU160_INFO = 371 /* 0x173 */, 421 HAL_VHT_SIG_B_MU20_INFO = 372 /* 0x174 */, 422 HAL_VHT_SIG_B_MU40_INFO = 373 /* 0x175 */, 423 HAL_VHT_SIG_B_MU80_INFO = 374 /* 0x176 */, 424 HAL_VHT_SIG_B_MU160_INFO = 375 /* 0x177 */, 425 HAL_SERVICE_INFO = 376 /* 0x178 */, 426 HAL_HE_SIG_A_SU_INFO = 377 /* 0x179 */, 427 HAL_HE_SIG_A_MU_DL_INFO = 378 /* 0x17a */, 428 HAL_HE_SIG_A_MU_UL_INFO = 379 /* 0x17b */, 429 HAL_HE_SIG_B1_MU_INFO = 380 /* 0x17c */, 430 HAL_HE_SIG_B2_MU_INFO = 381 /* 0x17d */, 431 HAL_HE_SIG_B2_OFDMA_INFO = 382 /* 0x17e */, 432 HAL_PDG_SW_MODE_BW_START = 383 /* 0x17f */, 433 HAL_PDG_SW_MODE_BW_END = 384 /* 0x180 */, 434 HAL_PDG_WAIT_FOR_MAC_REQUEST = 385 /* 0x181 */, 435 HAL_PDG_WAIT_FOR_PHY_REQUEST = 386 /* 0x182 */, 436 HAL_SCHEDULER_END = 387 /* 0x183 */, 437 HAL_PEER_TABLE_ENTRY = 388 /* 0x184 */, 438 HAL_SW_PEER_INFO = 389 /* 0x185 */, 439 HAL_RXOLE_CCE_CLASSIFY_INFO = 390 /* 0x186 */, 440 HAL_TCL_CCE_CLASSIFY_INFO = 391 /* 0x187 */, 441 HAL_RXOLE_CCE_INFO = 392 /* 0x188 */, 442 HAL_TCL_CCE_INFO = 393 /* 0x189 */, 443 HAL_TCL_CCE_SUPERRULE = 394 /* 0x18a */, 444 HAL_CCE_RULE = 395 /* 0x18b */, 445 HAL_RX_PPDU_START_DROPPED = 396 /* 0x18c */, 446 HAL_RX_PPDU_END_DROPPED = 397 /* 0x18d */, 447 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 398 /* 0x18e */, 448 HAL_RX_MPDU_START_DROPPED = 399 /* 0x18f */, 449 HAL_RX_MSDU_START_DROPPED = 400 /* 0x190 */, 450 HAL_RX_MSDU_END_DROPPED = 401 /* 0x191 */, 451 HAL_RX_MPDU_END_DROPPED = 402 /* 0x192 */, 452 HAL_RX_ATTENTION_DROPPED = 403 /* 0x193 */, 453 HAL_TXPCU_USER_SETUP = 404 /* 0x194 */, 454 HAL_RXPCU_USER_SETUP_EXT = 405 /* 0x195 */, 455 HAL_CE_SRC_DESC = 406 /* 0x196 */, 456 HAL_CE_STAT_DESC = 407 /* 0x197 */, 457 HAL_RXOLE_CCE_SUPERRULE = 408 /* 0x198 */, 458 HAL_TX_RATE_STATS_INFO = 409 /* 0x199 */, 459 HAL_CMD_PART_0_END = 410 /* 0x19a */, 460 HAL_MACTX_SYNTH_ON = 411 /* 0x19b */, 461 HAL_SCH_CRITICAL_TLV_REFERENCE = 412 /* 0x19c */, 462 HAL_TQM_MPDU_GLOBAL_START = 413 /* 0x19d */, 463 HAL_EXAMPLE_TLV_32 = 414 /* 0x19e */, 464 HAL_TQM_UPDATE_TX_MSDU_FLOW = 415 /* 0x19f */, 465 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 416 /* 0x1a0 */, 466 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 417 /* 0x1a1 */, 467 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 418 /* 0x1a2 */, 468 HAL_REO_UPDATE_RX_REO_QUEUE = 419 /* 0x1a3 */, 469 HAL_CE_DST_DESC = 420 /* 0x1a4 */, 470 HAL_TLV_BASE = 511 /* 0x1ff */, 471 }; 472 473 #define HAL_TLV_HDR_TAG GENMASK(9, 1) 474 #define HAL_TLV_HDR_LEN GENMASK(25, 10) 475 476 #define HAL_TLV_ALIGN 4 477 478 struct hal_tlv_hdr { 479 u32 tl; 480 u8 value[0]; 481 } __packed; 482 483 #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0) 484 #define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8) 485 #define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(20) 486 #define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(21) 487 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(22) 488 #define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(23) 489 #define RX_MPDU_DESC_INFO0_VALID_PN BIT(24) 490 #define RX_MPDU_DESC_INFO0_VALID_SA BIT(25) 491 #define RX_MPDU_DESC_INFO0_SA_IDX_TIMEOUT BIT(26) 492 #define RX_MPDU_DESC_INFO0_VALID_DA BIT(27) 493 #define RX_MPDU_DESC_INFO0_DA_MCBC BIT(28) 494 #define RX_MPDU_DESC_INFO0_DA_IDX_TIMEOUT BIT(29) 495 #define RX_MPDU_DESC_INFO0_RAW_MPDU BIT(30) 496 497 struct rx_mpdu_desc { 498 u32 info0; /* %RX_MPDU_DESC_INFO */ 499 u32 meta_data; 500 } __packed; 501 502 /* rx_mpdu_desc 503 * Producer: RXDMA 504 * Consumer: REO/SW/FW 505 * 506 * msdu_count 507 * The number of MSDUs within the MPDU 508 * 509 * mpdu_sequence_number 510 * The field can have two different meanings based on the setting 511 * of field 'bar_frame'. If 'bar_frame' is set, it means the MPDU 512 * start sequence number from the BAR frame otherwise it means 513 * the MPDU sequence number of the received frame. 514 * 515 * fragment_flag 516 * When set, this MPDU is a fragment and REO should forward this 517 * fragment MPDU to the REO destination ring without any reorder 518 * checks, pn checks or bitmap update. This implies that REO is 519 * forwarding the pointer to the MSDU link descriptor. 520 * 521 * mpdu_retry_bit 522 * The retry bit setting from the MPDU header of the received frame 523 * 524 * ampdu_flag 525 * Indicates the MPDU was received as part of an A-MPDU. 526 * 527 * bar_frame 528 * Indicates the received frame is a BAR frame. After processing, 529 * this frame shall be pushed to SW or deleted. 530 * 531 * valid_pn 532 * When not set, REO will not perform a PN sequence number check. 533 * 534 * valid_sa 535 * Indicates OLE found a valid SA entry for all MSDUs in this MPDU. 536 * 537 * sa_idx_timeout 538 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 539 * MAC source address search due to the expiration of search timer. 540 * 541 * valid_da 542 * When set, OLE found a valid DA entry for all MSDUs in this MPDU. 543 * 544 * da_mcbc 545 * Field Only valid if valid_da is set. Indicates at least one of 546 * the DA addresses is a Multicast or Broadcast address. 547 * 548 * da_idx_timeout 549 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 550 * MAC destination address search due to the expiration of search 551 * timer. 552 * 553 * raw_mpdu 554 * Field only valid when first_msdu_in_mpdu_flag is set. Indicates 555 * the contents in the MSDU buffer contains a 'RAW' MPDU. 556 */ 557 558 enum hal_rx_msdu_desc_reo_dest_ind { 559 HAL_RX_MSDU_DESC_REO_DEST_IND_TCL, 560 HAL_RX_MSDU_DESC_REO_DEST_IND_SW1, 561 HAL_RX_MSDU_DESC_REO_DEST_IND_SW2, 562 HAL_RX_MSDU_DESC_REO_DEST_IND_SW3, 563 HAL_RX_MSDU_DESC_REO_DEST_IND_SW4, 564 HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE, 565 HAL_RX_MSDU_DESC_REO_DEST_IND_FW, 566 }; 567 568 #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU BIT(0) 569 #define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU BIT(1) 570 #define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION BIT(2) 571 #define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3) 572 #define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17) 573 #define RX_MSDU_DESC_INFO0_MSDU_DROP BIT(22) 574 #define RX_MSDU_DESC_INFO0_VALID_SA BIT(23) 575 #define RX_MSDU_DESC_INFO0_SA_IDX_TIMEOUT BIT(24) 576 #define RX_MSDU_DESC_INFO0_VALID_DA BIT(25) 577 #define RX_MSDU_DESC_INFO0_DA_MCBC BIT(26) 578 #define RX_MSDU_DESC_INFO0_DA_IDX_TIMEOUT BIT(27) 579 580 #define HAL_RX_MSDU_PKT_LENGTH_GET(val) \ 581 (FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val))) 582 583 struct rx_msdu_desc { 584 u32 info0; 585 u32 rsvd0; 586 } __packed; 587 588 /* rx_msdu_desc 589 * 590 * first_msdu_in_mpdu 591 * Indicates first msdu in mpdu. 592 * 593 * last_msdu_in_mpdu 594 * Indicates last msdu in mpdu. This flag can be true only when 595 * 'Msdu_continuation' set to 0. This implies that when an msdu 596 * is spread out over multiple buffers and thus msdu_continuation 597 * is set, only for the very last buffer of the msdu, can the 598 * 'last_msdu_in_mpdu' be set. 599 * 600 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, 601 * the MPDU that this MSDU belongs to only contains a single MSDU. 602 * 603 * msdu_continuation 604 * When set, this MSDU buffer was not able to hold the entire MSDU. 605 * The next buffer will therefor contain additional information 606 * related to this MSDU. 607 * 608 * msdu_length 609 * Field is only valid in combination with the 'first_msdu_in_mpdu' 610 * being set. Full MSDU length in bytes after decapsulation. This 611 * field is still valid for MPDU frames without A-MSDU. It still 612 * represents MSDU length after decapsulation Or in case of RAW 613 * MPDUs, it indicates the length of the entire MPDU (without FCS 614 * field). 615 * 616 * reo_destination_indication 617 * The id of the reo exit ring where the msdu frame shall push 618 * after (MPDU level) reordering has finished. Values are defined 619 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 620 * 621 * msdu_drop 622 * Indicates that REO shall drop this MSDU and not forward it to 623 * any other ring. 624 * 625 * valid_sa 626 * Indicates OLE found a valid SA entry for this MSDU. 627 * 628 * sa_idx_timeout 629 * Indicates, an unsuccessful MAC source address search due to 630 * the expiration of search timer for this MSDU. 631 * 632 * valid_da 633 * When set, OLE found a valid DA entry for this MSDU. 634 * 635 * da_mcbc 636 * Field Only valid if valid_da is set. Indicates the DA address 637 * is a Multicast or Broadcast address for this MSDU. 638 * 639 * da_idx_timeout 640 * Indicates, an unsuccessful MAC destination address search due 641 * to the expiration of search timer fot this MSDU. 642 */ 643 644 enum hal_reo_dest_ring_buffer_type { 645 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU, 646 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC, 647 }; 648 649 enum hal_reo_dest_ring_push_reason { 650 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED, 651 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION, 652 }; 653 654 enum hal_reo_dest_ring_error_code { 655 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO, 656 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID, 657 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA, 658 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE, 659 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE, 660 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP, 661 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP, 662 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR, 663 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR, 664 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION, 665 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN, 666 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED, 667 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET, 668 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET, 669 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED, 670 HAL_REO_DEST_RING_ERROR_CODE_MAX, 671 }; 672 673 #define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 674 #define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE BIT(8) 675 #define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9) 676 #define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11) 677 #define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16) 678 679 #define HAL_REO_DEST_RING_INFO1_REORDER_INFO_VALID BIT(0) 680 #define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1) 681 #define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5) 682 683 #define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20) 684 #define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 685 686 struct hal_reo_dest_ring { 687 struct ath11k_buffer_addr buf_addr_info; 688 struct rx_mpdu_desc rx_mpdu_info; 689 struct rx_msdu_desc rx_msdu_info; 690 u32 queue_addr_lo; 691 u32 info0; /* %HAL_REO_DEST_RING_INFO0_ */ 692 u32 info1; /* %HAL_REO_DEST_RING_INFO1_ */ 693 u32 rsvd0; 694 u32 rsvd1; 695 u32 rsvd2; 696 u32 rsvd3; 697 u32 rsvd4; 698 u32 rsvd5; 699 u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ 700 } __packed; 701 702 /* hal_reo_dest_ring 703 * 704 * Producer: RXDMA 705 * Consumer: REO/SW/FW 706 * 707 * buf_addr_info 708 * Details of the physical address of a buffer or MSDU 709 * link descriptor. 710 * 711 * rx_mpdu_info 712 * General information related to the MPDU that is passed 713 * on from REO entrance ring to the REO destination ring. 714 * 715 * rx_msdu_info 716 * General information related to the MSDU that is passed 717 * on from RXDMA all the way to to the REO destination ring. 718 * 719 * queue_addr_lo 720 * Address (lower 32 bits) of the REO queue descriptor. 721 * 722 * queue_addr_hi 723 * Address (upper 8 bits) of the REO queue descriptor. 724 * 725 * buffer_type 726 * Indicates the type of address provided in the buf_addr_info. 727 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 728 * 729 * push_reason 730 * Reason for pushing this frame to this exit ring. Values are 731 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 732 * 733 * error_code 734 * Valid only when 'push_reason' is set. All error codes are 735 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 736 * 737 * rx_queue_num 738 * Indicates the REO MPDU reorder queue id from which this frame 739 * originated. 740 * 741 * reorder_info_valid 742 * When set, REO has been instructed to not perform the actual 743 * re-ordering of frames for this queue, but just to insert 744 * the reorder opcodes. 745 * 746 * reorder_opcode 747 * Field is valid when 'reorder_info_valid' is set. This field is 748 * always valid for debug purpose as well. 749 * 750 * reorder_slot_idx 751 * Valid only when 'reorder_info_valid' is set. 752 * 753 * ring_id 754 * The buffer pointer ring id. 755 * 0 - Idle ring 756 * 1 - N refers to other rings. 757 * 758 * looping_count 759 * Indicates the number of times the producer of entries into 760 * this ring has looped around the ring. 761 */ 762 763 enum hal_reo_entr_rxdma_ecode { 764 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR, 765 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR, 766 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR, 767 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR, 768 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR, 769 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR, 770 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR, 771 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR, 772 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR, 773 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR, 774 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR, 775 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR, 776 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, 777 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, 778 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, 779 }; 780 781 #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 782 #define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8) 783 #define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22) 784 #define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27) 785 786 #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0) 787 #define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2) 788 789 struct hal_reo_entrance_ring { 790 struct ath11k_buffer_addr buf_addr_info; 791 struct rx_mpdu_desc rx_mpdu_info; 792 u32 queue_addr_lo; 793 u32 info0; /* %HAL_REO_ENTR_RING_INFO0_ */ 794 u32 info1; /* %HAL_REO_ENTR_RING_INFO1_ */ 795 u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ 796 797 } __packed; 798 799 /* hal_reo_entrance_ring 800 * 801 * Producer: RXDMA 802 * Consumer: REO 803 * 804 * buf_addr_info 805 * Details of the physical address of a buffer or MSDU 806 * link descriptor. 807 * 808 * rx_mpdu_info 809 * General information related to the MPDU that is passed 810 * on from REO entrance ring to the REO destination ring. 811 * 812 * queue_addr_lo 813 * Address (lower 32 bits) of the REO queue descriptor. 814 * 815 * queue_addr_hi 816 * Address (upper 8 bits) of the REO queue descriptor. 817 * 818 * mpdu_byte_count 819 * An approximation of the number of bytes received in this MPDU. 820 * Used to keeps stats on the amount of data flowing 821 * through a queue. 822 * 823 * reo_destination_indication 824 * The id of the reo exit ring where the msdu frame shall push 825 * after (MPDU level) reordering has finished. Values are defined 826 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 827 * 828 * frameless_bar 829 * Indicates that this REO entrance ring struct contains BAR info 830 * from a multi TID BAR frame. The original multi TID BAR frame 831 * itself contained all the REO info for the first TID, but all 832 * the subsequent TID info and their linkage to the REO descriptors 833 * is passed down as 'frameless' BAR info. 834 * 835 * The only fields valid in this descriptor when this bit is set 836 * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number, 837 * bar_frame and peer_meta_data. 838 * 839 * rxdma_push_reason 840 * Reason for pushing this frame to this exit ring. Values are 841 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 842 * 843 * rxdma_error_code 844 * Valid only when 'push_reason' is set. All error codes are 845 * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 846 * 847 * ring_id 848 * The buffer pointer ring id. 849 * 0 - Idle ring 850 * 1 - N refers to other rings. 851 * 852 * looping_count 853 * Indicates the number of times the producer of entries into 854 * this ring has looped around the ring. 855 */ 856 857 #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0) 858 #define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16) 859 860 struct hal_reo_cmd_hdr { 861 u32 info0; 862 } __packed; 863 864 #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 865 #define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8) 866 867 struct hal_reo_get_queue_stats { 868 struct hal_reo_cmd_hdr cmd; 869 u32 queue_addr_lo; 870 u32 info0; 871 u32 rsvd0[6]; 872 } __packed; 873 874 /* hal_reo_get_queue_stats 875 * Producer: SW 876 * Consumer: REO 877 * 878 * cmd 879 * Details for command execution tracking purposes. 880 * 881 * queue_addr_lo 882 * Address (lower 32 bits) of the REO queue descriptor. 883 * 884 * queue_addr_hi 885 * Address (upper 8 bits) of the REO queue descriptor. 886 * 887 * clear_stats 888 * Clear stats settings. When set, Clear the stats after 889 * generating the status. 890 * 891 * Following stats will be cleared. 892 * Timeout_count 893 * Forward_due_to_bar_count 894 * Duplicate_count 895 * Frames_in_order_count 896 * BAR_received_count 897 * MPDU_Frames_processed_count 898 * MSDU_Frames_processed_count 899 * Total_processed_byte_count 900 * Late_receive_MPDU_count 901 * window_jump_2k 902 * Hole_count 903 */ 904 905 #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0) 906 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8) 907 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9) 908 909 struct hal_reo_flush_queue { 910 struct hal_reo_cmd_hdr cmd; 911 u32 desc_addr_lo; 912 u32 info0; 913 u32 rsvd0[6]; 914 } __packed; 915 916 #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0) 917 #define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8) 918 #define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9) 919 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10) 920 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) 921 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) 922 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) 923 924 struct hal_reo_flush_cache { 925 struct hal_reo_cmd_hdr cmd; 926 u32 cache_addr_lo; 927 u32 info0; 928 u32 rsvd0[6]; 929 } __packed; 930 931 #define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(0) 932 #define HAL_TCL_DATA_CMD_INFO0_EPD BIT(1) 933 #define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2) 934 #define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4) 935 #define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP BIT(8) 936 #define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP BIT(9) 937 #define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12) 938 #define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14) 939 #define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16) 940 941 #define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0) 942 #define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN BIT(16) 943 #define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN BIT(17) 944 #define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN BIT(18) 945 #define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN BIT(19) 946 #define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN BIT(20) 947 #define HAL_TCL_DATA_CMD_INFO1_TO_FW BIT(21) 948 #define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23) 949 950 #define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0) 951 #define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID BIT(19) 952 #define HAL_TCL_DATA_CMD_INFO2_MESH_ENABLE BIT(20) 953 #define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE BIT(21) 954 #define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22) 955 #define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26) 956 957 #define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0) 958 #define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6) 959 #define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26) 960 961 #define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20) 962 #define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28) 963 964 enum hal_encrypt_type { 965 HAL_ENCRYPT_TYPE_WEP_40, 966 HAL_ENCRYPT_TYPE_WEP_104, 967 HAL_ENCRYPT_TYPE_TKIP_NO_MIC, 968 HAL_ENCRYPT_TYPE_WEP_128, 969 HAL_ENCRYPT_TYPE_TKIP_MIC, 970 HAL_ENCRYPT_TYPE_WAPI, 971 HAL_ENCRYPT_TYPE_CCMP_128, 972 HAL_ENCRYPT_TYPE_OPEN, 973 HAL_ENCRYPT_TYPE_CCMP_256, 974 HAL_ENCRYPT_TYPE_GCMP_128, 975 HAL_ENCRYPT_TYPE_AES_GCMP_256, 976 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4, 977 }; 978 979 enum hal_tcl_encap_type { 980 HAL_TCL_ENCAP_TYPE_RAW, 981 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, 982 HAL_TCL_ENCAP_TYPE_ETHERNET, 983 HAL_TCL_ENCAP_TYPE_802_3 = 3, 984 }; 985 986 enum hal_tcl_desc_type { 987 HAL_TCL_DESC_TYPE_BUFFER, 988 HAL_TCL_DESC_TYPE_EXT_DESC, 989 }; 990 991 enum hal_wbm_htt_tx_comp_status { 992 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK, 993 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP, 994 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL, 995 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, 996 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, 997 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, 998 }; 999 1000 struct hal_tcl_data_cmd { 1001 struct ath11k_buffer_addr buf_addr_info; 1002 u32 info0; 1003 u32 info1; 1004 u32 info2; 1005 u32 info3; 1006 u32 info4; 1007 } __packed; 1008 1009 /* hal_tcl_data_cmd 1010 * 1011 * buf_addr_info 1012 * Details of the physical address of a buffer or MSDU 1013 * link descriptor. 1014 * 1015 * desc_type 1016 * Indicates the type of address provided in the buf_addr_info. 1017 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 1018 * 1019 * epd 1020 * When this bit is set then input packet is an EPD type. 1021 * 1022 * encap_type 1023 * Indicates the encapsulation that HW will perform. Values are 1024 * defined in enum %HAL_TCL_ENCAP_TYPE_. 1025 * 1026 * encrypt_type 1027 * Field only valid for encap_type: RAW 1028 * Values are defined in enum %HAL_ENCRYPT_TYPE_. 1029 * 1030 * src_buffer_swap 1031 * Treats source memory (packet buffer) organization as big-endian. 1032 * 1'b0: Source memory is little endian 1033 * 1'b1: Source memory is big endian 1034 * 1035 * link_meta_swap 1036 * Treats link descriptor and Metadata as big-endian. 1037 * 1'b0: memory is little endian 1038 * 1'b1: memory is big endian 1039 * 1040 * search_type 1041 * Search type select 1042 * 0 - Normal search, 1 - Index based address search, 1043 * 2 - Index based flow search 1044 * 1045 * addrx_en 1046 * addry_en 1047 * Address X/Y search enable in ASE correspondingly. 1048 * 1'b0: Search disable 1049 * 1'b1: Search Enable 1050 * 1051 * cmd_num 1052 * This number can be used to match against status. 1053 * 1054 * data_length 1055 * MSDU length in case of direct descriptor. Length of link 1056 * extension descriptor in case of Link extension descriptor. 1057 * 1058 * *_checksum_en 1059 * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6, 1060 * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6. 1061 * 1062 * to_fw 1063 * Forward packet to FW along with classification result. The 1064 * packet will not be forward to TQM when this bit is set. 1065 * 1'b0: Use classification result to forward the packet. 1066 * 1'b1: Override classification result & forward packet only to fw 1067 * 1068 * packet_offset 1069 * Packet offset from Metadata in case of direct buffer descriptor. 1070 * 1071 * buffer_timestamp 1072 * buffer_timestamp_valid 1073 * Frame system entrance timestamp. It shall be filled by first 1074 * module (SW, TCL or TQM) that sees the frames first. 1075 * 1076 * mesh_enable 1077 * For raw WiFi frames, this indicates transmission to a mesh STA, 1078 * enabling the interpretation of the 'Mesh Control Present' bit 1079 * (bit 8) of QoS Control. 1080 * For native WiFi frames, this indicates that a 'Mesh Control' 1081 * field is present between the header and the LLC. 1082 * 1083 * hlos_tid_overwrite 1084 * 1085 * When set, TCL shall ignore the IP DSCP and VLAN PCP 1086 * fields and use HLOS_TID as the final TID. Otherwise TCL 1087 * shall consider the DSCP and PCP fields as well as HLOS_TID 1088 * and choose a final TID based on the configured priority 1089 * 1090 * hlos_tid 1091 * HLOS MSDU priority 1092 * Field is used when HLOS_TID_overwrite is set. 1093 * 1094 * lmac_id 1095 * TCL uses this LMAC_ID in address search, i.e, while 1096 * finding matching entry for the packet in AST corresponding 1097 * to given LMAC_ID 1098 * 1099 * If LMAC ID is all 1s (=> value 3), it indicates wildcard 1100 * match for any MAC 1101 * 1102 * dscp_tid_table_num 1103 * DSCP to TID mapping table number that need to be used 1104 * for the MSDU. 1105 * 1106 * search_index 1107 * The index that will be used for index based address or 1108 * flow search. The field is valid when 'search_type' is 1 or 2. 1109 * 1110 * cache_set_num 1111 * 1112 * Cache set number that should be used to cache the index 1113 * based search results, for address and flow search. This 1114 * value should be equal to LSB four bits of the hash value of 1115 * match data, in case of search index points to an entry which 1116 * may be used in content based search also. The value can be 1117 * anything when the entry pointed by search index will not be 1118 * used for content based search. 1119 * 1120 * ring_id 1121 * The buffer pointer ring ID. 1122 * 0 refers to the IDLE ring 1123 * 1 - N refers to other rings 1124 * 1125 * looping_count 1126 * 1127 * A count value that indicates the number of times the 1128 * producer of entries into the Ring has looped around the 1129 * ring. 1130 * 1131 * At initialization time, this value is set to 0. On the 1132 * first loop, this value is set to 1. After the max value is 1133 * reached allowed by the number of bits for this field, the 1134 * count value continues with 0 again. 1135 * 1136 * In case SW is the consumer of the ring entries, it can 1137 * use this field to figure out up to where the producer of 1138 * entries has created new entries. This eliminates the need to 1139 * check where the head pointer' of the ring is located once 1140 * the SW starts processing an interrupt indicating that new 1141 * entries have been put into this ring... 1142 * 1143 * Also note that SW if it wants only needs to look at the 1144 * LSB bit of this count value. 1145 */ 1146 1147 #define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd) 1148 1149 enum hal_tcl_gse_ctrl { 1150 HAL_TCL_GSE_CTRL_RD_STAT, 1151 HAL_TCL_GSE_CTRL_SRCH_DIS, 1152 HAL_TCL_GSE_CTRL_WR_BK_SINGLE, 1153 HAL_TCL_GSE_CTRL_WR_BK_ALL, 1154 HAL_TCL_GSE_CTRL_INVAL_SINGLE, 1155 HAL_TCL_GSE_CTRL_INVAL_ALL, 1156 HAL_TCL_GSE_CTRL_WR_BK_INVAL_SINGLE, 1157 HAL_TCL_GSE_CTRL_WR_BK_INVAL_ALL, 1158 HAL_TCL_GSE_CTRL_CLR_STAT_SINGLE, 1159 }; 1160 1161 /* hal_tcl_gse_ctrl 1162 * 1163 * rd_stat 1164 * Report or Read statistics 1165 * srch_dis 1166 * Search disable. Report only Hash. 1167 * wr_bk_single 1168 * Write Back single entry 1169 * wr_bk_all 1170 * Write Back entire cache entry 1171 * inval_single 1172 * Invalidate single cache entry 1173 * inval_all 1174 * Invalidate entire cache 1175 * wr_bk_inval_single 1176 * Write back and invalidate single entry in cache 1177 * wr_bk_inval_all 1178 * Write back and invalidate entire cache 1179 * clr_stat_single 1180 * Clear statistics for single entry 1181 */ 1182 1183 #define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0) 1184 #define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8) 1185 #define HAL_TCL_GSE_CMD_INFO0_GSE_SEL BIT(12) 1186 #define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID BIT(13) 1187 #define HAL_TCL_GSE_CMD_INFO0_SWAP BIT(14) 1188 1189 #define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20) 1190 #define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28) 1191 1192 struct hal_tcl_gse_cmd { 1193 u32 ctrl_buf_addr_lo; 1194 u32 info0; 1195 u32 meta_data[2]; 1196 u32 rsvd0[2]; 1197 u32 info1; 1198 } __packed; 1199 1200 /* hal_tcl_gse_cmd 1201 * 1202 * ctrl_buf_addr_lo, ctrl_buf_addr_hi 1203 * Address of a control buffer containing additional info needed 1204 * for this command execution. 1205 * 1206 * gse_ctrl 1207 * GSE control operations. This includes cache operations and table 1208 * entry statistics read/clear operation. Values are defined in 1209 * enum %HAL_TCL_GSE_CTRL. 1210 * 1211 * gse_sel 1212 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 1213 * 0: FSE select 1: ASE select 1214 * 1215 * status_destination_ring_id 1216 * TCL status ring to which the GSE status needs to be send. 1217 * 1218 * swap 1219 * Bit to enable byte swapping of contents of buffer. 1220 * 1221 * meta_data 1222 * Meta data to be returned in the status descriptor 1223 */ 1224 1225 enum hal_tcl_cache_op_res { 1226 HAL_TCL_CACHE_OP_RES_DONE, 1227 HAL_TCL_CACHE_OP_RES_NOT_FOUND, 1228 HAL_TCL_CACHE_OP_RES_TIMEOUT, 1229 }; 1230 1231 #define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0) 1232 #define HAL_TCL_STATUS_RING_INFO0_GSE_SEL BIT(4) 1233 #define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5) 1234 #define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8) 1235 1236 #define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0) 1237 1238 #define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20) 1239 #define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 1240 1241 struct hal_tcl_status_ring { 1242 u32 info0; 1243 u32 msdu_byte_count; 1244 u32 msdu_timestamp; 1245 u32 meta_data[2]; 1246 u32 info1; 1247 u32 rsvd0; 1248 u32 info2; 1249 } __packed; 1250 1251 /* hal_tcl_status_ring 1252 * 1253 * gse_ctrl 1254 * GSE control operations. This includes cache operations and table 1255 * entry statistics read/clear operation. Values are defined in 1256 * enum %HAL_TCL_GSE_CTRL. 1257 * 1258 * gse_sel 1259 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 1260 * 0: FSE select 1: ASE select 1261 * 1262 * cache_op_res 1263 * Cache operation result. Values are defined in enum 1264 * %HAL_TCL_CACHE_OP_RES_. 1265 * 1266 * msdu_cnt 1267 * msdu_byte_count 1268 * MSDU count of Entry and MSDU byte count for entry 1. 1269 * 1270 * hash_indx 1271 * Hash value of the entry in case of search failed or disabled. 1272 */ 1273 1274 #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1275 #define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8) 1276 #define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9) 1277 #define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10) 1278 #define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11) 1279 #define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16) 1280 1281 #define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0) 1282 1283 #define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20) 1284 #define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1285 1286 struct hal_ce_srng_src_desc { 1287 u32 buffer_addr_low; 1288 u32 buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */ 1289 u32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */ 1290 u32 flags; /* %HAL_CE_SRC_DESC_FLAGS_ */ 1291 } __packed; 1292 1293 /* 1294 * hal_ce_srng_src_desc 1295 * 1296 * buffer_addr_lo 1297 * LSB 32 bits of the 40 Bit Pointer to the source buffer 1298 * 1299 * buffer_addr_hi 1300 * MSB 8 bits of the 40 Bit Pointer to the source buffer 1301 * 1302 * toeplitz_en 1303 * Enable generation of 32-bit Toeplitz-LFSR hash for 1304 * data transfer. In case of gather field in first source 1305 * ring entry of the gather copy cycle in taken into account. 1306 * 1307 * src_swap 1308 * Treats source memory organization as big-endian. For 1309 * each dword read (4 bytes), the byte 0 is swapped with byte 3 1310 * and byte 1 is swapped with byte 2. 1311 * In case of gather field in first source ring entry of 1312 * the gather copy cycle in taken into account. 1313 * 1314 * dest_swap 1315 * Treats destination memory organization as big-endian. 1316 * For each dword write (4 bytes), the byte 0 is swapped with 1317 * byte 3 and byte 1 is swapped with byte 2. 1318 * In case of gather field in first source ring entry of 1319 * the gather copy cycle in taken into account. 1320 * 1321 * gather 1322 * Enables gather of multiple copy engine source 1323 * descriptors to one destination. 1324 * 1325 * ce_res_0 1326 * Reserved 1327 * 1328 * 1329 * length 1330 * Length of the buffer in units of octets of the current 1331 * descriptor 1332 * 1333 * fw_metadata 1334 * Meta data used by FW. 1335 * In case of gather field in first source ring entry of 1336 * the gather copy cycle in taken into account. 1337 * 1338 * ce_res_1 1339 * Reserved 1340 * 1341 * ce_res_2 1342 * Reserved 1343 * 1344 * ring_id 1345 * The buffer pointer ring ID. 1346 * 0 refers to the IDLE ring 1347 * 1 - N refers to other rings 1348 * Helps with debugging when dumping ring contents. 1349 * 1350 * looping_count 1351 * A count value that indicates the number of times the 1352 * producer of entries into the Ring has looped around the 1353 * ring. 1354 * 1355 * At initialization time, this value is set to 0. On the 1356 * first loop, this value is set to 1. After the max value is 1357 * reached allowed by the number of bits for this field, the 1358 * count value continues with 0 again. 1359 * 1360 * In case SW is the consumer of the ring entries, it can 1361 * use this field to figure out up to where the producer of 1362 * entries has created new entries. This eliminates the need to 1363 * check where the head pointer' of the ring is located once 1364 * the SW starts processing an interrupt indicating that new 1365 * entries have been put into this ring... 1366 * 1367 * Also note that SW if it wants only needs to look at the 1368 * LSB bit of this count value. 1369 */ 1370 1371 #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1372 #define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20) 1373 #define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1374 1375 struct hal_ce_srng_dest_desc { 1376 u32 buffer_addr_low; 1377 u32 buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */ 1378 } __packed; 1379 1380 /* hal_ce_srng_dest_desc 1381 * 1382 * dst_buffer_low 1383 * LSB 32 bits of the 40 Bit Pointer to the Destination 1384 * buffer 1385 * 1386 * dst_buffer_high 1387 * MSB 8 bits of the 40 Bit Pointer to the Destination 1388 * buffer 1389 * 1390 * ce_res_4 1391 * Reserved 1392 * 1393 * ring_id 1394 * The buffer pointer ring ID. 1395 * 0 refers to the IDLE ring 1396 * 1 - N refers to other rings 1397 * Helps with debugging when dumping ring contents. 1398 * 1399 * looping_count 1400 * A count value that indicates the number of times the 1401 * producer of entries into the Ring has looped around the 1402 * ring. 1403 * 1404 * At initialization time, this value is set to 0. On the 1405 * first loop, this value is set to 1. After the max value is 1406 * reached allowed by the number of bits for this field, the 1407 * count value continues with 0 again. 1408 * 1409 * In case SW is the consumer of the ring entries, it can 1410 * use this field to figure out up to where the producer of 1411 * entries has created new entries. This eliminates the need to 1412 * check where the head pointer' of the ring is located once 1413 * the SW starts processing an interrupt indicating that new 1414 * entries have been put into this ring... 1415 * 1416 * Also note that SW if it wants only needs to look at the 1417 * LSB bit of this count value. 1418 */ 1419 1420 #define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8) 1421 #define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9) 1422 #define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10) 1423 #define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11) 1424 #define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16) 1425 1426 #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(7, 0) 1427 #define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20) 1428 #define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1429 1430 struct hal_ce_srng_dst_status_desc { 1431 u32 flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */ 1432 u32 toeplitz_hash0; 1433 u32 toeplitz_hash1; 1434 u32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */ 1435 } __packed; 1436 1437 /* hal_ce_srng_dst_status_desc 1438 * 1439 * ce_res_5 1440 * Reserved 1441 * 1442 * toeplitz_en 1443 * 1444 * src_swap 1445 * Source memory buffer swapped 1446 * 1447 * dest_swap 1448 * Destination memory buffer swapped 1449 * 1450 * gather 1451 * Gather of multiple copy engine source descriptors to one 1452 * destination enabled 1453 * 1454 * ce_res_6 1455 * Reserved 1456 * 1457 * length 1458 * Sum of all the Lengths of the source descriptor in the 1459 * gather chain 1460 * 1461 * toeplitz_hash_0 1462 * 32 LS bits of 64 bit Toeplitz LFSR hash result 1463 * 1464 * toeplitz_hash_1 1465 * 32 MS bits of 64 bit Toeplitz LFSR hash result 1466 * 1467 * fw_metadata 1468 * Meta data used by FW 1469 * In case of gather field in first source ring entry of 1470 * the gather copy cycle in taken into account. 1471 * 1472 * ce_res_7 1473 * Reserved 1474 * 1475 * ring_id 1476 * The buffer pointer ring ID. 1477 * 0 refers to the IDLE ring 1478 * 1 - N refers to other rings 1479 * Helps with debugging when dumping ring contents. 1480 * 1481 * looping_count 1482 * A count value that indicates the number of times the 1483 * producer of entries into the Ring has looped around the 1484 * ring. 1485 * 1486 * At initialization time, this value is set to 0. On the 1487 * first loop, this value is set to 1. After the max value is 1488 * reached allowed by the number of bits for this field, the 1489 * count value continues with 0 again. 1490 * 1491 * In case SW is the consumer of the ring entries, it can 1492 * use this field to figure out up to where the producer of 1493 * entries has created new entries. This eliminates the need to 1494 * check where the head pointer' of the ring is located once 1495 * the SW starts processing an interrupt indicating that new 1496 * entries have been put into this ring... 1497 * 1498 * Also note that SW if it wants only needs to look at the 1499 * LSB bit of this count value. 1500 */ 1501 1502 #define HAL_TX_RATE_STATS_INFO0_VALID BIT(0) 1503 #define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1) 1504 #define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3) 1505 #define HAL_TX_RATE_STATS_INFO0_STBC BIT(7) 1506 #define HAL_TX_RATE_STATS_INFO0_LDPC BIT(8) 1507 #define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9) 1508 #define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11) 1509 #define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(15) 1510 #define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16) 1511 1512 enum hal_tx_rate_stats_bw { 1513 HAL_TX_RATE_STATS_BW_20, 1514 HAL_TX_RATE_STATS_BW_40, 1515 HAL_TX_RATE_STATS_BW_80, 1516 HAL_TX_RATE_STATS_BW_160, 1517 }; 1518 1519 enum hal_tx_rate_stats_pkt_type { 1520 HAL_TX_RATE_STATS_PKT_TYPE_11A, 1521 HAL_TX_RATE_STATS_PKT_TYPE_11B, 1522 HAL_TX_RATE_STATS_PKT_TYPE_11N, 1523 HAL_TX_RATE_STATS_PKT_TYPE_11AC, 1524 HAL_TX_RATE_STATS_PKT_TYPE_11AX, 1525 }; 1526 1527 enum hal_tx_rate_stats_sgi { 1528 HAL_TX_RATE_STATS_SGI_08US, 1529 HAL_TX_RATE_STATS_SGI_04US, 1530 HAL_TX_RATE_STATS_SGI_16US, 1531 HAL_TX_RATE_STATS_SGI_32US, 1532 }; 1533 1534 struct hal_tx_rate_stats { 1535 u32 info0; 1536 u32 tsf; 1537 } __packed; 1538 1539 struct hal_wbm_link_desc { 1540 struct ath11k_buffer_addr buf_addr_info; 1541 } __packed; 1542 1543 /* hal_wbm_link_desc 1544 * 1545 * Producer: WBM 1546 * Consumer: WBM 1547 * 1548 * buf_addr_info 1549 * Details of the physical address of a buffer or MSDU 1550 * link descriptor. 1551 */ 1552 1553 enum hal_wbm_rel_src_module { 1554 HAL_WBM_REL_SRC_MODULE_TQM, 1555 HAL_WBM_REL_SRC_MODULE_RXDMA, 1556 HAL_WBM_REL_SRC_MODULE_REO, 1557 HAL_WBM_REL_SRC_MODULE_FW, 1558 HAL_WBM_REL_SRC_MODULE_SW, 1559 }; 1560 1561 enum hal_wbm_rel_desc_type { 1562 HAL_WBM_REL_DESC_TYPE_REL_MSDU, 1563 HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 1564 HAL_WBM_REL_DESC_TYPE_MPDU_LINK, 1565 HAL_WBM_REL_DESC_TYPE_MSDU_EXT, 1566 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT, 1567 }; 1568 1569 /* hal_wbm_rel_desc_type 1570 * 1571 * msdu_buffer 1572 * The address points to an MSDU buffer 1573 * 1574 * msdu_link_descriptor 1575 * The address points to an Tx MSDU link descriptor 1576 * 1577 * mpdu_link_descriptor 1578 * The address points to an MPDU link descriptor 1579 * 1580 * msdu_ext_descriptor 1581 * The address points to an MSDU extension descriptor 1582 * 1583 * queue_ext_descriptor 1584 * The address points to an TQM queue extension descriptor. WBM should 1585 * treat this is the same way as a link descriptor. 1586 */ 1587 1588 enum hal_wbm_rel_bm_act { 1589 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE, 1590 HAL_WBM_REL_BM_ACT_REL_MSDU, 1591 }; 1592 1593 /* hal_wbm_rel_bm_act 1594 * 1595 * put_in_idle_list 1596 * Put the buffer or descriptor back in the idle list. In case of MSDU or 1597 * MDPU link descriptor, BM does not need to check to release any 1598 * individual MSDU buffers. 1599 * 1600 * release_msdu_list 1601 * This BM action can only be used in combination with desc_type being 1602 * msdu_link_descriptor. Field first_msdu_index points out which MSDU 1603 * pointer in the MSDU link descriptor is the first of an MPDU that is 1604 * released. BM shall release all the MSDU buffers linked to this first 1605 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be 1606 * set to value 0, which represents the 'NULL' pointer. When all MSDU 1607 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link 1608 * descriptor itself shall also be released. 1609 */ 1610 1611 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1612 #define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3) 1613 #define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6) 1614 #define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) 1615 #define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13) 1616 #define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 1617 #define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 1618 #define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24) 1619 #define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26) 1620 #define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31) 1621 1622 #define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) 1623 #define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24) 1624 1625 #define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) 1626 #define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID BIT(8) 1627 #define HAL_WBM_RELEASE_INFO2_FIRST_MSDU BIT(9) 1628 #define HAL_WBM_RELEASE_INFO2_LAST_MSDU BIT(10) 1629 #define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU BIT(11) 1630 #define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME BIT(12) 1631 #define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) 1632 1633 #define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0) 1634 #define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16) 1635 #define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20) 1636 #define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28) 1637 1638 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9) 1639 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13) 1640 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME BIT(17) 1641 1642 struct hal_wbm_release_ring { 1643 struct ath11k_buffer_addr buf_addr_info; 1644 u32 info0; 1645 u32 info1; 1646 u32 info2; 1647 struct hal_tx_rate_stats rate_stats; 1648 u32 info3; 1649 } __packed; 1650 1651 /* hal_wbm_release_ring 1652 * 1653 * Producer: SW/TQM/RXDMA/REO/SWITCH 1654 * Consumer: WBM/SW/FW 1655 * 1656 * HTT tx status is overlayed on wbm_release ring on 4-byte words 2, 3, 4 and 5 1657 * for software based completions. 1658 * 1659 * buf_addr_info 1660 * Details of the physical address of the buffer or link descriptor. 1661 * 1662 * release_source_module 1663 * Indicates which module initiated the release of this buffer/descriptor. 1664 * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_. 1665 * 1666 * bm_action 1667 * Field only valid when the field return_buffer_manager in 1668 * Released_buff_or_desc_addr_info indicates: 1669 * WBM_IDLE_BUF_LIST / WBM_IDLE_DESC_LIST 1670 * Values are defined in enum %HAL_WBM_REL_BM_ACT_. 1671 * 1672 * buffer_or_desc_type 1673 * Field only valid when WBM is marked as the return_buffer_manager in 1674 * the Released_Buffer_address_info. Indicates that type of buffer or 1675 * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE. 1676 * 1677 * first_msdu_index 1678 * Field only valid for the bm_action release_msdu_list. The index of the 1679 * first MSDU in an MSDU link descriptor all belonging to the same MPDU. 1680 * 1681 * tqm_release_reason 1682 * Field only valid when Release_source_module is set to release_source_TQM 1683 * Release reasons are defined in enum %HAL_WBM_TQM_REL_REASON_. 1684 * 1685 * rxdma_push_reason 1686 * reo_push_reason 1687 * Indicates why rxdma/reo pushed the frame to this ring and values are 1688 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 1689 * 1690 * rxdma_error_code 1691 * Field only valid when 'rxdma_push_reason' set to 'error_detected'. 1692 * Values are defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 1693 * 1694 * reo_error_code 1695 * Field only valid when 'reo_push_reason' set to 'error_detected'. Values 1696 * are defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 1697 * 1698 * wbm_internal_error 1699 * Is set when WBM got a buffer pointer but the action was to push it to 1700 * the idle link descriptor ring or do link related activity OR 1701 * Is set when WBM got a link buffer pointer but the action was to push it 1702 * to the buffer descriptor ring. 1703 * 1704 * tqm_status_number 1705 * The value in this field is equal to tqm_cmd_number in TQM command. It is 1706 * used to correlate the statu with TQM commands. Only valid when 1707 * release_source_module is TQM. 1708 * 1709 * transmit_count 1710 * The number of times the frame has been transmitted, valid only when 1711 * release source in TQM. 1712 * 1713 * ack_frame_rssi 1714 * This field is only valid when the source is TQM. If this frame is 1715 * removed as the result of the reception of an ACK or BA, this field 1716 * indicates the RSSI of the received ACK or BA frame. 1717 * 1718 * sw_release_details_valid 1719 * This is set when WMB got a 'release_msdu_list' command from TQM and 1720 * return buffer manager is not WMB. WBM will then de-aggregate all MSDUs 1721 * and pass them one at a time on to the 'buffer owner'. 1722 * 1723 * first_msdu 1724 * Field only valid when SW_release_details_valid is set. 1725 * When set, this MSDU is the first MSDU pointed to in the 1726 * 'release_msdu_list' command. 1727 * 1728 * last_msdu 1729 * Field only valid when SW_release_details_valid is set. 1730 * When set, this MSDU is the last MSDU pointed to in the 1731 * 'release_msdu_list' command. 1732 * 1733 * msdu_part_of_amsdu 1734 * Field only valid when SW_release_details_valid is set. 1735 * When set, this MSDU was part of an A-MSDU in MPDU 1736 * 1737 * fw_tx_notify_frame 1738 * Field only valid when SW_release_details_valid is set. 1739 * 1740 * buffer_timestamp 1741 * Field only valid when SW_release_details_valid is set. 1742 * This is the Buffer_timestamp field from the 1743 * Timestamp in units of 1024 us 1744 * 1745 * struct hal_tx_rate_stats rate_stats 1746 * Details for command execution tracking purposes. 1747 * 1748 * sw_peer_id 1749 * tid 1750 * Field only valid when Release_source_module is set to 1751 * release_source_TQM 1752 * 1753 * 1) Release of msdu buffer due to drop_frame = 1. Flow is 1754 * not fetched and hence sw_peer_id and tid = 0 1755 * 1756 * buffer_or_desc_type = e_num 0 1757 * MSDU_rel_buffertqm_release_reason = e_num 1 1758 * tqm_rr_rem_cmd_rem 1759 * 1760 * 2) Release of msdu buffer due to Flow is not fetched and 1761 * hence sw_peer_id and tid = 0 1762 * 1763 * buffer_or_desc_type = e_num 0 1764 * MSDU_rel_buffertqm_release_reason = e_num 1 1765 * tqm_rr_rem_cmd_rem 1766 * 1767 * 3) Release of msdu link due to remove_mpdu or acked_mpdu 1768 * command. 1769 * 1770 * buffer_or_desc_type = e_num1 1771 * msdu_link_descriptortqm_release_reason can be:e_num 1 1772 * tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 1773 * e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged 1774 * 1775 * This field represents the TID from the TX_MSDU_FLOW 1776 * descriptor or TX_MPDU_QUEUE descriptor 1777 * 1778 * rind_id 1779 * For debugging. 1780 * This field is filled in by the SRNG module. 1781 * It help to identify the ring that is being looked 1782 * 1783 * looping_count 1784 * A count value that indicates the number of times the 1785 * producer of entries into the Buffer Manager Ring has looped 1786 * around the ring. 1787 * 1788 * At initialization time, this value is set to 0. On the 1789 * first loop, this value is set to 1. After the max value is 1790 * reached allowed by the number of bits for this field, the 1791 * count value continues with 0 again. 1792 * 1793 * In case SW is the consumer of the ring entries, it can 1794 * use this field to figure out up to where the producer of 1795 * entries has created new entries. This eliminates the need to 1796 * check where the head pointer' of the ring is located once 1797 * the SW starts processing an interrupt indicating that new 1798 * entries have been put into this ring... 1799 * 1800 * Also note that SW if it wants only needs to look at the 1801 * LSB bit of this count value. 1802 */ 1803 1804 /** 1805 * enum hal_wbm_tqm_rel_reason - TQM release reason code 1806 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame 1807 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW 1808 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus 1809 * initiated by sw. 1810 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus 1811 * initiated by sw. 1812 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or 1813 * mpdus. 1814 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by 1815 * fw with fw_reason1. 1816 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by 1817 * fw with fw_reason2. 1818 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by 1819 * fw with fw_reason3. 1820 */ 1821 enum hal_wbm_tqm_rel_reason { 1822 HAL_WBM_TQM_REL_REASON_FRAME_ACKED, 1823 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU, 1824 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX, 1825 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX, 1826 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES, 1827 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1, 1828 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2, 1829 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3, 1830 }; 1831 1832 struct hal_wbm_buffer_ring { 1833 struct ath11k_buffer_addr buf_addr_info; 1834 }; 1835 1836 enum hal_desc_owner { 1837 HAL_DESC_OWNER_WBM, 1838 HAL_DESC_OWNER_SW, 1839 HAL_DESC_OWNER_TQM, 1840 HAL_DESC_OWNER_RXDMA, 1841 HAL_DESC_OWNER_REO, 1842 HAL_DESC_OWNER_SWITCH, 1843 }; 1844 1845 enum hal_desc_buf_type { 1846 HAL_DESC_BUF_TYPE_TX_MSDU_LINK, 1847 HAL_DESC_BUF_TYPE_TX_MPDU_LINK, 1848 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD, 1849 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT, 1850 HAL_DESC_BUF_TYPE_TX_FLOW, 1851 HAL_DESC_BUF_TYPE_TX_BUFFER, 1852 HAL_DESC_BUF_TYPE_RX_MSDU_LINK, 1853 HAL_DESC_BUF_TYPE_RX_MPDU_LINK, 1854 HAL_DESC_BUF_TYPE_RX_REO_QUEUE, 1855 HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT, 1856 HAL_DESC_BUF_TYPE_RX_BUFFER, 1857 HAL_DESC_BUF_TYPE_IDLE_LINK, 1858 }; 1859 1860 #define HAL_DESC_REO_OWNED 4 1861 #define HAL_DESC_REO_QUEUE_DESC 8 1862 #define HAL_DESC_REO_QUEUE_EXT_DESC 9 1863 #define HAL_DESC_REO_NON_QOS_TID 16 1864 1865 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0) 1866 #define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4) 1867 #define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8) 1868 1869 struct hal_desc_header { 1870 u32 info0; 1871 } __packed; 1872 1873 struct hal_rx_mpdu_link_ptr { 1874 struct ath11k_buffer_addr addr_info; 1875 } __packed; 1876 1877 struct hal_rx_msdu_details { 1878 struct ath11k_buffer_addr buf_addr_info; 1879 struct rx_msdu_desc rx_msdu_info; 1880 } __packed; 1881 1882 #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0) 1883 #define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16) 1884 1885 struct hal_rx_msdu_link { 1886 struct hal_desc_header desc_hdr; 1887 struct ath11k_buffer_addr buf_addr_info; 1888 u32 info0; 1889 u32 pn[4]; 1890 struct hal_rx_msdu_details msdu_link[6]; 1891 } __packed; 1892 1893 struct hal_rx_reo_queue_ext { 1894 struct hal_desc_header desc_hdr; 1895 u32 rsvd; 1896 struct hal_rx_mpdu_link_ptr mpdu_link[15]; 1897 } __packed; 1898 1899 /* hal_rx_reo_queue_ext 1900 * Consumer: REO 1901 * Producer: REO 1902 * 1903 * descriptor_header 1904 * Details about which module owns this struct. 1905 * 1906 * mpdu_link 1907 * Pointer to the next MPDU_link descriptor in the MPDU queue. 1908 */ 1909 1910 enum hal_rx_reo_queue_pn_size { 1911 HAL_RX_REO_QUEUE_PN_SIZE_24, 1912 HAL_RX_REO_QUEUE_PN_SIZE_48, 1913 HAL_RX_REO_QUEUE_PN_SIZE_128, 1914 }; 1915 1916 #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0) 1917 1918 #define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0) 1919 #define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1) 1920 #define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3) 1921 #define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4) 1922 #define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5) 1923 #define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7) 1924 #define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8) 1925 #define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9) 1926 #define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10) 1927 #define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11) 1928 #define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(19) 1929 #define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(20) 1930 #define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(21) 1931 #define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(22) 1932 #define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23) 1933 #define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(25) 1934 1935 #define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0) 1936 #define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1) 1937 #define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13) 1938 #define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(21) 1939 #define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(22) 1940 #define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31) 1941 1942 #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0) 1943 #define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7) 1944 1945 #define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4) 1946 #define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10) 1947 #define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 10) 1948 1949 #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0) 1950 #define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24) 1951 1952 #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0) 1953 #define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12) 1954 #define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16) 1955 1956 struct hal_rx_reo_queue { 1957 struct hal_desc_header desc_hdr; 1958 u32 rx_queue_num; 1959 u32 info0; 1960 u32 info1; 1961 u32 pn[4]; 1962 u32 last_rx_enqueue_timestamp; 1963 u32 last_rx_dequeue_timestamp; 1964 u32 next_aging_queue[2]; 1965 u32 prev_aging_queue[2]; 1966 u32 rx_bitmap[8]; 1967 u32 info2; 1968 u32 info3; 1969 u32 info4; 1970 u32 processed_mpdus; 1971 u32 processed_msdus; 1972 u32 processed_total_bytes; 1973 u32 info5; 1974 u32 rsvd[3]; 1975 struct hal_rx_reo_queue_ext ext_desc[0]; 1976 } __packed; 1977 1978 /* hal_rx_reo_queue 1979 * 1980 * descriptor_header 1981 * Details about which module owns this struct. Note that sub field 1982 * Buffer_type shall be set to receive_reo_queue_descriptor. 1983 * 1984 * receive_queue_number 1985 * Indicates the MPDU queue ID to which this MPDU link descriptor belongs. 1986 * 1987 * vld 1988 * Valid bit indicating a session is established and the queue descriptor 1989 * is valid. 1990 * associated_link_descriptor_counter 1991 * Indicates which of the 3 link descriptor counters shall be incremented 1992 * or decremented when link descriptors are added or removed from this 1993 * flow queue. 1994 * disable_duplicate_detection 1995 * When set, do not perform any duplicate detection. 1996 * soft_reorder_enable 1997 * When set, REO has been instructed to not perform the actual re-ordering 1998 * of frames for this queue, but just to insert the reorder opcodes. 1999 * ac 2000 * Indicates the access category of the queue descriptor. 2001 * bar 2002 * Indicates if BAR has been received. 2003 * retry 2004 * Retry bit is checked if this bit is set. 2005 * chk_2k_mode 2006 * Indicates what type of operation is expected from Reo when the received 2007 * frame SN falls within the 2K window. 2008 * oor_mode 2009 * Indicates what type of operation is expected when the received frame 2010 * falls within the OOR window. 2011 * ba_window_size 2012 * Indicates the negotiated (window size + 1). Max of 256 bits. 2013 * 2014 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA 2015 * session, with window size of 0). The 3 values here are the main values 2016 * validated, but other values should work as well. 2017 * 2018 * A BA window size of 0 (=> one frame entry bitmat), means that there is 2019 * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory. 2020 * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext. 2021 * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext. 2022 * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext. 2023 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable, 2024 * pn_size 2025 * REO shall perform the PN increment check, even number check, uneven 2026 * number check, PN error check and size of the PN field check. 2027 * ignore_ampdu_flag 2028 * REO shall ignore the ampdu_flag on entrance descriptor for this queue. 2029 * 2030 * svld 2031 * Sequence number in next field is valid one. 2032 * ssn 2033 * Starting Sequence number of the session. 2034 * current_index 2035 * Points to last forwarded packet 2036 * seq_2k_error_detected_flag 2037 * REO has detected a 2k error jump in the sequence number and from that 2038 * moment forward, all new frames are forwarded directly to FW, without 2039 * duplicate detect, reordering, etc. 2040 * pn_error_detected_flag 2041 * REO has detected a PN error. 2042 */ 2043 2044 #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 2045 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8) 2046 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9) 2047 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10) 2048 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11) 2049 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12) 2050 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13) 2051 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14) 2052 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15) 2053 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16) 2054 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17) 2055 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18) 2056 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19) 2057 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20) 2058 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21) 2059 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22) 2060 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23) 2061 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24) 2062 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25) 2063 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26) 2064 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27) 2065 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28) 2066 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29) 2067 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30) 2068 2069 #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0) 2070 #define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16) 2071 #define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17) 2072 #define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19) 2073 #define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20) 2074 #define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21) 2075 #define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23) 2076 #define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24) 2077 #define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25) 2078 #define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26) 2079 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27) 2080 #define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28) 2081 #define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29) 2082 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30) 2083 #define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31) 2084 2085 #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0) 2086 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8) 2087 #define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10) 2088 #define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11) 2089 #define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23) 2090 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24) 2091 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25) 2092 2093 struct hal_reo_update_rx_queue { 2094 struct hal_reo_cmd_hdr cmd; 2095 u32 queue_addr_lo; 2096 u32 info0; 2097 u32 info1; 2098 u32 info2; 2099 u32 pn[4]; 2100 } __packed; 2101 2102 #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0) 2103 #define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1) 2104 2105 struct hal_reo_unblock_cache { 2106 struct hal_reo_cmd_hdr cmd; 2107 u32 info0; 2108 u32 rsvd[7]; 2109 } __packed; 2110 2111 enum hal_reo_exec_status { 2112 HAL_REO_EXEC_STATUS_SUCCESS, 2113 HAL_REO_EXEC_STATUS_BLOCKED, 2114 HAL_REO_EXEC_STATUS_FAILED, 2115 HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED, 2116 }; 2117 2118 #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0) 2119 #define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16) 2120 #define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26) 2121 2122 struct hal_reo_status_hdr { 2123 u32 info0; 2124 u32 timestamp; 2125 } __packed; 2126 2127 /* hal_reo_status_hdr 2128 * Producer: REO 2129 * Consumer: SW 2130 * 2131 * status_num 2132 * The value in this field is equal to value of the reo command 2133 * number. This field helps to correlate the statuses with the REO 2134 * commands. 2135 * 2136 * execution_time (in us) 2137 * The amount of time REO took to excecute the command. Note that 2138 * this time does not include the duration of the command waiting 2139 * in the command ring, before the execution started. 2140 * 2141 * execution_status 2142 * Execution status of the command. Values are defined in 2143 * enum %HAL_REO_EXEC_STATUS_. 2144 */ 2145 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0) 2146 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12) 2147 2148 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0) 2149 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7) 2150 2151 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4) 2152 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10) 2153 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16) 2154 2155 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0) 2156 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24) 2157 2158 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0) 2159 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12) 2160 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16) 2161 2162 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28) 2163 2164 struct hal_reo_get_queue_stats_status { 2165 struct hal_reo_status_hdr hdr; 2166 u32 info0; 2167 u32 pn[4]; 2168 u32 last_rx_enqueue_timestamp; 2169 u32 last_rx_dequeue_timestamp; 2170 u32 rx_bitmap[8]; 2171 u32 info1; 2172 u32 info2; 2173 u32 info3; 2174 u32 num_mpdu_frames; 2175 u32 num_msdu_frames; 2176 u32 total_bytes; 2177 u32 info4; 2178 u32 info5; 2179 } __packed; 2180 2181 /* hal_reo_get_queue_stats_status 2182 * Producer: REO 2183 * Consumer: SW 2184 * 2185 * status_hdr 2186 * Details that can link this status with the original command. It 2187 * also contains info on how long REO took to execute this command. 2188 * 2189 * ssn 2190 * Starting Sequence number of the session, this changes whenever 2191 * window moves (can be filled by SW then maintained by REO). 2192 * 2193 * current_index 2194 * Points to last forwarded packet. 2195 * 2196 * pn 2197 * Bits of the PN number. 2198 * 2199 * last_rx_enqueue_timestamp 2200 * last_rx_dequeue_timestamp 2201 * Timestamp of arrival of the last MPDU for this queue and 2202 * Timestamp of forwarding an MPDU accordingly. 2203 * 2204 * rx_bitmap 2205 * When a bit is set, the corresponding frame is currently held 2206 * in the re-order queue. The bitmap is Fully managed by HW. 2207 * 2208 * current_mpdu_count 2209 * current_msdu_count 2210 * The number of MPDUs and MSDUs in the queue. 2211 * 2212 * timeout_count 2213 * The number of times REO started forwarding frames even though 2214 * there is a hole in the bitmap. Forwarding reason is timeout. 2215 * 2216 * forward_due_to_bar_count 2217 * The number of times REO started forwarding frames even though 2218 * there is a hole in the bitmap. Fwd reason is reception of BAR. 2219 * 2220 * duplicate_count 2221 * The number of duplicate frames that have been detected. 2222 * 2223 * frames_in_order_count 2224 * The number of frames that have been received in order (without 2225 * a hole that prevented them from being forwarded immediately). 2226 * 2227 * bar_received_count 2228 * The number of times a BAR frame is received. 2229 * 2230 * mpdu_frames_processed_count 2231 * msdu_frames_processed_count 2232 * The total number of MPDU/MSDU frames that have been processed. 2233 * 2234 * total_bytes 2235 * An approximation of the number of bytes received for this queue. 2236 * 2237 * late_receive_mpdu_count 2238 * The number of MPDUs received after the window had already moved 2239 * on. The 'late' sequence window is defined as 2240 * (Window SSN - 256) - (Window SSN - 1). 2241 * 2242 * window_jump_2k 2243 * The number of times the window moved more than 2K 2244 * 2245 * hole_count 2246 * The number of times a hole was created in the receive bitmap. 2247 * 2248 * looping_count 2249 * A count value that indicates the number of times the producer of 2250 * entries into this Ring has looped around the ring. 2251 */ 2252 2253 #define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28) 2254 2255 #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0) 2256 #define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1) 2257 #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0) 2258 2259 struct hal_reo_flush_queue_status { 2260 struct hal_reo_status_hdr hdr; 2261 u32 info0; 2262 u32 rsvd0[21]; 2263 u32 info1; 2264 } __packed; 2265 2266 /* hal_reo_flush_queue_status 2267 * Producer: REO 2268 * Consumer: SW 2269 * 2270 * status_hdr 2271 * Details that can link this status with the original command. It 2272 * also contains info on how long REO took to execute this command. 2273 * 2274 * error_detected 2275 * Status of blocking resource 2276 * 2277 * 0 - No error has been detected while executing this command 2278 * 1 - Error detected. The resource to be used for blocking was 2279 * already in use. 2280 * 2281 * looping_count 2282 * A count value that indicates the number of times the producer of 2283 * entries into this Ring has looped around the ring. 2284 */ 2285 2286 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2287 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1) 2288 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8) 2289 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9) 2290 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12) 2291 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16) 2292 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18) 2293 2294 struct hal_reo_flush_cache_status { 2295 struct hal_reo_status_hdr hdr; 2296 u32 info0; 2297 u32 rsvd0[21]; 2298 u32 info1; 2299 } __packed; 2300 2301 /* hal_reo_flush_cache_status 2302 * Producer: REO 2303 * Consumer: SW 2304 * 2305 * status_hdr 2306 * Details that can link this status with the original command. It 2307 * also contains info on how long REO took to execute this command. 2308 * 2309 * error_detected 2310 * Status for blocking resource handling 2311 * 2312 * 0 - No error has been detected while executing this command 2313 * 1 - An error in the blocking resource management was detected 2314 * 2315 * block_error_details 2316 * only valid when error_detected is set 2317 * 2318 * 0 - No blocking related errors found 2319 * 1 - Blocking resource is already in use 2320 * 2 - Resource requested to be unblocked, was not blocked 2321 * 2322 * cache_controller_flush_status_hit 2323 * The status that the cache controller returned on executing the 2324 * flush command. 2325 * 2326 * 0 - miss; 1 - hit 2327 * 2328 * cache_controller_flush_status_desc_type 2329 * Flush descriptor type 2330 * 2331 * cache_controller_flush_status_client_id 2332 * Module who made the flush request 2333 * 2334 * In REO, this is always 0 2335 * 2336 * cache_controller_flush_status_error 2337 * Error condition 2338 * 2339 * 0 - No error found 2340 * 1 - HW interface is still busy 2341 * 2 - Line currently locked. Used for one line flush command 2342 * 3 - At least one line is still locked. 2343 * Used for cache flush command. 2344 * 2345 * cache_controller_flush_count 2346 * The number of lines that were actually flushed out 2347 * 2348 * looping_count 2349 * A count value that indicates the number of times the producer of 2350 * entries into this Ring has looped around the ring. 2351 */ 2352 2353 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2354 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1) 2355 2356 struct hal_reo_unblock_cache_status { 2357 struct hal_reo_status_hdr hdr; 2358 u32 info0; 2359 u32 rsvd0[21]; 2360 u32 info1; 2361 } __packed; 2362 2363 /* hal_reo_unblock_cache_status 2364 * Producer: REO 2365 * Consumer: SW 2366 * 2367 * status_hdr 2368 * Details that can link this status with the original command. It 2369 * also contains info on how long REO took to execute this command. 2370 * 2371 * error_detected 2372 * 0 - No error has been detected while executing this command 2373 * 1 - The blocking resource was not in use, and therefore it could 2374 * not be unblocked. 2375 * 2376 * unblock_type 2377 * Reference to the type of unblock command 2378 * 0 - Unblock a blocking resource 2379 * 1 - The entire cache usage is unblock 2380 * 2381 * looping_count 2382 * A count value that indicates the number of times the producer of 2383 * entries into this Ring has looped around the ring. 2384 */ 2385 2386 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0) 2387 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1) 2388 2389 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0) 2390 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16) 2391 2392 struct hal_reo_flush_timeout_list_status { 2393 struct hal_reo_status_hdr hdr; 2394 u32 info0; 2395 u32 info1; 2396 u32 rsvd0[20]; 2397 u32 info2; 2398 } __packed; 2399 2400 /* hal_reo_flush_timeout_list_status 2401 * Producer: REO 2402 * Consumer: SW 2403 * 2404 * status_hdr 2405 * Details that can link this status with the original command. It 2406 * also contains info on how long REO took to execute this command. 2407 * 2408 * error_detected 2409 * 0 - No error has been detected while executing this command 2410 * 1 - Command not properly executed and returned with error 2411 * 2412 * timeout_list_empty 2413 * When set, REO has depleted the timeout list and all entries are 2414 * gone. 2415 * 2416 * release_desc_count 2417 * Producer: SW; Consumer: REO 2418 * The number of link descriptor released 2419 * 2420 * forward_buf_count 2421 * Producer: SW; Consumer: REO 2422 * The number of buffers forwarded to the REO destination rings 2423 * 2424 * looping_count 2425 * A count value that indicates the number of times the producer of 2426 * entries into this Ring has looped around the ring. 2427 */ 2428 2429 #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0) 2430 #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0) 2431 #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0) 2432 #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0) 2433 #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(23, 0) 2434 2435 struct hal_reo_desc_thresh_reached_status { 2436 struct hal_reo_status_hdr hdr; 2437 u32 info0; 2438 u32 info1; 2439 u32 info2; 2440 u32 info3; 2441 u32 info4; 2442 u32 rsvd0[17]; 2443 u32 info5; 2444 } __packed; 2445 2446 /* hal_reo_desc_thresh_reached_status 2447 * Producer: REO 2448 * Consumer: SW 2449 * 2450 * status_hdr 2451 * Details that can link this status with the original command. It 2452 * also contains info on how long REO took to execute this command. 2453 * 2454 * threshold_index 2455 * The index of the threshold register whose value got reached 2456 * 2457 * link_descriptor_counter0 2458 * link_descriptor_counter1 2459 * link_descriptor_counter2 2460 * link_descriptor_counter_sum 2461 * Value of the respective counters at generation of this message 2462 * 2463 * looping_count 2464 * A count value that indicates the number of times the producer of 2465 * entries into this Ring has looped around the ring. 2466 */ 2467 2468 #endif /* ATH11K_HAL_DESC_H */ 2469