1 /* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Kevin Tian <kevin.tian@intel.com> 25 * Eddie Dong <eddie.dong@intel.com> 26 * 27 * Contributors: 28 * Niu Bing <bing.niu@intel.com> 29 * Zhi Wang <zhi.a.wang@intel.com> 30 * 31 */ 32 33 #ifndef _GVT_H_ 34 #define _GVT_H_ 35 36 #include "debug.h" 37 #include "hypercall.h" 38 #include "mmio.h" 39 #include "reg.h" 40 #include "interrupt.h" 41 #include "gtt.h" 42 #include "display.h" 43 #include "edid.h" 44 #include "execlist.h" 45 #include "scheduler.h" 46 #include "sched_policy.h" 47 #include "mmio_context.h" 48 #include "cmd_parser.h" 49 #include "fb_decoder.h" 50 #include "dmabuf.h" 51 #include "page_track.h" 52 53 #define GVT_MAX_VGPU 8 54 55 struct intel_gvt_host { 56 struct device *dev; 57 bool initialized; 58 int hypervisor_type; 59 struct intel_gvt_mpt *mpt; 60 }; 61 62 extern struct intel_gvt_host intel_gvt_host; 63 64 /* Describe per-platform limitations. */ 65 struct intel_gvt_device_info { 66 u32 max_support_vgpus; 67 u32 cfg_space_size; 68 u32 mmio_size; 69 u32 mmio_bar; 70 unsigned long msi_cap_offset; 71 u32 gtt_start_offset; 72 u32 gtt_entry_size; 73 u32 gtt_entry_size_shift; 74 int gmadr_bytes_in_cmd; 75 u32 max_surface_size; 76 }; 77 78 /* GM resources owned by a vGPU */ 79 struct intel_vgpu_gm { 80 u64 aperture_sz; 81 u64 hidden_sz; 82 struct drm_mm_node low_gm_node; 83 struct drm_mm_node high_gm_node; 84 }; 85 86 #define INTEL_GVT_MAX_NUM_FENCES 32 87 88 /* Fences owned by a vGPU */ 89 struct intel_vgpu_fence { 90 struct i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES]; 91 u32 base; 92 u32 size; 93 }; 94 95 struct intel_vgpu_mmio { 96 void *vreg; 97 }; 98 99 #define INTEL_GVT_MAX_BAR_NUM 4 100 101 struct intel_vgpu_pci_bar { 102 u64 size; 103 bool tracked; 104 }; 105 106 struct intel_vgpu_cfg_space { 107 unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE]; 108 struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM]; 109 }; 110 111 #define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space) 112 113 struct intel_vgpu_irq { 114 bool irq_warn_once[INTEL_GVT_EVENT_MAX]; 115 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES], 116 INTEL_GVT_EVENT_MAX); 117 }; 118 119 struct intel_vgpu_opregion { 120 bool mapped; 121 void *va; 122 u32 gfn[INTEL_GVT_OPREGION_PAGES]; 123 }; 124 125 #define vgpu_opregion(vgpu) (&(vgpu->opregion)) 126 127 struct intel_vgpu_display { 128 struct intel_vgpu_i2c_edid i2c_edid; 129 struct intel_vgpu_port ports[I915_MAX_PORTS]; 130 struct intel_vgpu_sbi sbi; 131 }; 132 133 struct vgpu_sched_ctl { 134 int weight; 135 }; 136 137 enum { 138 INTEL_VGPU_EXECLIST_SUBMISSION = 1, 139 INTEL_VGPU_GUC_SUBMISSION, 140 }; 141 142 struct intel_vgpu_submission_ops { 143 const char *name; 144 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 145 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 146 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask); 147 }; 148 149 struct intel_vgpu_submission { 150 struct intel_vgpu_execlist execlist[I915_NUM_ENGINES]; 151 struct list_head workload_q_head[I915_NUM_ENGINES]; 152 struct intel_context *shadow[I915_NUM_ENGINES]; 153 struct kmem_cache *workloads; 154 atomic_t running_workload_num; 155 union { 156 u64 i915_context_pml4; 157 u64 i915_context_pdps[GEN8_3LVL_PDPES]; 158 }; 159 DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES); 160 DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES); 161 void *ring_scan_buffer[I915_NUM_ENGINES]; 162 int ring_scan_buffer_size[I915_NUM_ENGINES]; 163 const struct intel_vgpu_submission_ops *ops; 164 int virtual_submission_interface; 165 bool active; 166 }; 167 168 struct intel_vgpu { 169 struct intel_gvt *gvt; 170 struct mutex vgpu_lock; 171 int id; 172 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */ 173 bool active; 174 bool pv_notified; 175 bool failsafe; 176 unsigned int resetting_eng; 177 178 /* Both sched_data and sched_ctl can be seen a part of the global gvt 179 * scheduler structure. So below 2 vgpu data are protected 180 * by sched_lock, not vgpu_lock. 181 */ 182 void *sched_data; 183 struct vgpu_sched_ctl sched_ctl; 184 185 struct intel_vgpu_fence fence; 186 struct intel_vgpu_gm gm; 187 struct intel_vgpu_cfg_space cfg_space; 188 struct intel_vgpu_mmio mmio; 189 struct intel_vgpu_irq irq; 190 struct intel_vgpu_gtt gtt; 191 struct intel_vgpu_opregion opregion; 192 struct intel_vgpu_display display; 193 struct intel_vgpu_submission submission; 194 struct radix_tree_root page_track_tree; 195 u32 hws_pga[I915_NUM_ENGINES]; 196 197 struct dentry *debugfs; 198 199 /* Hypervisor-specific device state. */ 200 void *vdev; 201 202 struct list_head dmabuf_obj_list_head; 203 struct mutex dmabuf_lock; 204 struct idr object_idr; 205 206 u32 scan_nonprivbb; 207 }; 208 209 static inline void *intel_vgpu_vdev(struct intel_vgpu *vgpu) 210 { 211 return vgpu->vdev; 212 } 213 214 /* validating GM healthy status*/ 215 #define vgpu_is_vm_unhealthy(ret_val) \ 216 (((ret_val) == -EBADRQC) || ((ret_val) == -EFAULT)) 217 218 struct intel_gvt_gm { 219 unsigned long vgpu_allocated_low_gm_size; 220 unsigned long vgpu_allocated_high_gm_size; 221 }; 222 223 struct intel_gvt_fence { 224 unsigned long vgpu_allocated_fence_num; 225 }; 226 227 /* Special MMIO blocks. */ 228 struct gvt_mmio_block { 229 unsigned int device; 230 i915_reg_t offset; 231 unsigned int size; 232 gvt_mmio_func read; 233 gvt_mmio_func write; 234 }; 235 236 #define INTEL_GVT_MMIO_HASH_BITS 11 237 238 struct intel_gvt_mmio { 239 u8 *mmio_attribute; 240 /* Register contains RO bits */ 241 #define F_RO (1 << 0) 242 /* Register contains graphics address */ 243 #define F_GMADR (1 << 1) 244 /* Mode mask registers with high 16 bits as the mask bits */ 245 #define F_MODE_MASK (1 << 2) 246 /* This reg can be accessed by GPU commands */ 247 #define F_CMD_ACCESS (1 << 3) 248 /* This reg has been accessed by a VM */ 249 #define F_ACCESSED (1 << 4) 250 /* This reg has been accessed through GPU commands */ 251 #define F_CMD_ACCESSED (1 << 5) 252 /* This reg could be accessed by unaligned address */ 253 #define F_UNALIGN (1 << 6) 254 /* This reg is saved/restored in context */ 255 #define F_IN_CTX (1 << 7) 256 257 struct gvt_mmio_block *mmio_block; 258 unsigned int num_mmio_block; 259 260 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS); 261 unsigned long num_tracked_mmio; 262 }; 263 264 struct intel_gvt_firmware { 265 void *cfg_space; 266 void *mmio; 267 bool firmware_loaded; 268 }; 269 270 #define NR_MAX_INTEL_VGPU_TYPES 20 271 struct intel_vgpu_type { 272 char name[16]; 273 unsigned int avail_instance; 274 unsigned int low_gm_size; 275 unsigned int high_gm_size; 276 unsigned int fence; 277 unsigned int weight; 278 enum intel_vgpu_edid resolution; 279 }; 280 281 struct intel_gvt { 282 /* GVT scope lock, protect GVT itself, and all resource currently 283 * not yet protected by special locks(vgpu and scheduler lock). 284 */ 285 struct mutex lock; 286 /* scheduler scope lock, protect gvt and vgpu schedule related data */ 287 struct mutex sched_lock; 288 289 struct intel_gt *gt; 290 struct idr vgpu_idr; /* vGPU IDR pool */ 291 292 struct intel_gvt_device_info device_info; 293 struct intel_gvt_gm gm; 294 struct intel_gvt_fence fence; 295 struct intel_gvt_mmio mmio; 296 struct intel_gvt_firmware firmware; 297 struct intel_gvt_irq irq; 298 struct intel_gvt_gtt gtt; 299 struct intel_gvt_workload_scheduler scheduler; 300 struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES]; 301 DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS); 302 struct intel_vgpu_type *types; 303 unsigned int num_types; 304 struct intel_vgpu *idle_vgpu; 305 306 struct task_struct *service_thread; 307 wait_queue_head_t service_thread_wq; 308 309 /* service_request is always used in bit operation, we should always 310 * use it with atomic bit ops so that no need to use gvt big lock. 311 */ 312 unsigned long service_request; 313 314 struct { 315 struct engine_mmio *mmio; 316 int ctx_mmio_count[I915_NUM_ENGINES]; 317 u32 *tlb_mmio_offset_list; 318 u32 tlb_mmio_offset_list_cnt; 319 u32 *mocs_mmio_offset_list; 320 u32 mocs_mmio_offset_list_cnt; 321 } engine_mmio_list; 322 323 struct dentry *debugfs_root; 324 }; 325 326 static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915) 327 { 328 return i915->gvt; 329 } 330 331 enum { 332 INTEL_GVT_REQUEST_EMULATE_VBLANK = 0, 333 334 /* Scheduling trigger by timer */ 335 INTEL_GVT_REQUEST_SCHED = 1, 336 337 /* Scheduling trigger by event */ 338 INTEL_GVT_REQUEST_EVENT_SCHED = 2, 339 }; 340 341 static inline void intel_gvt_request_service(struct intel_gvt *gvt, 342 int service) 343 { 344 set_bit(service, (void *)&gvt->service_request); 345 wake_up(&gvt->service_thread_wq); 346 } 347 348 void intel_gvt_free_firmware(struct intel_gvt *gvt); 349 int intel_gvt_load_firmware(struct intel_gvt *gvt); 350 351 /* Aperture/GM space definitions for GVT device */ 352 #define MB_TO_BYTES(mb) ((mb) << 20ULL) 353 #define BYTES_TO_MB(b) ((b) >> 20ULL) 354 355 #define HOST_LOW_GM_SIZE MB_TO_BYTES(128) 356 #define HOST_HIGH_GM_SIZE MB_TO_BYTES(384) 357 #define HOST_FENCE 4 358 359 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt) 360 361 /* Aperture/GM space definitions for GVT device */ 362 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end 363 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start 364 365 #define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total 366 #define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3) 367 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt)) 368 369 #define gvt_aperture_gmadr_base(gvt) (0) 370 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \ 371 + gvt_aperture_sz(gvt) - 1) 372 373 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \ 374 + gvt_aperture_sz(gvt)) 375 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \ 376 + gvt_hidden_sz(gvt) - 1) 377 378 #define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences) 379 380 /* Aperture/GM space definitions for vGPU */ 381 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start) 382 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start) 383 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz) 384 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz) 385 386 #define vgpu_aperture_pa_base(vgpu) \ 387 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu)) 388 389 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz) 390 391 #define vgpu_aperture_pa_end(vgpu) \ 392 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 393 394 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu)) 395 #define vgpu_aperture_gmadr_end(vgpu) \ 396 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1) 397 398 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu)) 399 #define vgpu_hidden_gmadr_end(vgpu) \ 400 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1) 401 402 #define vgpu_fence_base(vgpu) (vgpu->fence.base) 403 #define vgpu_fence_sz(vgpu) (vgpu->fence.size) 404 405 struct intel_vgpu_creation_params { 406 __u64 handle; 407 __u64 low_gm_sz; /* in MB */ 408 __u64 high_gm_sz; /* in MB */ 409 __u64 fence_sz; 410 __u64 resolution; 411 __s32 primary; 412 __u64 vgpu_id; 413 414 __u32 weight; 415 }; 416 417 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu, 418 struct intel_vgpu_creation_params *param); 419 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu); 420 void intel_vgpu_free_resource(struct intel_vgpu *vgpu); 421 void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 422 u32 fence, u64 value); 423 424 /* Macros for easily accessing vGPU virtual/shadow register. 425 Explicitly seperate use for typed MMIO reg or real offset.*/ 426 #define vgpu_vreg_t(vgpu, reg) \ 427 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 428 #define vgpu_vreg(vgpu, offset) \ 429 (*(u32 *)(vgpu->mmio.vreg + (offset))) 430 #define vgpu_vreg64_t(vgpu, reg) \ 431 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg))) 432 #define vgpu_vreg64(vgpu, offset) \ 433 (*(u64 *)(vgpu->mmio.vreg + (offset))) 434 435 #define for_each_active_vgpu(gvt, vgpu, id) \ 436 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \ 437 for_each_if(vgpu->active) 438 439 static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu, 440 u32 offset, u32 val, bool low) 441 { 442 u32 *pval; 443 444 /* BAR offset should be 32 bits algiend */ 445 offset = rounddown(offset, 4); 446 pval = (u32 *)(vgpu_cfg_space(vgpu) + offset); 447 448 if (low) { 449 /* 450 * only update bit 31 - bit 4, 451 * leave the bit 3 - bit 0 unchanged. 452 */ 453 *pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0)); 454 } else { 455 *pval = val; 456 } 457 } 458 459 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt); 460 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt); 461 462 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt); 463 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu); 464 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt, 465 struct intel_vgpu_type *type); 466 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu); 467 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu); 468 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, 469 intel_engine_mask_t engine_mask); 470 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu); 471 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu); 472 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu); 473 474 /* validating GM functions */ 475 #define vgpu_gmadr_is_aperture(vgpu, gmadr) \ 476 ((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \ 477 (gmadr <= vgpu_aperture_gmadr_end(vgpu))) 478 479 #define vgpu_gmadr_is_hidden(vgpu, gmadr) \ 480 ((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \ 481 (gmadr <= vgpu_hidden_gmadr_end(vgpu))) 482 483 #define vgpu_gmadr_is_valid(vgpu, gmadr) \ 484 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \ 485 (vgpu_gmadr_is_hidden(vgpu, gmadr)))) 486 487 #define gvt_gmadr_is_aperture(gvt, gmadr) \ 488 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \ 489 (gmadr <= gvt_aperture_gmadr_end(gvt))) 490 491 #define gvt_gmadr_is_hidden(gvt, gmadr) \ 492 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \ 493 (gmadr <= gvt_hidden_gmadr_end(gvt))) 494 495 #define gvt_gmadr_is_valid(gvt, gmadr) \ 496 (gvt_gmadr_is_aperture(gvt, gmadr) || \ 497 gvt_gmadr_is_hidden(gvt, gmadr)) 498 499 bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size); 500 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr); 501 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr); 502 int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index, 503 unsigned long *h_index); 504 int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index, 505 unsigned long *g_index); 506 507 void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu, 508 bool primary); 509 void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu); 510 511 int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset, 512 void *p_data, unsigned int bytes); 513 514 int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 515 void *p_data, unsigned int bytes); 516 517 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected); 518 519 static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar) 520 { 521 /* We are 64bit bar. */ 522 return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) & 523 PCI_BASE_ADDRESS_MEM_MASK; 524 } 525 526 void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu); 527 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu); 528 int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa); 529 530 int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci); 531 void populate_pvinfo_page(struct intel_vgpu *vgpu); 532 533 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload); 534 void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason); 535 536 struct intel_gvt_ops { 537 int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *, 538 unsigned int); 539 int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *, 540 unsigned int); 541 int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *, 542 unsigned int); 543 int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *, 544 unsigned int); 545 struct intel_vgpu *(*vgpu_create)(struct intel_gvt *, 546 struct intel_vgpu_type *); 547 void (*vgpu_destroy)(struct intel_vgpu *vgpu); 548 void (*vgpu_release)(struct intel_vgpu *vgpu); 549 void (*vgpu_reset)(struct intel_vgpu *); 550 void (*vgpu_activate)(struct intel_vgpu *); 551 void (*vgpu_deactivate)(struct intel_vgpu *); 552 struct intel_vgpu_type *(*gvt_find_vgpu_type)(struct intel_gvt *gvt, 553 const char *name); 554 bool (*get_gvt_attrs)(struct attribute_group ***intel_vgpu_type_groups); 555 int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *); 556 int (*vgpu_get_dmabuf)(struct intel_vgpu *vgpu, unsigned int); 557 int (*write_protect_handler)(struct intel_vgpu *, u64, void *, 558 unsigned int); 559 void (*emulate_hotplug)(struct intel_vgpu *vgpu, bool connected); 560 }; 561 562 563 enum { 564 GVT_FAILSAFE_UNSUPPORTED_GUEST, 565 GVT_FAILSAFE_INSUFFICIENT_RESOURCE, 566 GVT_FAILSAFE_GUEST_ERR, 567 }; 568 569 static inline void mmio_hw_access_pre(struct intel_gt *gt) 570 { 571 intel_runtime_pm_get(gt->uncore->rpm); 572 } 573 574 static inline void mmio_hw_access_post(struct intel_gt *gt) 575 { 576 intel_runtime_pm_put_unchecked(gt->uncore->rpm); 577 } 578 579 /** 580 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed 581 * @gvt: a GVT device 582 * @offset: register offset 583 * 584 */ 585 static inline void intel_gvt_mmio_set_accessed( 586 struct intel_gvt *gvt, unsigned int offset) 587 { 588 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; 589 } 590 591 /** 592 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command 593 * @gvt: a GVT device 594 * @offset: register offset 595 * 596 */ 597 static inline bool intel_gvt_mmio_is_cmd_access( 598 struct intel_gvt *gvt, unsigned int offset) 599 { 600 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; 601 } 602 603 /** 604 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned 605 * @gvt: a GVT device 606 * @offset: register offset 607 * 608 */ 609 static inline bool intel_gvt_mmio_is_unalign( 610 struct intel_gvt *gvt, unsigned int offset) 611 { 612 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; 613 } 614 615 /** 616 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command 617 * @gvt: a GVT device 618 * @offset: register offset 619 * 620 */ 621 static inline void intel_gvt_mmio_set_cmd_accessed( 622 struct intel_gvt *gvt, unsigned int offset) 623 { 624 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESSED; 625 } 626 627 /** 628 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask 629 * @gvt: a GVT device 630 * @offset: register offset 631 * 632 * Returns: 633 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't. 634 * 635 */ 636 static inline bool intel_gvt_mmio_has_mode_mask( 637 struct intel_gvt *gvt, unsigned int offset) 638 { 639 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; 640 } 641 642 /** 643 * intel_gvt_mmio_is_in_ctx - check if a MMIO has in-ctx mask 644 * @gvt: a GVT device 645 * @offset: register offset 646 * 647 * Returns: 648 * True if a MMIO has a in-context mask, false if it isn't. 649 * 650 */ 651 static inline bool intel_gvt_mmio_is_in_ctx( 652 struct intel_gvt *gvt, unsigned int offset) 653 { 654 return gvt->mmio.mmio_attribute[offset >> 2] & F_IN_CTX; 655 } 656 657 /** 658 * intel_gvt_mmio_set_in_ctx - mask a MMIO in logical context 659 * @gvt: a GVT device 660 * @offset: register offset 661 * 662 */ 663 static inline void intel_gvt_mmio_set_in_ctx( 664 struct intel_gvt *gvt, unsigned int offset) 665 { 666 gvt->mmio.mmio_attribute[offset >> 2] |= F_IN_CTX; 667 } 668 669 void intel_gvt_debugfs_add_vgpu(struct intel_vgpu *vgpu); 670 void intel_gvt_debugfs_remove_vgpu(struct intel_vgpu *vgpu); 671 void intel_gvt_debugfs_init(struct intel_gvt *gvt); 672 void intel_gvt_debugfs_clean(struct intel_gvt *gvt); 673 674 675 #include "trace.h" 676 #include "mpt.h" 677 678 #endif 679