1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * AMD SVM support 6 * 7 * Copyright (C) 2006 Qumranet, Inc. 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 9 * 10 * Authors: 11 * Yaniv Kamay <yaniv@qumranet.com> 12 * Avi Kivity <avi@qumranet.com> 13 */ 14 15 #ifndef __SVM_SVM_H 16 #define __SVM_SVM_H 17 18 #include <linux/kvm_types.h> 19 #include <linux/kvm_host.h> 20 21 #include <asm/svm.h> 22 23 static const u32 host_save_user_msrs[] = { 24 #ifdef CONFIG_X86_64 25 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE, 26 MSR_FS_BASE, 27 #endif 28 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP, 29 MSR_TSC_AUX, 30 }; 31 32 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs) 33 34 #define MSRPM_OFFSETS 16 35 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly; 36 extern bool npt_enabled; 37 38 enum { 39 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset, 40 pause filter count */ 41 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */ 42 VMCB_ASID, /* ASID */ 43 VMCB_INTR, /* int_ctl, int_vector */ 44 VMCB_NPT, /* npt_en, nCR3, gPAT */ 45 VMCB_CR, /* CR0, CR3, CR4, EFER */ 46 VMCB_DR, /* DR6, DR7 */ 47 VMCB_DT, /* GDT, IDT */ 48 VMCB_SEG, /* CS, DS, SS, ES, CPL */ 49 VMCB_CR2, /* CR2 only */ 50 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */ 51 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE, 52 * AVIC PHYSICAL_TABLE pointer, 53 * AVIC LOGICAL_TABLE pointer 54 */ 55 VMCB_DIRTY_MAX, 56 }; 57 58 /* TPR and CR2 are always written before VMRUN */ 59 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2)) 60 61 struct kvm_sev_info { 62 bool active; /* SEV enabled guest */ 63 unsigned int asid; /* ASID used for this guest */ 64 unsigned int handle; /* SEV firmware handle */ 65 int fd; /* SEV device fd */ 66 unsigned long pages_locked; /* Number of pages locked */ 67 struct list_head regions_list; /* List of registered regions */ 68 }; 69 70 struct kvm_svm { 71 struct kvm kvm; 72 73 /* Struct members for AVIC */ 74 u32 avic_vm_id; 75 struct page *avic_logical_id_table_page; 76 struct page *avic_physical_id_table_page; 77 struct hlist_node hnode; 78 79 struct kvm_sev_info sev_info; 80 }; 81 82 struct kvm_vcpu; 83 84 struct nested_state { 85 struct vmcb *hsave; 86 u64 hsave_msr; 87 u64 vm_cr_msr; 88 u64 vmcb; 89 90 /* These are the merged vectors */ 91 u32 *msrpm; 92 93 /* gpa pointers to the real vectors */ 94 u64 vmcb_msrpm; 95 u64 vmcb_iopm; 96 97 /* A VMEXIT is required but not yet emulated */ 98 bool exit_required; 99 100 /* cache for intercepts of the guest */ 101 u32 intercept_cr; 102 u32 intercept_dr; 103 u32 intercept_exceptions; 104 u64 intercept; 105 106 /* Nested Paging related state */ 107 u64 nested_cr3; 108 }; 109 110 struct vcpu_svm { 111 struct kvm_vcpu vcpu; 112 struct vmcb *vmcb; 113 unsigned long vmcb_pa; 114 struct svm_cpu_data *svm_data; 115 uint64_t asid_generation; 116 uint64_t sysenter_esp; 117 uint64_t sysenter_eip; 118 uint64_t tsc_aux; 119 120 u64 msr_decfg; 121 122 u64 next_rip; 123 124 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS]; 125 struct { 126 u16 fs; 127 u16 gs; 128 u16 ldt; 129 u64 gs_base; 130 } host; 131 132 u64 spec_ctrl; 133 /* 134 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be 135 * translated into the appropriate L2_CFG bits on the host to 136 * perform speculative control. 137 */ 138 u64 virt_spec_ctrl; 139 140 u32 *msrpm; 141 142 ulong nmi_iret_rip; 143 144 struct nested_state nested; 145 146 bool nmi_singlestep; 147 u64 nmi_singlestep_guest_rflags; 148 149 unsigned int3_injected; 150 unsigned long int3_rip; 151 152 /* cached guest cpuid flags for faster access */ 153 bool nrips_enabled : 1; 154 155 u32 ldr_reg; 156 u32 dfr_reg; 157 struct page *avic_backing_page; 158 u64 *avic_physical_id_cache; 159 bool avic_is_running; 160 161 /* 162 * Per-vcpu list of struct amd_svm_iommu_ir: 163 * This is used mainly to store interrupt remapping information used 164 * when update the vcpu affinity. This avoids the need to scan for 165 * IRTE and try to match ga_tag in the IOMMU driver. 166 */ 167 struct list_head ir_list; 168 spinlock_t ir_list_lock; 169 170 /* which host CPU was used for running this vcpu */ 171 unsigned int last_cpu; 172 }; 173 174 struct svm_cpu_data { 175 int cpu; 176 177 u64 asid_generation; 178 u32 max_asid; 179 u32 next_asid; 180 u32 min_asid; 181 struct kvm_ldttss_desc *tss_desc; 182 183 struct page *save_area; 184 struct vmcb *current_vmcb; 185 186 /* index = sev_asid, value = vmcb pointer */ 187 struct vmcb **sev_vmcbs; 188 }; 189 190 DECLARE_PER_CPU(struct svm_cpu_data *, svm_data); 191 192 void recalc_intercepts(struct vcpu_svm *svm); 193 194 static inline struct kvm_svm *to_kvm_svm(struct kvm *kvm) 195 { 196 return container_of(kvm, struct kvm_svm, kvm); 197 } 198 199 static inline void mark_all_dirty(struct vmcb *vmcb) 200 { 201 vmcb->control.clean = 0; 202 } 203 204 static inline void mark_all_clean(struct vmcb *vmcb) 205 { 206 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1) 207 & ~VMCB_ALWAYS_DIRTY_MASK; 208 } 209 210 static inline void mark_dirty(struct vmcb *vmcb, int bit) 211 { 212 vmcb->control.clean &= ~(1 << bit); 213 } 214 215 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) 216 { 217 return container_of(vcpu, struct vcpu_svm, vcpu); 218 } 219 220 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm) 221 { 222 if (is_guest_mode(&svm->vcpu)) 223 return svm->nested.hsave; 224 else 225 return svm->vmcb; 226 } 227 228 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit) 229 { 230 struct vmcb *vmcb = get_host_vmcb(svm); 231 232 vmcb->control.intercept_cr |= (1U << bit); 233 234 recalc_intercepts(svm); 235 } 236 237 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit) 238 { 239 struct vmcb *vmcb = get_host_vmcb(svm); 240 241 vmcb->control.intercept_cr &= ~(1U << bit); 242 243 recalc_intercepts(svm); 244 } 245 246 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit) 247 { 248 struct vmcb *vmcb = get_host_vmcb(svm); 249 250 return vmcb->control.intercept_cr & (1U << bit); 251 } 252 253 static inline void set_dr_intercepts(struct vcpu_svm *svm) 254 { 255 struct vmcb *vmcb = get_host_vmcb(svm); 256 257 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ) 258 | (1 << INTERCEPT_DR1_READ) 259 | (1 << INTERCEPT_DR2_READ) 260 | (1 << INTERCEPT_DR3_READ) 261 | (1 << INTERCEPT_DR4_READ) 262 | (1 << INTERCEPT_DR5_READ) 263 | (1 << INTERCEPT_DR6_READ) 264 | (1 << INTERCEPT_DR7_READ) 265 | (1 << INTERCEPT_DR0_WRITE) 266 | (1 << INTERCEPT_DR1_WRITE) 267 | (1 << INTERCEPT_DR2_WRITE) 268 | (1 << INTERCEPT_DR3_WRITE) 269 | (1 << INTERCEPT_DR4_WRITE) 270 | (1 << INTERCEPT_DR5_WRITE) 271 | (1 << INTERCEPT_DR6_WRITE) 272 | (1 << INTERCEPT_DR7_WRITE); 273 274 recalc_intercepts(svm); 275 } 276 277 static inline void clr_dr_intercepts(struct vcpu_svm *svm) 278 { 279 struct vmcb *vmcb = get_host_vmcb(svm); 280 281 vmcb->control.intercept_dr = 0; 282 283 recalc_intercepts(svm); 284 } 285 286 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit) 287 { 288 struct vmcb *vmcb = get_host_vmcb(svm); 289 290 vmcb->control.intercept_exceptions |= (1U << bit); 291 292 recalc_intercepts(svm); 293 } 294 295 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit) 296 { 297 struct vmcb *vmcb = get_host_vmcb(svm); 298 299 vmcb->control.intercept_exceptions &= ~(1U << bit); 300 301 recalc_intercepts(svm); 302 } 303 304 static inline void set_intercept(struct vcpu_svm *svm, int bit) 305 { 306 struct vmcb *vmcb = get_host_vmcb(svm); 307 308 vmcb->control.intercept |= (1ULL << bit); 309 310 recalc_intercepts(svm); 311 } 312 313 static inline void clr_intercept(struct vcpu_svm *svm, int bit) 314 { 315 struct vmcb *vmcb = get_host_vmcb(svm); 316 317 vmcb->control.intercept &= ~(1ULL << bit); 318 319 recalc_intercepts(svm); 320 } 321 322 static inline bool is_intercept(struct vcpu_svm *svm, int bit) 323 { 324 return (svm->vmcb->control.intercept & (1ULL << bit)) != 0; 325 } 326 327 static inline bool vgif_enabled(struct vcpu_svm *svm) 328 { 329 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK); 330 } 331 332 static inline void enable_gif(struct vcpu_svm *svm) 333 { 334 if (vgif_enabled(svm)) 335 svm->vmcb->control.int_ctl |= V_GIF_MASK; 336 else 337 svm->vcpu.arch.hflags |= HF_GIF_MASK; 338 } 339 340 static inline void disable_gif(struct vcpu_svm *svm) 341 { 342 if (vgif_enabled(svm)) 343 svm->vmcb->control.int_ctl &= ~V_GIF_MASK; 344 else 345 svm->vcpu.arch.hflags &= ~HF_GIF_MASK; 346 } 347 348 static inline bool gif_set(struct vcpu_svm *svm) 349 { 350 if (vgif_enabled(svm)) 351 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK); 352 else 353 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK); 354 } 355 356 /* svm.c */ 357 #define MSR_INVALID 0xffffffffU 358 359 u32 svm_msrpm_offset(u32 msr); 360 void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); 361 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); 362 int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); 363 void svm_flush_tlb(struct kvm_vcpu *vcpu, bool invalidate_gpa); 364 void disable_nmi_singlestep(struct vcpu_svm *svm); 365 366 /* nested.c */ 367 368 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */ 369 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */ 370 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */ 371 372 /* This function returns true if it is save to enable the nmi window */ 373 static inline bool nested_svm_nmi(struct vcpu_svm *svm) 374 { 375 if (!is_guest_mode(&svm->vcpu)) 376 return true; 377 378 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI))) 379 return true; 380 381 svm->vmcb->control.exit_code = SVM_EXIT_NMI; 382 svm->nested.exit_required = true; 383 384 return false; 385 } 386 387 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu) 388 { 389 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK); 390 } 391 392 void enter_svm_guest_mode(struct vcpu_svm *svm, u64 vmcb_gpa, 393 struct vmcb *nested_vmcb, struct kvm_host_map *map); 394 int nested_svm_vmrun(struct vcpu_svm *svm); 395 void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb); 396 int nested_svm_vmexit(struct vcpu_svm *svm); 397 int nested_svm_exit_handled(struct vcpu_svm *svm); 398 int nested_svm_check_permissions(struct vcpu_svm *svm); 399 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr, 400 bool has_error_code, u32 error_code); 401 int svm_check_nested_events(struct kvm_vcpu *vcpu); 402 int nested_svm_exit_special(struct vcpu_svm *svm); 403 404 /* avic.c */ 405 406 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF) 407 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 408 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) 409 410 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL) 411 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) 412 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) 413 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) 414 415 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL 416 417 extern int avic; 418 419 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data) 420 { 421 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK; 422 mark_dirty(svm->vmcb, VMCB_AVIC); 423 } 424 425 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu) 426 { 427 struct vcpu_svm *svm = to_svm(vcpu); 428 u64 *entry = svm->avic_physical_id_cache; 429 430 if (!entry) 431 return false; 432 433 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); 434 } 435 436 int avic_ga_log_notifier(u32 ga_tag); 437 void avic_vm_destroy(struct kvm *kvm); 438 int avic_vm_init(struct kvm *kvm); 439 void avic_init_vmcb(struct vcpu_svm *svm); 440 void svm_toggle_avic_for_irq_window(struct kvm_vcpu *vcpu, bool activate); 441 int avic_incomplete_ipi_interception(struct vcpu_svm *svm); 442 int avic_unaccelerated_access_interception(struct vcpu_svm *svm); 443 int avic_init_vcpu(struct vcpu_svm *svm); 444 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); 445 void avic_vcpu_put(struct kvm_vcpu *vcpu); 446 void avic_post_state_restore(struct kvm_vcpu *vcpu); 447 void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu); 448 void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); 449 bool svm_check_apicv_inhibit_reasons(ulong bit); 450 void svm_pre_update_apicv_exec_ctrl(struct kvm *kvm, bool activate); 451 void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap); 452 void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr); 453 void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr); 454 int svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec); 455 bool svm_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu); 456 int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 457 uint32_t guest_irq, bool set); 458 void svm_vcpu_blocking(struct kvm_vcpu *vcpu); 459 void svm_vcpu_unblocking(struct kvm_vcpu *vcpu); 460 461 /* sev.c */ 462 463 extern unsigned int max_sev_asid; 464 465 static inline bool sev_guest(struct kvm *kvm) 466 { 467 #ifdef CONFIG_KVM_AMD_SEV 468 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info; 469 470 return sev->active; 471 #else 472 return false; 473 #endif 474 } 475 476 static inline bool svm_sev_enabled(void) 477 { 478 return IS_ENABLED(CONFIG_KVM_AMD_SEV) ? max_sev_asid : 0; 479 } 480 481 void sev_vm_destroy(struct kvm *kvm); 482 int svm_mem_enc_op(struct kvm *kvm, void __user *argp); 483 int svm_register_enc_region(struct kvm *kvm, 484 struct kvm_enc_region *range); 485 int svm_unregister_enc_region(struct kvm *kvm, 486 struct kvm_enc_region *range); 487 void pre_sev_run(struct vcpu_svm *svm, int cpu); 488 int __init sev_hardware_setup(void); 489 void sev_hardware_teardown(void); 490 491 #endif 492