1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for NXP Layerscape-1028A family SoC. 4 * 5 * Copyright 2018 NXP 6 * 7 * Harninder Rai <harninder.rai@nxp.com> 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "fsl,ls1028a"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a72"; 27 reg = <0x0>; 28 enable-method = "psci"; 29 clocks = <&clockgen 1 0>; 30 next-level-cache = <&l2>; 31 cpu-idle-states = <&CPU_PW20>; 32 #cooling-cells = <2>; 33 }; 34 35 cpu1: cpu@1 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a72"; 38 reg = <0x1>; 39 enable-method = "psci"; 40 clocks = <&clockgen 1 0>; 41 next-level-cache = <&l2>; 42 cpu-idle-states = <&CPU_PW20>; 43 #cooling-cells = <2>; 44 }; 45 46 l2: l2-cache { 47 compatible = "cache"; 48 }; 49 }; 50 51 idle-states { 52 /* 53 * PSCI node is not added default, U-boot will add missing 54 * parts if it determines to use PSCI. 55 */ 56 entry-method = "arm,psci"; 57 58 CPU_PW20: cpu-pw20 { 59 compatible = "arm,idle-state"; 60 idle-state-name = "PW20"; 61 arm,psci-suspend-param = <0x0>; 62 entry-latency-us = <2000>; 63 exit-latency-us = <2000>; 64 min-residency-us = <6000>; 65 }; 66 }; 67 68 sysclk: clock-sysclk { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <100000000>; 72 clock-output-names = "sysclk"; 73 }; 74 75 osc_27m: clock-osc-27m { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <27000000>; 79 clock-output-names = "phy_27m"; 80 }; 81 82 dpclk: clock-controller@f1f0000 { 83 compatible = "fsl,ls1028a-plldig"; 84 reg = <0x0 0xf1f0000 0x0 0xffff>; 85 #clock-cells = <0>; 86 clocks = <&osc_27m>; 87 }; 88 89 reboot { 90 compatible ="syscon-reboot"; 91 regmap = <&rst>; 92 offset = <0xb0>; 93 mask = <0x02>; 94 }; 95 96 timer { 97 compatible = "arm,armv8-timer"; 98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 99 IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 101 IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 103 IRQ_TYPE_LEVEL_LOW)>, 104 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 105 IRQ_TYPE_LEVEL_LOW)>; 106 }; 107 108 pmu { 109 compatible = "arm,cortex-a72-pmu"; 110 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 111 }; 112 113 gic: interrupt-controller@6000000 { 114 compatible= "arm,gic-v3"; 115 #address-cells = <2>; 116 #size-cells = <2>; 117 ranges; 118 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 119 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ 120 #interrupt-cells= <3>; 121 interrupt-controller; 122 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | 123 IRQ_TYPE_LEVEL_LOW)>; 124 its: gic-its@6020000 { 125 compatible = "arm,gic-v3-its"; 126 msi-controller; 127 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ 128 }; 129 }; 130 131 thermal-zones { 132 core-cluster { 133 polling-delay-passive = <1000>; 134 polling-delay = <5000>; 135 thermal-sensors = <&tmu 0>; 136 137 trips { 138 core_cluster_alert: core-cluster-alert { 139 temperature = <85000>; 140 hysteresis = <2000>; 141 type = "passive"; 142 }; 143 144 core_cluster_crit: core-cluster-crit { 145 temperature = <95000>; 146 hysteresis = <2000>; 147 type = "critical"; 148 }; 149 }; 150 151 cooling-maps { 152 map0 { 153 trip = <&core_cluster_alert>; 154 cooling-device = 155 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 156 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 157 }; 158 }; 159 }; 160 }; 161 162 soc: soc { 163 compatible = "simple-bus"; 164 #address-cells = <2>; 165 #size-cells = <2>; 166 ranges; 167 168 ddr: memory-controller@1080000 { 169 compatible = "fsl,qoriq-memory-controller"; 170 reg = <0x0 0x1080000 0x0 0x1000>; 171 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 172 big-endian; 173 }; 174 175 dcfg: syscon@1e00000 { 176 compatible = "fsl,ls1028a-dcfg", "syscon"; 177 reg = <0x0 0x1e00000 0x0 0x10000>; 178 little-endian; 179 }; 180 181 rst: syscon@1e60000 { 182 compatible = "syscon"; 183 reg = <0x0 0x1e60000 0x0 0x10000>; 184 little-endian; 185 }; 186 187 scfg: syscon@1fc0000 { 188 compatible = "fsl,ls1028a-scfg", "syscon"; 189 reg = <0x0 0x1fc0000 0x0 0x10000>; 190 big-endian; 191 }; 192 193 clockgen: clock-controller@1300000 { 194 compatible = "fsl,ls1028a-clockgen"; 195 reg = <0x0 0x1300000 0x0 0xa0000>; 196 #clock-cells = <2>; 197 clocks = <&sysclk>; 198 }; 199 200 i2c0: i2c@2000000 { 201 compatible = "fsl,vf610-i2c"; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 reg = <0x0 0x2000000 0x0 0x10000>; 205 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&clockgen 4 3>; 207 status = "disabled"; 208 }; 209 210 i2c1: i2c@2010000 { 211 compatible = "fsl,vf610-i2c"; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 reg = <0x0 0x2010000 0x0 0x10000>; 215 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 216 clocks = <&clockgen 4 3>; 217 status = "disabled"; 218 }; 219 220 i2c2: i2c@2020000 { 221 compatible = "fsl,vf610-i2c"; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 reg = <0x0 0x2020000 0x0 0x10000>; 225 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&clockgen 4 3>; 227 status = "disabled"; 228 }; 229 230 i2c3: i2c@2030000 { 231 compatible = "fsl,vf610-i2c"; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 reg = <0x0 0x2030000 0x0 0x10000>; 235 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 236 clocks = <&clockgen 4 3>; 237 status = "disabled"; 238 }; 239 240 i2c4: i2c@2040000 { 241 compatible = "fsl,vf610-i2c"; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 reg = <0x0 0x2040000 0x0 0x10000>; 245 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 246 clocks = <&clockgen 4 3>; 247 status = "disabled"; 248 }; 249 250 i2c5: i2c@2050000 { 251 compatible = "fsl,vf610-i2c"; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 reg = <0x0 0x2050000 0x0 0x10000>; 255 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 256 clocks = <&clockgen 4 3>; 257 status = "disabled"; 258 }; 259 260 i2c6: i2c@2060000 { 261 compatible = "fsl,vf610-i2c"; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 reg = <0x0 0x2060000 0x0 0x10000>; 265 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 266 clocks = <&clockgen 4 3>; 267 status = "disabled"; 268 }; 269 270 i2c7: i2c@2070000 { 271 compatible = "fsl,vf610-i2c"; 272 #address-cells = <1>; 273 #size-cells = <0>; 274 reg = <0x0 0x2070000 0x0 0x10000>; 275 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 276 clocks = <&clockgen 4 3>; 277 status = "disabled"; 278 }; 279 280 fspi: spi@20c0000 { 281 compatible = "nxp,lx2160a-fspi"; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 reg = <0x0 0x20c0000 0x0 0x10000>, 285 <0x0 0x20000000 0x0 0x10000000>; 286 reg-names = "fspi_base", "fspi_mmap"; 287 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 288 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 289 clock-names = "fspi_en", "fspi"; 290 status = "disabled"; 291 }; 292 293 esdhc: mmc@2140000 { 294 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 295 reg = <0x0 0x2140000 0x0 0x10000>; 296 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 297 clock-frequency = <0>; /* fixed up by bootloader */ 298 clocks = <&clockgen 2 1>; 299 voltage-ranges = <1800 1800 3300 3300>; 300 sdhci,auto-cmd12; 301 little-endian; 302 bus-width = <4>; 303 status = "disabled"; 304 }; 305 306 esdhc1: mmc@2150000 { 307 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; 308 reg = <0x0 0x2150000 0x0 0x10000>; 309 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 310 clock-frequency = <0>; /* fixed up by bootloader */ 311 clocks = <&clockgen 2 1>; 312 voltage-ranges = <1800 1800 3300 3300>; 313 sdhci,auto-cmd12; 314 broken-cd; 315 little-endian; 316 bus-width = <4>; 317 status = "disabled"; 318 }; 319 320 duart0: serial@21c0500 { 321 compatible = "fsl,ns16550", "ns16550a"; 322 reg = <0x00 0x21c0500 0x0 0x100>; 323 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&clockgen 4 1>; 325 status = "disabled"; 326 }; 327 328 duart1: serial@21c0600 { 329 compatible = "fsl,ns16550", "ns16550a"; 330 reg = <0x00 0x21c0600 0x0 0x100>; 331 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 332 clocks = <&clockgen 4 1>; 333 status = "disabled"; 334 }; 335 336 edma0: dma-controller@22c0000 { 337 #dma-cells = <2>; 338 compatible = "fsl,ls1028a-edma"; 339 reg = <0x0 0x22c0000 0x0 0x10000>, 340 <0x0 0x22d0000 0x0 0x10000>, 341 <0x0 0x22e0000 0x0 0x10000>; 342 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 344 interrupt-names = "edma-tx", "edma-err"; 345 dma-channels = <32>; 346 clock-names = "dmamux0", "dmamux1"; 347 clocks = <&clockgen 4 1>, 348 <&clockgen 4 1>; 349 }; 350 351 gpio1: gpio@2300000 { 352 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 353 reg = <0x0 0x2300000 0x0 0x10000>; 354 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 355 gpio-controller; 356 #gpio-cells = <2>; 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 little-endian; 360 }; 361 362 gpio2: gpio@2310000 { 363 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 364 reg = <0x0 0x2310000 0x0 0x10000>; 365 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 366 gpio-controller; 367 #gpio-cells = <2>; 368 interrupt-controller; 369 #interrupt-cells = <2>; 370 little-endian; 371 }; 372 373 gpio3: gpio@2320000 { 374 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; 375 reg = <0x0 0x2320000 0x0 0x10000>; 376 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 377 gpio-controller; 378 #gpio-cells = <2>; 379 interrupt-controller; 380 #interrupt-cells = <2>; 381 little-endian; 382 }; 383 384 usb0: usb@3100000 { 385 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 386 reg = <0x0 0x3100000 0x0 0x10000>; 387 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 388 dr_mode = "host"; 389 snps,dis_rxdet_inp3_quirk; 390 snps,quirk-frame-length-adjustment = <0x20>; 391 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 392 }; 393 394 usb1: usb@3110000 { 395 compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; 396 reg = <0x0 0x3110000 0x0 0x10000>; 397 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 398 dr_mode = "host"; 399 snps,dis_rxdet_inp3_quirk; 400 snps,quirk-frame-length-adjustment = <0x20>; 401 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 402 }; 403 404 sata: sata@3200000 { 405 compatible = "fsl,ls1028a-ahci"; 406 reg = <0x0 0x3200000 0x0 0x10000>, 407 <0x7 0x100520 0x0 0x4>; 408 reg-names = "ahci", "sata-ecc"; 409 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 410 clocks = <&clockgen 4 1>; 411 status = "disabled"; 412 }; 413 414 smmu: iommu@5000000 { 415 compatible = "arm,mmu-500"; 416 reg = <0 0x5000000 0 0x800000>; 417 #global-interrupts = <8>; 418 #iommu-cells = <1>; 419 stream-match-mask = <0x7c00>; 420 /* global secure fault */ 421 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 422 /* combined secure interrupt */ 423 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 424 /* global non-secure fault */ 425 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 426 /* combined non-secure interrupt */ 427 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 428 /* performance counter interrupts 0-7 */ 429 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 431 /* per context interrupt, 64 interrupts */ 432 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 434 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 436 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 437 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 464 }; 465 466 crypto: crypto@8000000 { 467 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 468 fsl,sec-era = <10>; 469 #address-cells = <1>; 470 #size-cells = <1>; 471 ranges = <0x0 0x00 0x8000000 0x100000>; 472 reg = <0x00 0x8000000 0x0 0x100000>; 473 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 474 dma-coherent; 475 476 sec_jr0: jr@10000 { 477 compatible = "fsl,sec-v5.0-job-ring", 478 "fsl,sec-v4.0-job-ring"; 479 reg = <0x10000 0x10000>; 480 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 481 }; 482 483 sec_jr1: jr@20000 { 484 compatible = "fsl,sec-v5.0-job-ring", 485 "fsl,sec-v4.0-job-ring"; 486 reg = <0x20000 0x10000>; 487 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 488 }; 489 490 sec_jr2: jr@30000 { 491 compatible = "fsl,sec-v5.0-job-ring", 492 "fsl,sec-v4.0-job-ring"; 493 reg = <0x30000 0x10000>; 494 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 495 }; 496 497 sec_jr3: jr@40000 { 498 compatible = "fsl,sec-v5.0-job-ring", 499 "fsl,sec-v4.0-job-ring"; 500 reg = <0x40000 0x10000>; 501 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 502 }; 503 }; 504 505 qdma: dma-controller@8380000 { 506 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; 507 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ 508 <0x0 0x8390000 0x0 0x10000>, /* Status regs */ 509 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ 510 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 515 interrupt-names = "qdma-error", "qdma-queue0", 516 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 517 dma-channels = <8>; 518 block-number = <1>; 519 block-offset = <0x10000>; 520 fsl,dma-queues = <2>; 521 status-sizes = <64>; 522 queue-sizes = <64 64>; 523 }; 524 525 cluster1_core0_watchdog: watchdog@c000000 { 526 compatible = "arm,sp805", "arm,primecell"; 527 reg = <0x0 0xc000000 0x0 0x1000>; 528 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 529 clock-names = "apb_pclk", "wdog_clk"; 530 }; 531 532 cluster1_core1_watchdog: watchdog@c010000 { 533 compatible = "arm,sp805", "arm,primecell"; 534 reg = <0x0 0xc010000 0x0 0x1000>; 535 clocks = <&clockgen 4 15>, <&clockgen 4 15>; 536 clock-names = "apb_pclk", "wdog_clk"; 537 }; 538 539 sai1: audio-controller@f100000 { 540 #sound-dai-cells = <0>; 541 compatible = "fsl,vf610-sai"; 542 reg = <0x0 0xf100000 0x0 0x10000>; 543 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 545 <&clockgen 4 1>, <&clockgen 4 1>; 546 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 547 dma-names = "tx", "rx"; 548 dmas = <&edma0 1 4>, 549 <&edma0 1 3>; 550 fsl,sai-asynchronous; 551 status = "disabled"; 552 }; 553 554 sai2: audio-controller@f110000 { 555 #sound-dai-cells = <0>; 556 compatible = "fsl,vf610-sai"; 557 reg = <0x0 0xf110000 0x0 0x10000>; 558 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 560 <&clockgen 4 1>, <&clockgen 4 1>; 561 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 562 dma-names = "tx", "rx"; 563 dmas = <&edma0 1 6>, 564 <&edma0 1 5>; 565 fsl,sai-asynchronous; 566 status = "disabled"; 567 }; 568 569 sai3: audio-controller@f120000 { 570 #sound-dai-cells = <0>; 571 compatible = "fsl,vf610-sai"; 572 reg = <0x0 0xf120000 0x0 0x10000>; 573 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 575 <&clockgen 4 1>, <&clockgen 4 1>; 576 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 577 dma-names = "tx", "rx"; 578 dmas = <&edma0 1 8>, 579 <&edma0 1 7>; 580 fsl,sai-asynchronous; 581 status = "disabled"; 582 }; 583 584 sai4: audio-controller@f130000 { 585 #sound-dai-cells = <0>; 586 compatible = "fsl,vf610-sai"; 587 reg = <0x0 0xf130000 0x0 0x10000>; 588 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 590 <&clockgen 4 1>, <&clockgen 4 1>; 591 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 592 dma-names = "tx", "rx"; 593 dmas = <&edma0 1 10>, 594 <&edma0 1 9>; 595 fsl,sai-asynchronous; 596 status = "disabled"; 597 }; 598 599 sai5: audio-controller@f140000 { 600 #sound-dai-cells = <0>; 601 compatible = "fsl,vf610-sai"; 602 reg = <0x0 0xf140000 0x0 0x10000>; 603 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 605 <&clockgen 4 1>, <&clockgen 4 1>; 606 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 607 dma-names = "tx", "rx"; 608 dmas = <&edma0 1 12>, 609 <&edma0 1 11>; 610 fsl,sai-asynchronous; 611 status = "disabled"; 612 }; 613 614 sai6: audio-controller@f150000 { 615 #sound-dai-cells = <0>; 616 compatible = "fsl,vf610-sai"; 617 reg = <0x0 0xf150000 0x0 0x10000>; 618 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 619 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 620 <&clockgen 4 1>, <&clockgen 4 1>; 621 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 622 dma-names = "tx", "rx"; 623 dmas = <&edma0 1 14>, 624 <&edma0 1 13>; 625 fsl,sai-asynchronous; 626 status = "disabled"; 627 }; 628 629 tmu: tmu@1f80000 { 630 compatible = "fsl,qoriq-tmu"; 631 reg = <0x0 0x1f80000 0x0 0x10000>; 632 interrupts = <0 23 0x4>; 633 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 634 fsl,tmu-calibration = <0x00000000 0x00000024 635 0x00000001 0x0000002b 636 0x00000002 0x00000031 637 0x00000003 0x00000038 638 0x00000004 0x0000003f 639 0x00000005 0x00000045 640 0x00000006 0x0000004c 641 0x00000007 0x00000053 642 0x00000008 0x00000059 643 0x00000009 0x00000060 644 0x0000000a 0x00000066 645 0x0000000b 0x0000006d 646 647 0x00010000 0x0000001c 648 0x00010001 0x00000024 649 0x00010002 0x0000002c 650 0x00010003 0x00000035 651 0x00010004 0x0000003d 652 0x00010005 0x00000045 653 0x00010006 0x0000004d 654 0x00010007 0x00000055 655 0x00010008 0x0000005e 656 0x00010009 0x00000066 657 0x0001000a 0x0000006e 658 659 0x00020000 0x00000018 660 0x00020001 0x00000022 661 0x00020002 0x0000002d 662 0x00020003 0x00000038 663 0x00020004 0x00000043 664 0x00020005 0x0000004d 665 0x00020006 0x00000058 666 0x00020007 0x00000063 667 0x00020008 0x0000006e 668 669 0x00030000 0x00000010 670 0x00030001 0x0000001c 671 0x00030002 0x00000029 672 0x00030003 0x00000036 673 0x00030004 0x00000042 674 0x00030005 0x0000004f 675 0x00030006 0x0000005b 676 0x00030007 0x00000068>; 677 little-endian; 678 #thermal-sensor-cells = <1>; 679 }; 680 681 pcie@1f0000000 { /* Integrated Endpoint Root Complex */ 682 compatible = "pci-host-ecam-generic"; 683 reg = <0x01 0xf0000000 0x0 0x100000>; 684 #address-cells = <3>; 685 #size-cells = <2>; 686 #interrupt-cells = <1>; 687 msi-parent = <&its>; 688 device_type = "pci"; 689 bus-range = <0x0 0x0>; 690 dma-coherent; 691 msi-map = <0 &its 0x17 0xe>; 692 iommu-map = <0 &smmu 0x17 0xe>; 693 /* PF0-6 BAR0 - non-prefetchable memory */ 694 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000 695 /* PF0-6 BAR2 - prefetchable memory */ 696 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000 697 /* PF0: VF0-1 BAR0 - non-prefetchable memory */ 698 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000 699 /* PF0: VF0-1 BAR2 - prefetchable memory */ 700 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000 701 /* PF1: VF0-1 BAR0 - non-prefetchable memory */ 702 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000 703 /* PF1: VF0-1 BAR2 - prefetchable memory */ 704 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>; 705 706 enetc_port0: ethernet@0,0 { 707 compatible = "fsl,enetc"; 708 reg = <0x000000 0 0 0 0>; 709 }; 710 enetc_port1: ethernet@0,1 { 711 compatible = "fsl,enetc"; 712 reg = <0x000100 0 0 0 0>; 713 }; 714 enetc_mdio_pf3: mdio@0,3 { 715 compatible = "fsl,enetc-mdio"; 716 reg = <0x000300 0 0 0 0>; 717 #address-cells = <1>; 718 #size-cells = <0>; 719 }; 720 ethernet@0,4 { 721 compatible = "fsl,enetc-ptp"; 722 reg = <0x000400 0 0 0 0>; 723 clocks = <&clockgen 4 0>; 724 little-endian; 725 }; 726 }; 727 }; 728 729 malidp0: display@f080000 { 730 compatible = "arm,mali-dp500"; 731 reg = <0x0 0xf080000 0x0 0x10000>; 732 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 733 <0 223 IRQ_TYPE_LEVEL_HIGH>; 734 interrupt-names = "DE", "SE"; 735 clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>, 736 <&clockgen 2 2>; 737 clock-names = "pxlclk", "mclk", "aclk", "pclk"; 738 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; 739 arm,malidp-arqos-value = <0xd000d000>; 740 741 port { 742 dp0_out: endpoint { 743 744 }; 745 }; 746 }; 747}; 748