1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI SoC Ethernet Switch Controller (CPSW) Device Tree Bindings
8
9maintainers:
10  - Grygorii Strashko <grygorii.strashko@ti.com>
11  - Sekhar Nori <nsekhar@ti.com>
12
13description:
14  The 3-port switch gigabit ethernet subsystem provides ethernet packet
15  communication and can be configured as an ethernet switch. It provides the
16  gigabit media independent interface (GMII),reduced gigabit media
17  independent interface (RGMII), reduced media independent interface (RMII),
18  the management data input output (MDIO) for physical layer device (PHY)
19  management.
20
21properties:
22  compatible:
23    oneOf:
24      - const: ti,cpsw-switch
25      - items:
26         - const: ti,am335x-cpsw-switch
27         - const: ti,cpsw-switch
28      - items:
29        - const: ti,am4372-cpsw-switch
30        - const: ti,cpsw-switch
31      - items:
32        - const: ti,dra7-cpsw-switch
33        - const: ti,cpsw-switch
34
35  reg:
36    maxItems: 1
37    description:
38       The physical base address and size of full the CPSW module IO range
39
40  ranges: true
41
42  clocks:
43    maxItems: 1
44    description: CPSW functional clock
45
46  clock-names:
47    items:
48      - const: fck
49
50  interrupts:
51    items:
52      - description: RX_THRESH interrupt
53      - description: RX interrupt
54      - description: TX interrupt
55      - description: MISC interrupt
56
57  interrupt-names:
58    items:
59      - const: "rx_thresh"
60      - const: "rx"
61      - const: "tx"
62      - const: "misc"
63
64  pinctrl-names: true
65
66  syscon:
67    $ref: /schemas/types.yaml#definitions/phandle
68    description:
69      Phandle to the system control device node which provides access to
70      efuse IO range with MAC addresses
71
72  ethernet-ports:
73    type: object
74    properties:
75      '#address-cells':
76        const: 1
77      '#size-cells':
78        const: 0
79
80    patternProperties:
81      "^port@[0-9]+$":
82          type: object
83          description: CPSW external ports
84
85          allOf:
86            - $ref: ethernet-controller.yaml#
87
88          properties:
89            reg:
90              items:
91                - enum: [1, 2]
92              description: CPSW port number
93
94            phys:
95              maxItems: 1
96              description:  phandle on phy-gmii-sel PHY
97
98            label:
99              description: label associated with this port
100
101            ti,dual-emac-pvid:
102              allOf:
103                - $ref: /schemas/types.yaml#/definitions/uint32
104              minimum: 1
105              maximum: 1024
106              description:
107                Specifies default PORT VID to be used to segregate
108                ports. Default value - CPSW port number.
109
110          required:
111            - reg
112            - phys
113
114  mdio:
115    type: object
116    allOf:
117      - $ref: "ti,davinci-mdio.yaml#"
118    description:
119      CPSW MDIO bus.
120
121  cpts:
122    type: object
123    description:
124      The Common Platform Time Sync (CPTS) module
125
126    properties:
127      clocks:
128        maxItems: 1
129        description: CPTS reference clock
130
131      clock-names:
132        items:
133          - const: cpts
134
135      cpts_clock_mult:
136        $ref: /schemas/types.yaml#/definitions/uint32
137        description:
138          Numerator to convert input clock ticks into ns
139
140      cpts_clock_shift:
141        $ref: /schemas/types.yaml#/definitions/uint32
142        description:
143          Denominator to convert input clock ticks into ns.
144          Mult and shift will be calculated basing on CPTS rftclk frequency if
145          both cpts_clock_shift and cpts_clock_mult properties are not provided.
146
147    required:
148      - clocks
149      - clock-names
150
151required:
152  - compatible
153  - reg
154  - ranges
155  - clocks
156  - clock-names
157  - interrupts
158  - interrupt-names
159  - '#address-cells'
160  - '#size-cells'
161
162examples:
163  - |
164    #include <dt-bindings/interrupt-controller/irq.h>
165    #include <dt-bindings/interrupt-controller/arm-gic.h>
166    #include <dt-bindings/clock/dra7.h>
167
168    mac_sw: switch@0 {
169        compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
170        reg = <0x0 0x4000>;
171        ranges = <0 0 0x4000>;
172        clocks = <&gmac_main_clk>;
173        clock-names = "fck";
174        #address-cells = <1>;
175        #size-cells = <1>;
176        syscon = <&scm_conf>;
177        inctrl-names = "default", "sleep";
178
179        interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
180                     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
181                     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
182                     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
183        interrupt-names = "rx_thresh", "rx", "tx", "misc";
184
185        ethernet-ports {
186                #address-cells = <1>;
187                #size-cells = <0>;
188
189                cpsw_port1: port@1 {
190                        reg = <1>;
191                        label = "port1";
192                        mac-address = [ 00 00 00 00 00 00 ];
193                        phys = <&phy_gmii_sel 1>;
194                        phy-handle = <&ethphy0_sw>;
195                        phy-mode = "rgmii";
196                        ti,dual-emac-pvid = <1>;
197                };
198
199                cpsw_port2: port@2 {
200                        reg = <2>;
201                        label = "wan";
202                        mac-address = [ 00 00 00 00 00 00 ];
203                        phys = <&phy_gmii_sel 2>;
204                        phy-handle = <&ethphy1_sw>;
205                        phy-mode = "rgmii";
206                        ti,dual-emac-pvid = <2>;
207                };
208        };
209
210        davinci_mdio_sw: mdio@1000 {
211                compatible = "ti,cpsw-mdio","ti,davinci_mdio";
212                reg = <0x1000 0x100>;
213                clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
214                clock-names = "fck";
215                #address-cells = <1>;
216                #size-cells = <0>;
217                bus_freq = <1000000>;
218
219                ethphy0_sw: ethernet-phy@0 {
220                        reg = <0>;
221                };
222
223                ethphy1_sw: ethernet-phy@1 {
224                        reg = <1>;
225                };
226        };
227
228        cpts {
229                clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
230                clock-names = "cpts";
231        };
232    };
233