1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* 4 * This file contains definitions from Hyper-V Hypervisor Top-Level Functional 5 * Specification (TLFS): 6 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs 7 */ 8 9 #ifndef _ASM_X86_HYPERV_TLFS_H 10 #define _ASM_X86_HYPERV_TLFS_H 11 12 #include <linux/types.h> 13 #include <asm/page.h> 14 /* 15 * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent 16 * is set by CPUID(HvCpuIdFunctionVersionAndFeatures). 17 */ 18 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000 19 #define HYPERV_CPUID_INTERFACE 0x40000001 20 #define HYPERV_CPUID_VERSION 0x40000002 21 #define HYPERV_CPUID_FEATURES 0x40000003 22 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004 23 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005 24 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A 25 26 #define HYPERV_HYPERVISOR_PRESENT_BIT 0x80000000 27 #define HYPERV_CPUID_MIN 0x40000005 28 #define HYPERV_CPUID_MAX 0x4000ffff 29 30 /* 31 * Aliases for Group A features that have X64 in the name. 32 * On x86/x64 these are HYPERV_CPUID_FEATURES.EAX bits. 33 */ 34 35 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE \ 36 HV_MSR_VP_RUNTIME_AVAILABLE 37 #define HV_X64_MSR_SYNIC_AVAILABLE \ 38 HV_MSR_SYNIC_AVAILABLE 39 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE \ 40 HV_MSR_APIC_ACCESS_AVAILABLE 41 #define HV_X64_MSR_HYPERCALL_AVAILABLE \ 42 HV_MSR_HYPERCALL_AVAILABLE 43 #define HV_X64_MSR_VP_INDEX_AVAILABLE \ 44 HV_MSR_VP_INDEX_AVAILABLE 45 #define HV_X64_MSR_RESET_AVAILABLE \ 46 HV_MSR_RESET_AVAILABLE 47 #define HV_X64_MSR_GUEST_IDLE_AVAILABLE \ 48 HV_MSR_GUEST_IDLE_AVAILABLE 49 #define HV_X64_ACCESS_FREQUENCY_MSRS \ 50 HV_ACCESS_FREQUENCY_MSRS 51 #define HV_X64_ACCESS_REENLIGHTENMENT \ 52 HV_ACCESS_REENLIGHTENMENT 53 #define HV_X64_ACCESS_TSC_INVARIANT \ 54 HV_ACCESS_TSC_INVARIANT 55 56 /* 57 * Aliases for Group B features that have X64 in the name. 58 * On x86/x64 these are HYPERV_CPUID_FEATURES.EBX bits. 59 */ 60 #define HV_X64_POST_MESSAGES HV_POST_MESSAGES 61 #define HV_X64_SIGNAL_EVENTS HV_SIGNAL_EVENTS 62 63 /* 64 * Group D Features. The bit assignments are custom to each architecture. 65 * On x86/x64 these are HYPERV_CPUID_FEATURES.EDX bits. 66 */ 67 /* The MWAIT instruction is available (per section MONITOR / MWAIT) */ 68 #define HV_X64_MWAIT_AVAILABLE BIT(0) 69 /* Guest debugging support is available */ 70 #define HV_X64_GUEST_DEBUGGING_AVAILABLE BIT(1) 71 /* Performance Monitor support is available*/ 72 #define HV_X64_PERF_MONITOR_AVAILABLE BIT(2) 73 /* Support for physical CPU dynamic partitioning events is available*/ 74 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE BIT(3) 75 /* 76 * Support for passing hypercall input parameter block via XMM 77 * registers is available 78 */ 79 #define HV_X64_HYPERCALL_PARAMS_XMM_AVAILABLE BIT(4) 80 /* Support for a virtual guest idle state is available */ 81 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE BIT(5) 82 /* Frequency MSRs available */ 83 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE BIT(8) 84 /* Crash MSR available */ 85 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(10) 86 /* Support for debug MSRs available */ 87 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE BIT(11) 88 /* stimer Direct Mode is available */ 89 #define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(19) 90 91 /* 92 * Implementation recommendations. Indicates which behaviors the hypervisor 93 * recommends the OS implement for optimal performance. 94 * These are HYPERV_CPUID_ENLIGHTMENT_INFO.EAX bits. 95 */ 96 /* 97 * Recommend using hypercall for address space switches rather 98 * than MOV to CR3 instruction 99 */ 100 #define HV_X64_AS_SWITCH_RECOMMENDED BIT(0) 101 /* Recommend using hypercall for local TLB flushes rather 102 * than INVLPG or MOV to CR3 instructions */ 103 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED BIT(1) 104 /* 105 * Recommend using hypercall for remote TLB flushes rather 106 * than inter-processor interrupts 107 */ 108 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED BIT(2) 109 /* 110 * Recommend using MSRs for accessing APIC registers 111 * EOI, ICR and TPR rather than their memory-mapped counterparts 112 */ 113 #define HV_X64_APIC_ACCESS_RECOMMENDED BIT(3) 114 /* Recommend using the hypervisor-provided MSR to initiate a system RESET */ 115 #define HV_X64_SYSTEM_RESET_RECOMMENDED BIT(4) 116 /* 117 * Recommend using relaxed timing for this partition. If used, 118 * the VM should disable any watchdog timeouts that rely on the 119 * timely delivery of external interrupts 120 */ 121 #define HV_X64_RELAXED_TIMING_RECOMMENDED BIT(5) 122 123 /* 124 * Recommend not using Auto End-Of-Interrupt feature 125 */ 126 #define HV_DEPRECATING_AEOI_RECOMMENDED BIT(9) 127 128 /* 129 * Recommend using cluster IPI hypercalls. 130 */ 131 #define HV_X64_CLUSTER_IPI_RECOMMENDED BIT(10) 132 133 /* Recommend using the newer ExProcessorMasks interface */ 134 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED BIT(11) 135 136 /* Recommend using enlightened VMCS */ 137 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED BIT(14) 138 139 /* 140 * Virtual processor will never share a physical core with another virtual 141 * processor, except for virtual processors that are reported as sibling SMT 142 * threads. 143 */ 144 #define HV_X64_NO_NONARCH_CORESHARING BIT(18) 145 146 /* Nested features. These are HYPERV_CPUID_NESTED_FEATURES.EAX bits. */ 147 #define HV_X64_NESTED_DIRECT_FLUSH BIT(17) 148 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH BIT(18) 149 #define HV_X64_NESTED_MSR_BITMAP BIT(19) 150 151 /* Hyper-V specific model specific registers (MSRs) */ 152 153 /* MSR used to identify the guest OS. */ 154 #define HV_X64_MSR_GUEST_OS_ID 0x40000000 155 156 /* MSR used to setup pages used to communicate with the hypervisor. */ 157 #define HV_X64_MSR_HYPERCALL 0x40000001 158 159 /* MSR used to provide vcpu index */ 160 #define HV_X64_MSR_VP_INDEX 0x40000002 161 162 /* MSR used to reset the guest OS. */ 163 #define HV_X64_MSR_RESET 0x40000003 164 165 /* MSR used to provide vcpu runtime in 100ns units */ 166 #define HV_X64_MSR_VP_RUNTIME 0x40000010 167 168 /* MSR used to read the per-partition time reference counter */ 169 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020 170 171 /* A partition's reference time stamp counter (TSC) page */ 172 #define HV_X64_MSR_REFERENCE_TSC 0x40000021 173 174 /* MSR used to retrieve the TSC frequency */ 175 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022 176 177 /* MSR used to retrieve the local APIC timer frequency */ 178 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023 179 180 /* Define the virtual APIC registers */ 181 #define HV_X64_MSR_EOI 0x40000070 182 #define HV_X64_MSR_ICR 0x40000071 183 #define HV_X64_MSR_TPR 0x40000072 184 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073 185 186 /* Define synthetic interrupt controller model specific registers. */ 187 #define HV_X64_MSR_SCONTROL 0x40000080 188 #define HV_X64_MSR_SVERSION 0x40000081 189 #define HV_X64_MSR_SIEFP 0x40000082 190 #define HV_X64_MSR_SIMP 0x40000083 191 #define HV_X64_MSR_EOM 0x40000084 192 #define HV_X64_MSR_SINT0 0x40000090 193 #define HV_X64_MSR_SINT1 0x40000091 194 #define HV_X64_MSR_SINT2 0x40000092 195 #define HV_X64_MSR_SINT3 0x40000093 196 #define HV_X64_MSR_SINT4 0x40000094 197 #define HV_X64_MSR_SINT5 0x40000095 198 #define HV_X64_MSR_SINT6 0x40000096 199 #define HV_X64_MSR_SINT7 0x40000097 200 #define HV_X64_MSR_SINT8 0x40000098 201 #define HV_X64_MSR_SINT9 0x40000099 202 #define HV_X64_MSR_SINT10 0x4000009A 203 #define HV_X64_MSR_SINT11 0x4000009B 204 #define HV_X64_MSR_SINT12 0x4000009C 205 #define HV_X64_MSR_SINT13 0x4000009D 206 #define HV_X64_MSR_SINT14 0x4000009E 207 #define HV_X64_MSR_SINT15 0x4000009F 208 209 /* 210 * Synthetic Timer MSRs. Four timers per vcpu. 211 */ 212 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0 213 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1 214 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2 215 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3 216 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4 217 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5 218 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6 219 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7 220 221 /* Hyper-V guest idle MSR */ 222 #define HV_X64_MSR_GUEST_IDLE 0x400000F0 223 224 /* Hyper-V guest crash notification MSR's */ 225 #define HV_X64_MSR_CRASH_P0 0x40000100 226 #define HV_X64_MSR_CRASH_P1 0x40000101 227 #define HV_X64_MSR_CRASH_P2 0x40000102 228 #define HV_X64_MSR_CRASH_P3 0x40000103 229 #define HV_X64_MSR_CRASH_P4 0x40000104 230 #define HV_X64_MSR_CRASH_CTL 0x40000105 231 232 /* TSC emulation after migration */ 233 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106 234 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107 235 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108 236 237 /* TSC invariant control */ 238 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118 239 240 /* 241 * Declare the MSR used to setup pages used to communicate with the hypervisor. 242 */ 243 union hv_x64_msr_hypercall_contents { 244 u64 as_uint64; 245 struct { 246 u64 enable:1; 247 u64 reserved:11; 248 u64 guest_physical_address:52; 249 } __packed; 250 }; 251 252 struct hv_reenlightenment_control { 253 __u64 vector:8; 254 __u64 reserved1:8; 255 __u64 enabled:1; 256 __u64 reserved2:15; 257 __u64 target_vp:32; 258 } __packed; 259 260 struct hv_tsc_emulation_control { 261 __u64 enabled:1; 262 __u64 reserved:63; 263 } __packed; 264 265 struct hv_tsc_emulation_status { 266 __u64 inprogress:1; 267 __u64 reserved:63; 268 } __packed; 269 270 #define HV_X64_MSR_HYPERCALL_ENABLE 0x00000001 271 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT 12 272 #define HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_MASK \ 273 (~((1ull << HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT) - 1)) 274 275 #define HV_X64_MSR_CRASH_PARAMS \ 276 (1 + (HV_X64_MSR_CRASH_P4 - HV_X64_MSR_CRASH_P0)) 277 278 #define HV_IPI_LOW_VECTOR 0x10 279 #define HV_IPI_HIGH_VECTOR 0xff 280 281 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001 282 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12 283 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \ 284 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1)) 285 286 /* Hyper-V Enlightened VMCS version mask in nested features CPUID */ 287 #define HV_X64_ENLIGHTENED_VMCS_VERSION 0xff 288 289 #define HV_X64_MSR_TSC_REFERENCE_ENABLE 0x00000001 290 #define HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT 12 291 292 293 /* Define hypervisor message types. */ 294 enum hv_message_type { 295 HVMSG_NONE = 0x00000000, 296 297 /* Memory access messages. */ 298 HVMSG_UNMAPPED_GPA = 0x80000000, 299 HVMSG_GPA_INTERCEPT = 0x80000001, 300 301 /* Timer notification messages. */ 302 HVMSG_TIMER_EXPIRED = 0x80000010, 303 304 /* Error messages. */ 305 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020, 306 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021, 307 HVMSG_UNSUPPORTED_FEATURE = 0x80000022, 308 309 /* Trace buffer complete messages. */ 310 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040, 311 312 /* Platform-specific processor intercept messages. */ 313 HVMSG_X64_IOPORT_INTERCEPT = 0x80010000, 314 HVMSG_X64_MSR_INTERCEPT = 0x80010001, 315 HVMSG_X64_CPUID_INTERCEPT = 0x80010002, 316 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003, 317 HVMSG_X64_APIC_EOI = 0x80010004, 318 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005 319 }; 320 321 struct hv_nested_enlightenments_control { 322 struct { 323 __u32 directhypercall:1; 324 __u32 reserved:31; 325 } features; 326 struct { 327 __u32 reserved; 328 } hypercallControls; 329 } __packed; 330 331 /* Define virtual processor assist page structure. */ 332 struct hv_vp_assist_page { 333 __u32 apic_assist; 334 __u32 reserved1; 335 __u64 vtl_control[3]; 336 struct hv_nested_enlightenments_control nested_control; 337 __u8 enlighten_vmentry; 338 __u8 reserved2[7]; 339 __u64 current_nested_vmcs; 340 } __packed; 341 342 struct hv_enlightened_vmcs { 343 u32 revision_id; 344 u32 abort; 345 346 u16 host_es_selector; 347 u16 host_cs_selector; 348 u16 host_ss_selector; 349 u16 host_ds_selector; 350 u16 host_fs_selector; 351 u16 host_gs_selector; 352 u16 host_tr_selector; 353 354 u16 padding16_1; 355 356 u64 host_ia32_pat; 357 u64 host_ia32_efer; 358 359 u64 host_cr0; 360 u64 host_cr3; 361 u64 host_cr4; 362 363 u64 host_ia32_sysenter_esp; 364 u64 host_ia32_sysenter_eip; 365 u64 host_rip; 366 u32 host_ia32_sysenter_cs; 367 368 u32 pin_based_vm_exec_control; 369 u32 vm_exit_controls; 370 u32 secondary_vm_exec_control; 371 372 u64 io_bitmap_a; 373 u64 io_bitmap_b; 374 u64 msr_bitmap; 375 376 u16 guest_es_selector; 377 u16 guest_cs_selector; 378 u16 guest_ss_selector; 379 u16 guest_ds_selector; 380 u16 guest_fs_selector; 381 u16 guest_gs_selector; 382 u16 guest_ldtr_selector; 383 u16 guest_tr_selector; 384 385 u32 guest_es_limit; 386 u32 guest_cs_limit; 387 u32 guest_ss_limit; 388 u32 guest_ds_limit; 389 u32 guest_fs_limit; 390 u32 guest_gs_limit; 391 u32 guest_ldtr_limit; 392 u32 guest_tr_limit; 393 u32 guest_gdtr_limit; 394 u32 guest_idtr_limit; 395 396 u32 guest_es_ar_bytes; 397 u32 guest_cs_ar_bytes; 398 u32 guest_ss_ar_bytes; 399 u32 guest_ds_ar_bytes; 400 u32 guest_fs_ar_bytes; 401 u32 guest_gs_ar_bytes; 402 u32 guest_ldtr_ar_bytes; 403 u32 guest_tr_ar_bytes; 404 405 u64 guest_es_base; 406 u64 guest_cs_base; 407 u64 guest_ss_base; 408 u64 guest_ds_base; 409 u64 guest_fs_base; 410 u64 guest_gs_base; 411 u64 guest_ldtr_base; 412 u64 guest_tr_base; 413 u64 guest_gdtr_base; 414 u64 guest_idtr_base; 415 416 u64 padding64_1[3]; 417 418 u64 vm_exit_msr_store_addr; 419 u64 vm_exit_msr_load_addr; 420 u64 vm_entry_msr_load_addr; 421 422 u64 cr3_target_value0; 423 u64 cr3_target_value1; 424 u64 cr3_target_value2; 425 u64 cr3_target_value3; 426 427 u32 page_fault_error_code_mask; 428 u32 page_fault_error_code_match; 429 430 u32 cr3_target_count; 431 u32 vm_exit_msr_store_count; 432 u32 vm_exit_msr_load_count; 433 u32 vm_entry_msr_load_count; 434 435 u64 tsc_offset; 436 u64 virtual_apic_page_addr; 437 u64 vmcs_link_pointer; 438 439 u64 guest_ia32_debugctl; 440 u64 guest_ia32_pat; 441 u64 guest_ia32_efer; 442 443 u64 guest_pdptr0; 444 u64 guest_pdptr1; 445 u64 guest_pdptr2; 446 u64 guest_pdptr3; 447 448 u64 guest_pending_dbg_exceptions; 449 u64 guest_sysenter_esp; 450 u64 guest_sysenter_eip; 451 452 u32 guest_activity_state; 453 u32 guest_sysenter_cs; 454 455 u64 cr0_guest_host_mask; 456 u64 cr4_guest_host_mask; 457 u64 cr0_read_shadow; 458 u64 cr4_read_shadow; 459 u64 guest_cr0; 460 u64 guest_cr3; 461 u64 guest_cr4; 462 u64 guest_dr7; 463 464 u64 host_fs_base; 465 u64 host_gs_base; 466 u64 host_tr_base; 467 u64 host_gdtr_base; 468 u64 host_idtr_base; 469 u64 host_rsp; 470 471 u64 ept_pointer; 472 473 u16 virtual_processor_id; 474 u16 padding16_2[3]; 475 476 u64 padding64_2[5]; 477 u64 guest_physical_address; 478 479 u32 vm_instruction_error; 480 u32 vm_exit_reason; 481 u32 vm_exit_intr_info; 482 u32 vm_exit_intr_error_code; 483 u32 idt_vectoring_info_field; 484 u32 idt_vectoring_error_code; 485 u32 vm_exit_instruction_len; 486 u32 vmx_instruction_info; 487 488 u64 exit_qualification; 489 u64 exit_io_instruction_ecx; 490 u64 exit_io_instruction_esi; 491 u64 exit_io_instruction_edi; 492 u64 exit_io_instruction_eip; 493 494 u64 guest_linear_address; 495 u64 guest_rsp; 496 u64 guest_rflags; 497 498 u32 guest_interruptibility_info; 499 u32 cpu_based_vm_exec_control; 500 u32 exception_bitmap; 501 u32 vm_entry_controls; 502 u32 vm_entry_intr_info_field; 503 u32 vm_entry_exception_error_code; 504 u32 vm_entry_instruction_len; 505 u32 tpr_threshold; 506 507 u64 guest_rip; 508 509 u32 hv_clean_fields; 510 u32 hv_padding_32; 511 u32 hv_synthetic_controls; 512 struct { 513 u32 nested_flush_hypercall:1; 514 u32 msr_bitmap:1; 515 u32 reserved:30; 516 } __packed hv_enlightenments_control; 517 u32 hv_vp_id; 518 519 u64 hv_vm_id; 520 u64 partition_assist_page; 521 u64 padding64_4[4]; 522 u64 guest_bndcfgs; 523 u64 padding64_5[7]; 524 u64 xss_exit_bitmap; 525 u64 padding64_6[7]; 526 } __packed; 527 528 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_NONE 0 529 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_IO_BITMAP BIT(0) 530 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP BIT(1) 531 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP2 BIT(2) 532 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_GRP1 BIT(3) 533 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_PROC BIT(4) 534 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EVENT BIT(5) 535 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_ENTRY BIT(6) 536 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_EXCPN BIT(7) 537 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CRDR BIT(8) 538 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_CONTROL_XLAT BIT(9) 539 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_BASIC BIT(10) 540 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP1 BIT(11) 541 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_GUEST_GRP2 BIT(12) 542 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_POINTER BIT(13) 543 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_HOST_GRP1 BIT(14) 544 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ENLIGHTENMENTSCONTROL BIT(15) 545 546 #define HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL 0xFFFF 547 548 struct hv_partition_assist_pg { 549 u32 tlb_lock_count; 550 }; 551 552 553 #include <asm-generic/hyperv-tlfs.h> 554 555 #endif 556