1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018 Intel Corporation */ 3 4 #ifndef _IGC_H_ 5 #define _IGC_H_ 6 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/netdevice.h> 10 #include <linux/vmalloc.h> 11 #include <linux/ethtool.h> 12 #include <linux/sctp.h> 13 #include <linux/ptp_clock_kernel.h> 14 #include <linux/timecounter.h> 15 #include <linux/net_tstamp.h> 16 17 #include "igc_hw.h" 18 19 /* forward declaration */ 20 void igc_set_ethtool_ops(struct net_device *); 21 22 struct igc_adapter; 23 struct igc_ring; 24 25 void igc_up(struct igc_adapter *adapter); 26 void igc_down(struct igc_adapter *adapter); 27 int igc_setup_tx_resources(struct igc_ring *ring); 28 int igc_setup_rx_resources(struct igc_ring *ring); 29 void igc_free_tx_resources(struct igc_ring *ring); 30 void igc_free_rx_resources(struct igc_ring *ring); 31 unsigned int igc_get_max_rss_queues(struct igc_adapter *adapter); 32 void igc_set_flag_queue_pairs(struct igc_adapter *adapter, 33 const u32 max_rss_queues); 34 int igc_reinit_queues(struct igc_adapter *adapter); 35 void igc_write_rss_indir_tbl(struct igc_adapter *adapter); 36 bool igc_has_link(struct igc_adapter *adapter); 37 void igc_reset(struct igc_adapter *adapter); 38 int igc_set_spd_dplx(struct igc_adapter *adapter, u32 spd, u8 dplx); 39 int igc_add_mac_steering_filter(struct igc_adapter *adapter, 40 const u8 *addr, u8 queue, u8 flags); 41 int igc_del_mac_steering_filter(struct igc_adapter *adapter, 42 const u8 *addr, u8 queue, u8 flags); 43 void igc_update_stats(struct igc_adapter *adapter); 44 45 extern char igc_driver_name[]; 46 extern char igc_driver_version[]; 47 48 #define IGC_REGS_LEN 740 49 #define IGC_RETA_SIZE 128 50 51 /* flags controlling PTP/1588 function */ 52 #define IGC_PTP_ENABLED BIT(0) 53 54 /* Interrupt defines */ 55 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 56 #define IGC_FLAG_HAS_MSI BIT(0) 57 #define IGC_FLAG_QUEUE_PAIRS BIT(3) 58 #define IGC_FLAG_DMAC BIT(4) 59 #define IGC_FLAG_PTP BIT(8) 60 #define IGC_FLAG_NEED_LINK_UPDATE BIT(9) 61 #define IGC_FLAG_MEDIA_RESET BIT(10) 62 #define IGC_FLAG_MAS_ENABLE BIT(12) 63 #define IGC_FLAG_HAS_MSIX BIT(13) 64 #define IGC_FLAG_VLAN_PROMISC BIT(15) 65 #define IGC_FLAG_RX_LEGACY BIT(16) 66 67 #define IGC_FLAG_RSS_FIELD_IPV4_UDP BIT(6) 68 #define IGC_FLAG_RSS_FIELD_IPV6_UDP BIT(7) 69 70 #define IGC_MRQC_ENABLE_RSS_MQ 0x00000002 71 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 72 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 73 74 #define IGC_START_ITR 648 /* ~6000 ints/sec */ 75 #define IGC_4K_ITR 980 76 #define IGC_20K_ITR 196 77 #define IGC_70K_ITR 56 78 79 #define IGC_DEFAULT_ITR 3 /* dynamic */ 80 #define IGC_MAX_ITR_USECS 10000 81 #define IGC_MIN_ITR_USECS 10 82 #define NON_Q_VECTORS 1 83 #define MAX_MSIX_ENTRIES 10 84 85 /* TX/RX descriptor defines */ 86 #define IGC_DEFAULT_TXD 256 87 #define IGC_DEFAULT_TX_WORK 128 88 #define IGC_MIN_TXD 80 89 #define IGC_MAX_TXD 4096 90 91 #define IGC_DEFAULT_RXD 256 92 #define IGC_MIN_RXD 80 93 #define IGC_MAX_RXD 4096 94 95 /* Transmit and receive queues */ 96 #define IGC_MAX_RX_QUEUES 4 97 #define IGC_MAX_TX_QUEUES 4 98 99 #define MAX_Q_VECTORS 8 100 #define MAX_STD_JUMBO_FRAME_SIZE 9216 101 102 /* Supported Rx Buffer Sizes */ 103 #define IGC_RXBUFFER_256 256 104 #define IGC_RXBUFFER_2048 2048 105 #define IGC_RXBUFFER_3072 3072 106 107 #define AUTO_ALL_MODES 0 108 #define IGC_RX_HDR_LEN IGC_RXBUFFER_256 109 110 /* Transmit and receive latency (for PTP timestamps) */ 111 /* FIXME: These values were estimated using the ones that i210 has as 112 * basis, they seem to provide good numbers with ptp4l/phc2sys, but we 113 * need to confirm them. 114 */ 115 #define IGC_I225_TX_LATENCY_10 9542 116 #define IGC_I225_TX_LATENCY_100 1024 117 #define IGC_I225_TX_LATENCY_1000 178 118 #define IGC_I225_TX_LATENCY_2500 64 119 #define IGC_I225_RX_LATENCY_10 20662 120 #define IGC_I225_RX_LATENCY_100 2213 121 #define IGC_I225_RX_LATENCY_1000 448 122 #define IGC_I225_RX_LATENCY_2500 160 123 124 /* RX and TX descriptor control thresholds. 125 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 126 * descriptors available in its onboard memory. 127 * Setting this to 0 disables RX descriptor prefetch. 128 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 129 * available in host memory. 130 * If PTHRESH is 0, this should also be 0. 131 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 132 * descriptors until either it has this many to write back, or the 133 * ITR timer expires. 134 */ 135 #define IGC_RX_PTHRESH 8 136 #define IGC_RX_HTHRESH 8 137 #define IGC_TX_PTHRESH 8 138 #define IGC_TX_HTHRESH 1 139 #define IGC_RX_WTHRESH 4 140 #define IGC_TX_WTHRESH 16 141 142 #define IGC_RX_DMA_ATTR \ 143 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 144 145 #define IGC_TS_HDR_LEN 16 146 147 #define IGC_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 148 149 #if (PAGE_SIZE < 8192) 150 #define IGC_MAX_FRAME_BUILD_SKB \ 151 (SKB_WITH_OVERHEAD(IGC_RXBUFFER_2048) - IGC_SKB_PAD - IGC_TS_HDR_LEN) 152 #else 153 #define IGC_MAX_FRAME_BUILD_SKB (IGC_RXBUFFER_2048 - IGC_TS_HDR_LEN) 154 #endif 155 156 /* How many Rx Buffers do we bundle into one write to the hardware ? */ 157 #define IGC_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 158 159 /* VLAN info */ 160 #define IGC_TX_FLAGS_VLAN_MASK 0xffff0000 161 162 /* igc_test_staterr - tests bits within Rx descriptor status and error fields */ 163 static inline __le32 igc_test_staterr(union igc_adv_rx_desc *rx_desc, 164 const u32 stat_err_bits) 165 { 166 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 167 } 168 169 enum igc_state_t { 170 __IGC_TESTING, 171 __IGC_RESETTING, 172 __IGC_DOWN, 173 __IGC_PTP_TX_IN_PROGRESS, 174 }; 175 176 enum igc_tx_flags { 177 /* cmd_type flags */ 178 IGC_TX_FLAGS_VLAN = 0x01, 179 IGC_TX_FLAGS_TSO = 0x02, 180 IGC_TX_FLAGS_TSTAMP = 0x04, 181 182 /* olinfo flags */ 183 IGC_TX_FLAGS_IPV4 = 0x10, 184 IGC_TX_FLAGS_CSUM = 0x20, 185 }; 186 187 enum igc_boards { 188 board_base, 189 }; 190 191 /* The largest size we can write to the descriptor is 65535. In order to 192 * maintain a power of two alignment we have to limit ourselves to 32K. 193 */ 194 #define IGC_MAX_TXD_PWR 15 195 #define IGC_MAX_DATA_PER_TXD BIT(IGC_MAX_TXD_PWR) 196 197 /* Tx Descriptors needed, worst case */ 198 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGC_MAX_DATA_PER_TXD) 199 #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 200 201 /* wrapper around a pointer to a socket buffer, 202 * so a DMA handle can be stored along with the buffer 203 */ 204 struct igc_tx_buffer { 205 union igc_adv_tx_desc *next_to_watch; 206 unsigned long time_stamp; 207 struct sk_buff *skb; 208 unsigned int bytecount; 209 u16 gso_segs; 210 __be16 protocol; 211 212 DEFINE_DMA_UNMAP_ADDR(dma); 213 DEFINE_DMA_UNMAP_LEN(len); 214 u32 tx_flags; 215 }; 216 217 struct igc_rx_buffer { 218 dma_addr_t dma; 219 struct page *page; 220 #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536) 221 __u32 page_offset; 222 #else 223 __u16 page_offset; 224 #endif 225 __u16 pagecnt_bias; 226 }; 227 228 struct igc_tx_queue_stats { 229 u64 packets; 230 u64 bytes; 231 u64 restart_queue; 232 u64 restart_queue2; 233 }; 234 235 struct igc_rx_queue_stats { 236 u64 packets; 237 u64 bytes; 238 u64 drops; 239 u64 csum_err; 240 u64 alloc_failed; 241 }; 242 243 struct igc_rx_packet_stats { 244 u64 ipv4_packets; /* IPv4 headers processed */ 245 u64 ipv4e_packets; /* IPv4E headers with extensions processed */ 246 u64 ipv6_packets; /* IPv6 headers processed */ 247 u64 ipv6e_packets; /* IPv6E headers with extensions processed */ 248 u64 tcp_packets; /* TCP headers processed */ 249 u64 udp_packets; /* UDP headers processed */ 250 u64 sctp_packets; /* SCTP headers processed */ 251 u64 nfs_packets; /* NFS headers processe */ 252 u64 other_packets; 253 }; 254 255 struct igc_ring_container { 256 struct igc_ring *ring; /* pointer to linked list of rings */ 257 unsigned int total_bytes; /* total bytes processed this int */ 258 unsigned int total_packets; /* total packets processed this int */ 259 u16 work_limit; /* total work allowed per interrupt */ 260 u8 count; /* total number of rings in vector */ 261 u8 itr; /* current ITR setting for ring */ 262 }; 263 264 struct igc_ring { 265 struct igc_q_vector *q_vector; /* backlink to q_vector */ 266 struct net_device *netdev; /* back pointer to net_device */ 267 struct device *dev; /* device for dma mapping */ 268 union { /* array of buffer info structs */ 269 struct igc_tx_buffer *tx_buffer_info; 270 struct igc_rx_buffer *rx_buffer_info; 271 }; 272 void *desc; /* descriptor ring memory */ 273 unsigned long flags; /* ring specific flags */ 274 void __iomem *tail; /* pointer to ring tail register */ 275 dma_addr_t dma; /* phys address of the ring */ 276 unsigned int size; /* length of desc. ring in bytes */ 277 278 u16 count; /* number of desc. in the ring */ 279 u8 queue_index; /* logical index of the ring*/ 280 u8 reg_idx; /* physical index of the ring */ 281 bool launchtime_enable; /* true if LaunchTime is enabled */ 282 283 /* everything past this point are written often */ 284 u16 next_to_clean; 285 u16 next_to_use; 286 u16 next_to_alloc; 287 288 union { 289 /* TX */ 290 struct { 291 struct igc_tx_queue_stats tx_stats; 292 struct u64_stats_sync tx_syncp; 293 struct u64_stats_sync tx_syncp2; 294 }; 295 /* RX */ 296 struct { 297 struct igc_rx_queue_stats rx_stats; 298 struct igc_rx_packet_stats pkt_stats; 299 struct u64_stats_sync rx_syncp; 300 struct sk_buff *skb; 301 }; 302 }; 303 } ____cacheline_internodealigned_in_smp; 304 305 struct igc_q_vector { 306 struct igc_adapter *adapter; /* backlink */ 307 void __iomem *itr_register; 308 u32 eims_value; /* EIMS mask value */ 309 310 u16 itr_val; 311 u8 set_itr; 312 313 struct igc_ring_container rx, tx; 314 315 struct napi_struct napi; 316 317 struct rcu_head rcu; /* to avoid race with update stats on free */ 318 char name[IFNAMSIZ + 9]; 319 struct net_device poll_dev; 320 321 /* for dynamic allocation of rings associated with this q_vector */ 322 struct igc_ring ring[0] ____cacheline_internodealigned_in_smp; 323 }; 324 325 #define MAX_ETYPE_FILTER (4 - 1) 326 327 enum igc_filter_match_flags { 328 IGC_FILTER_FLAG_ETHER_TYPE = 0x1, 329 IGC_FILTER_FLAG_VLAN_TCI = 0x2, 330 IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4, 331 IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8, 332 }; 333 334 /* RX network flow classification data structure */ 335 struct igc_nfc_input { 336 /* Byte layout in order, all values with MSB first: 337 * match_flags - 1 byte 338 * etype - 2 bytes 339 * vlan_tci - 2 bytes 340 */ 341 u8 match_flags; 342 __be16 etype; 343 __be16 vlan_tci; 344 u8 src_addr[ETH_ALEN]; 345 u8 dst_addr[ETH_ALEN]; 346 }; 347 348 struct igc_nfc_filter { 349 struct hlist_node nfc_node; 350 struct igc_nfc_input filter; 351 unsigned long cookie; 352 u16 etype_reg_index; 353 u16 sw_idx; 354 u16 action; 355 }; 356 357 struct igc_mac_addr { 358 u8 addr[ETH_ALEN]; 359 u8 queue; 360 u8 state; /* bitmask */ 361 }; 362 363 #define IGC_MAC_STATE_DEFAULT 0x1 364 #define IGC_MAC_STATE_IN_USE 0x2 365 #define IGC_MAC_STATE_SRC_ADDR 0x4 366 #define IGC_MAC_STATE_QUEUE_STEERING 0x8 367 368 #define IGC_MAX_RXNFC_FILTERS 16 369 370 /* Board specific private data structure */ 371 struct igc_adapter { 372 struct net_device *netdev; 373 374 unsigned long state; 375 unsigned int flags; 376 unsigned int num_q_vectors; 377 378 struct msix_entry *msix_entries; 379 380 /* TX */ 381 u16 tx_work_limit; 382 u32 tx_timeout_count; 383 int num_tx_queues; 384 struct igc_ring *tx_ring[IGC_MAX_TX_QUEUES]; 385 386 /* RX */ 387 int num_rx_queues; 388 struct igc_ring *rx_ring[IGC_MAX_RX_QUEUES]; 389 390 struct timer_list watchdog_timer; 391 struct timer_list dma_err_timer; 392 struct timer_list phy_info_timer; 393 394 u32 wol; 395 u32 en_mng_pt; 396 u16 link_speed; 397 u16 link_duplex; 398 399 u8 port_num; 400 401 u8 __iomem *io_addr; 402 /* Interrupt Throttle Rate */ 403 u32 rx_itr_setting; 404 u32 tx_itr_setting; 405 406 struct work_struct reset_task; 407 struct work_struct watchdog_task; 408 struct work_struct dma_err_task; 409 bool fc_autoneg; 410 411 u8 tx_timeout_factor; 412 413 int msg_enable; 414 u32 max_frame_size; 415 u32 min_frame_size; 416 417 /* OS defined structs */ 418 struct pci_dev *pdev; 419 /* lock for statistics */ 420 spinlock_t stats64_lock; 421 struct rtnl_link_stats64 stats64; 422 423 /* structs defined in igc_hw.h */ 424 struct igc_hw hw; 425 struct igc_hw_stats stats; 426 427 struct igc_q_vector *q_vector[MAX_Q_VECTORS]; 428 u32 eims_enable_mask; 429 u32 eims_other; 430 431 u16 tx_ring_count; 432 u16 rx_ring_count; 433 434 u32 tx_hwtstamp_timeouts; 435 u32 tx_hwtstamp_skipped; 436 u32 rx_hwtstamp_cleared; 437 438 u32 rss_queues; 439 u32 rss_indir_tbl_init; 440 441 /* RX network flow classification support */ 442 struct hlist_head nfc_filter_list; 443 struct hlist_head cls_flower_list; 444 unsigned int nfc_filter_count; 445 446 /* lock for RX network flow classification filter */ 447 spinlock_t nfc_lock; 448 bool etype_bitmap[MAX_ETYPE_FILTER]; 449 450 struct igc_mac_addr *mac_table; 451 452 u8 rss_indir_tbl[IGC_RETA_SIZE]; 453 454 unsigned long link_check_timeout; 455 struct igc_info ei; 456 457 struct ptp_clock *ptp_clock; 458 struct ptp_clock_info ptp_caps; 459 struct work_struct ptp_tx_work; 460 struct sk_buff *ptp_tx_skb; 461 struct hwtstamp_config tstamp_config; 462 unsigned long ptp_tx_start; 463 unsigned long last_rx_ptp_check; 464 unsigned long last_rx_timestamp; 465 unsigned int ptp_flags; 466 /* System time value lock */ 467 spinlock_t tmreg_lock; 468 struct cyclecounter cc; 469 struct timecounter tc; 470 }; 471 472 /* igc_desc_unused - calculate if we have unused descriptors */ 473 static inline u16 igc_desc_unused(const struct igc_ring *ring) 474 { 475 u16 ntc = ring->next_to_clean; 476 u16 ntu = ring->next_to_use; 477 478 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1; 479 } 480 481 static inline s32 igc_get_phy_info(struct igc_hw *hw) 482 { 483 if (hw->phy.ops.get_phy_info) 484 return hw->phy.ops.get_phy_info(hw); 485 486 return 0; 487 } 488 489 static inline s32 igc_reset_phy(struct igc_hw *hw) 490 { 491 if (hw->phy.ops.reset) 492 return hw->phy.ops.reset(hw); 493 494 return 0; 495 } 496 497 static inline struct netdev_queue *txring_txq(const struct igc_ring *tx_ring) 498 { 499 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 500 } 501 502 enum igc_ring_flags_t { 503 IGC_RING_FLAG_RX_3K_BUFFER, 504 IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, 505 IGC_RING_FLAG_RX_SCTP_CSUM, 506 IGC_RING_FLAG_RX_LB_VLAN_BSWAP, 507 IGC_RING_FLAG_TX_CTX_IDX, 508 IGC_RING_FLAG_TX_DETECT_HANG 509 }; 510 511 #define ring_uses_large_buffer(ring) \ 512 test_bit(IGC_RING_FLAG_RX_3K_BUFFER, &(ring)->flags) 513 514 #define ring_uses_build_skb(ring) \ 515 test_bit(IGC_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags) 516 517 static inline unsigned int igc_rx_bufsz(struct igc_ring *ring) 518 { 519 #if (PAGE_SIZE < 8192) 520 if (ring_uses_large_buffer(ring)) 521 return IGC_RXBUFFER_3072; 522 523 if (ring_uses_build_skb(ring)) 524 return IGC_MAX_FRAME_BUILD_SKB + IGC_TS_HDR_LEN; 525 #endif 526 return IGC_RXBUFFER_2048; 527 } 528 529 static inline unsigned int igc_rx_pg_order(struct igc_ring *ring) 530 { 531 #if (PAGE_SIZE < 8192) 532 if (ring_uses_large_buffer(ring)) 533 return 1; 534 #endif 535 return 0; 536 } 537 538 static inline s32 igc_read_phy_reg(struct igc_hw *hw, u32 offset, u16 *data) 539 { 540 if (hw->phy.ops.read_reg) 541 return hw->phy.ops.read_reg(hw, offset, data); 542 543 return 0; 544 } 545 546 /* forward declaration */ 547 void igc_reinit_locked(struct igc_adapter *); 548 int igc_add_filter(struct igc_adapter *adapter, 549 struct igc_nfc_filter *input); 550 int igc_erase_filter(struct igc_adapter *adapter, 551 struct igc_nfc_filter *input); 552 553 void igc_ptp_init(struct igc_adapter *adapter); 554 void igc_ptp_reset(struct igc_adapter *adapter); 555 void igc_ptp_stop(struct igc_adapter *adapter); 556 void igc_ptp_rx_rgtstamp(struct igc_q_vector *q_vector, struct sk_buff *skb); 557 void igc_ptp_rx_pktstamp(struct igc_q_vector *q_vector, void *va, 558 struct sk_buff *skb); 559 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr); 560 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr); 561 void igc_ptp_tx_hang(struct igc_adapter *adapter); 562 563 #define igc_rx_pg_size(_ring) (PAGE_SIZE << igc_rx_pg_order(_ring)) 564 565 #define IGC_TXD_DCMD (IGC_ADVTXD_DCMD_EOP | IGC_ADVTXD_DCMD_RS) 566 567 #define IGC_RX_DESC(R, i) \ 568 (&(((union igc_adv_rx_desc *)((R)->desc))[i])) 569 #define IGC_TX_DESC(R, i) \ 570 (&(((union igc_adv_tx_desc *)((R)->desc))[i])) 571 #define IGC_TX_CTXTDESC(R, i) \ 572 (&(((struct igc_adv_tx_context_desc *)((R)->desc))[i])) 573 574 #endif /* _IGC_H_ */ 575